| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.2055080796 |
|
|
Sep 09 11:14:07 AM UTC 24 |
Sep 09 11:14:09 AM UTC 24 |
18018450 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2656433027 |
|
|
Sep 09 11:13:38 AM UTC 24 |
Sep 09 11:14:10 AM UTC 24 |
29496756402 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.561155593 |
|
|
Sep 09 11:14:08 AM UTC 24 |
Sep 09 11:14:11 AM UTC 24 |
14803390 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.358203105 |
|
|
Sep 09 11:12:47 AM UTC 24 |
Sep 09 11:14:12 AM UTC 24 |
8153364187 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.316353147 |
|
|
Sep 09 11:13:56 AM UTC 24 |
Sep 09 11:14:13 AM UTC 24 |
1897020707 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.574816759 |
|
|
Sep 09 11:14:11 AM UTC 24 |
Sep 09 11:14:14 AM UTC 24 |
23949738 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2206130055 |
|
|
Sep 09 11:14:11 AM UTC 24 |
Sep 09 11:14:14 AM UTC 24 |
127974380 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2822507879 |
|
|
Sep 09 11:11:47 AM UTC 24 |
Sep 09 11:14:16 AM UTC 24 |
92576269502 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.396826686 |
|
|
Sep 09 11:14:13 AM UTC 24 |
Sep 09 11:14:16 AM UTC 24 |
646988840 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3348974283 |
|
|
Sep 09 11:14:02 AM UTC 24 |
Sep 09 11:14:19 AM UTC 24 |
740898848 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3435882114 |
|
|
Sep 09 11:14:15 AM UTC 24 |
Sep 09 11:14:20 AM UTC 24 |
72909414 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.3645382703 |
|
|
Sep 09 11:14:15 AM UTC 24 |
Sep 09 11:14:20 AM UTC 24 |
798652226 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2159685135 |
|
|
Sep 09 11:14:04 AM UTC 24 |
Sep 09 11:14:21 AM UTC 24 |
3915296596 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.2007532956 |
|
|
Sep 09 11:13:57 AM UTC 24 |
Sep 09 11:14:23 AM UTC 24 |
5653312676 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1125418101 |
|
|
Sep 09 11:14:21 AM UTC 24 |
Sep 09 11:14:23 AM UTC 24 |
40806401 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.777645387 |
|
|
Sep 09 11:13:07 AM UTC 24 |
Sep 09 11:14:24 AM UTC 24 |
25134236337 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1533536485 |
|
|
Sep 09 11:14:20 AM UTC 24 |
Sep 09 11:14:24 AM UTC 24 |
33113715 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.967137979 |
|
|
Sep 09 11:14:02 AM UTC 24 |
Sep 09 11:14:25 AM UTC 24 |
3952261259 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.3842030158 |
|
|
Sep 09 11:11:30 AM UTC 24 |
Sep 09 11:14:26 AM UTC 24 |
38943419927 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.1135505347 |
|
|
Sep 09 11:14:24 AM UTC 24 |
Sep 09 11:14:27 AM UTC 24 |
32603496 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.496952200 |
|
|
Sep 09 11:13:57 AM UTC 24 |
Sep 09 11:14:27 AM UTC 24 |
18705115385 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3896788448 |
|
|
Sep 09 11:14:26 AM UTC 24 |
Sep 09 11:14:28 AM UTC 24 |
37195815 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1903182723 |
|
|
Sep 09 11:14:26 AM UTC 24 |
Sep 09 11:14:28 AM UTC 24 |
185958624 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.2544562250 |
|
|
Sep 09 11:14:27 AM UTC 24 |
Sep 09 11:14:29 AM UTC 24 |
18814525 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3813457105 |
|
|
Sep 09 11:14:05 AM UTC 24 |
Sep 09 11:14:30 AM UTC 24 |
864419315 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.2981450425 |
|
|
Sep 09 11:14:10 AM UTC 24 |
Sep 09 11:14:30 AM UTC 24 |
4072220716 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.52370703 |
|
|
Sep 09 11:14:29 AM UTC 24 |
Sep 09 11:14:31 AM UTC 24 |
17222462 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1714281701 |
|
|
Sep 09 11:14:29 AM UTC 24 |
Sep 09 11:14:32 AM UTC 24 |
313754736 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.235103511 |
|
|
Sep 09 11:14:15 AM UTC 24 |
Sep 09 11:14:34 AM UTC 24 |
2564776474 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.1822712359 |
|
|
Sep 09 11:14:17 AM UTC 24 |
Sep 09 11:14:35 AM UTC 24 |
2566263615 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.4006718134 |
|
|
Sep 09 11:11:11 AM UTC 24 |
Sep 09 11:14:36 AM UTC 24 |
16532879273 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2795896818 |
|
|
Sep 09 11:14:28 AM UTC 24 |
Sep 09 11:14:36 AM UTC 24 |
509481973 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.2705034249 |
|
|
Sep 09 11:14:05 AM UTC 24 |
Sep 09 11:14:36 AM UTC 24 |
20335445442 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.3087333884 |
|
|
Sep 09 11:14:31 AM UTC 24 |
Sep 09 11:14:38 AM UTC 24 |
989080655 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.4169301750 |
|
|
Sep 09 11:15:44 AM UTC 24 |
Sep 09 11:15:46 AM UTC 24 |
18704093 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2317512802 |
|
|
Sep 09 11:14:22 AM UTC 24 |
Sep 09 11:14:38 AM UTC 24 |
1501194580 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.1998394552 |
|
|
Sep 09 11:14:37 AM UTC 24 |
Sep 09 11:14:41 AM UTC 24 |
230962329 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1538459734 |
|
|
Sep 09 11:14:31 AM UTC 24 |
Sep 09 11:14:41 AM UTC 24 |
358015874 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.649579908 |
|
|
Sep 09 11:14:21 AM UTC 24 |
Sep 09 11:14:41 AM UTC 24 |
9246434000 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1258984009 |
|
|
Sep 09 11:14:34 AM UTC 24 |
Sep 09 11:14:43 AM UTC 24 |
1163369340 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.821944746 |
|
|
Sep 09 11:14:30 AM UTC 24 |
Sep 09 11:14:43 AM UTC 24 |
23973979382 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.2377883817 |
|
|
Sep 09 11:13:52 AM UTC 24 |
Sep 09 11:14:44 AM UTC 24 |
9870427300 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.2071916711 |
|
|
Sep 09 11:14:42 AM UTC 24 |
Sep 09 11:14:44 AM UTC 24 |
20380583 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.4079061219 |
|
|
Sep 09 11:14:42 AM UTC 24 |
Sep 09 11:14:44 AM UTC 24 |
24746200 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1381234974 |
|
|
Sep 09 11:14:44 AM UTC 24 |
Sep 09 11:14:47 AM UTC 24 |
175083430 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.2310755800 |
|
|
Sep 09 11:14:45 AM UTC 24 |
Sep 09 11:14:48 AM UTC 24 |
77594950 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3797998444 |
|
|
Sep 09 11:14:43 AM UTC 24 |
Sep 09 11:14:49 AM UTC 24 |
597602158 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2636297510 |
|
|
Sep 09 11:14:38 AM UTC 24 |
Sep 09 11:14:50 AM UTC 24 |
1128125645 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3279480157 |
|
|
Sep 09 11:12:35 AM UTC 24 |
Sep 09 11:14:50 AM UTC 24 |
7544736334 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.1625717283 |
|
|
Sep 09 11:13:09 AM UTC 24 |
Sep 09 11:14:50 AM UTC 24 |
19817166758 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.2704222665 |
|
|
Sep 09 11:14:06 AM UTC 24 |
Sep 09 11:14:51 AM UTC 24 |
3116756767 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.1569401996 |
|
|
Sep 09 11:14:32 AM UTC 24 |
Sep 09 11:14:51 AM UTC 24 |
2951353045 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3127620724 |
|
|
Sep 09 11:13:46 AM UTC 24 |
Sep 09 11:14:52 AM UTC 24 |
5933912521 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2361550844 |
|
|
Sep 09 11:14:50 AM UTC 24 |
Sep 09 11:14:53 AM UTC 24 |
82734275 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.957979732 |
|
|
Sep 09 11:14:51 AM UTC 24 |
Sep 09 11:14:55 AM UTC 24 |
84290913 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.43544173 |
|
|
Sep 09 11:14:28 AM UTC 24 |
Sep 09 11:14:57 AM UTC 24 |
8352315362 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.334332697 |
|
|
Sep 09 11:12:35 AM UTC 24 |
Sep 09 11:15:01 AM UTC 24 |
9093753591 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3412284193 |
|
|
Sep 09 11:14:48 AM UTC 24 |
Sep 09 11:15:01 AM UTC 24 |
5214080391 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.1063777631 |
|
|
Sep 09 11:14:51 AM UTC 24 |
Sep 09 11:15:02 AM UTC 24 |
4303131638 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.3686914102 |
|
|
Sep 09 11:14:52 AM UTC 24 |
Sep 09 11:15:04 AM UTC 24 |
571972803 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.131789396 |
|
|
Sep 09 11:14:51 AM UTC 24 |
Sep 09 11:15:04 AM UTC 24 |
4423576119 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.1130330821 |
|
|
Sep 09 11:15:02 AM UTC 24 |
Sep 09 11:15:04 AM UTC 24 |
12692095 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.1040838806 |
|
|
Sep 09 11:15:02 AM UTC 24 |
Sep 09 11:15:04 AM UTC 24 |
18458186 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.2189631222 |
|
|
Sep 09 11:14:32 AM UTC 24 |
Sep 09 11:15:04 AM UTC 24 |
7750814285 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.3131433569 |
|
|
Sep 09 11:15:03 AM UTC 24 |
Sep 09 11:15:05 AM UTC 24 |
142079145 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3283319915 |
|
|
Sep 09 11:10:41 AM UTC 24 |
Sep 09 11:15:06 AM UTC 24 |
152062622211 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.96185931 |
|
|
Sep 09 11:15:05 AM UTC 24 |
Sep 09 11:15:07 AM UTC 24 |
173325970 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2602267574 |
|
|
Sep 09 11:14:45 AM UTC 24 |
Sep 09 11:15:07 AM UTC 24 |
4358157419 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.1169105503 |
|
|
Sep 09 11:15:05 AM UTC 24 |
Sep 09 11:15:07 AM UTC 24 |
28662570 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.2650051901 |
|
|
Sep 09 11:12:17 AM UTC 24 |
Sep 09 11:15:07 AM UTC 24 |
166137643831 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.743528537 |
|
|
Sep 09 11:14:39 AM UTC 24 |
Sep 09 11:15:07 AM UTC 24 |
4799238152 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.772352231 |
|
|
Sep 09 11:13:40 AM UTC 24 |
Sep 09 11:15:09 AM UTC 24 |
12325801680 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.2684381684 |
|
|
Sep 09 11:10:42 AM UTC 24 |
Sep 09 11:15:11 AM UTC 24 |
25930661749 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.785621988 |
|
|
Sep 09 11:15:10 AM UTC 24 |
Sep 09 11:15:12 AM UTC 24 |
124450254 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2890802315 |
|
|
Sep 09 11:15:05 AM UTC 24 |
Sep 09 11:15:13 AM UTC 24 |
347344487 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1987885006 |
|
|
Sep 09 11:15:08 AM UTC 24 |
Sep 09 11:15:13 AM UTC 24 |
89721012 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.573683732 |
|
|
Sep 09 11:15:05 AM UTC 24 |
Sep 09 11:15:14 AM UTC 24 |
229336184 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.708308632 |
|
|
Sep 09 11:15:07 AM UTC 24 |
Sep 09 11:15:15 AM UTC 24 |
575673366 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.120201271 |
|
|
Sep 09 11:15:08 AM UTC 24 |
Sep 09 11:15:16 AM UTC 24 |
327485127 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.4061944472 |
|
|
Sep 09 11:08:27 AM UTC 24 |
Sep 09 11:15:16 AM UTC 24 |
80522003608 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.718341492 |
|
|
Sep 09 11:15:14 AM UTC 24 |
Sep 09 11:15:16 AM UTC 24 |
12150224 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.1487835572 |
|
|
Sep 09 11:15:14 AM UTC 24 |
Sep 09 11:15:16 AM UTC 24 |
69964675 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.1912608350 |
|
|
Sep 09 11:15:08 AM UTC 24 |
Sep 09 11:15:17 AM UTC 24 |
104542065 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1804610063 |
|
|
Sep 09 11:15:09 AM UTC 24 |
Sep 09 11:15:17 AM UTC 24 |
2376484513 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.654863100 |
|
|
Sep 09 11:15:17 AM UTC 24 |
Sep 09 11:15:20 AM UTC 24 |
36324731 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.1023929177 |
|
|
Sep 09 11:14:17 AM UTC 24 |
Sep 09 11:15:20 AM UTC 24 |
38915336896 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.78659330 |
|
|
Sep 09 11:15:06 AM UTC 24 |
Sep 09 11:15:21 AM UTC 24 |
4989794361 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.2989191243 |
|
|
Sep 09 11:15:17 AM UTC 24 |
Sep 09 11:15:21 AM UTC 24 |
30732535 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.3022347685 |
|
|
Sep 09 11:14:44 AM UTC 24 |
Sep 09 11:15:23 AM UTC 24 |
18977532242 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.751838071 |
|
|
Sep 09 11:11:49 AM UTC 24 |
Sep 09 11:15:24 AM UTC 24 |
14577342348 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.3652321583 |
|
|
Sep 09 11:15:19 AM UTC 24 |
Sep 09 11:15:25 AM UTC 24 |
334450234 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.205736685 |
|
|
Sep 09 11:15:22 AM UTC 24 |
Sep 09 11:15:26 AM UTC 24 |
330791212 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.4229931814 |
|
|
Sep 09 11:14:38 AM UTC 24 |
Sep 09 11:15:28 AM UTC 24 |
5845726952 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.2836909441 |
|
|
Sep 09 11:15:15 AM UTC 24 |
Sep 09 11:15:28 AM UTC 24 |
7259500670 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.1710102096 |
|
|
Sep 09 11:14:50 AM UTC 24 |
Sep 09 11:15:28 AM UTC 24 |
6525007480 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2713732088 |
|
|
Sep 09 11:15:17 AM UTC 24 |
Sep 09 11:15:30 AM UTC 24 |
2724937265 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2160827623 |
|
|
Sep 09 11:15:25 AM UTC 24 |
Sep 09 11:15:31 AM UTC 24 |
109810871 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.3341397667 |
|
|
Sep 09 11:15:28 AM UTC 24 |
Sep 09 11:15:31 AM UTC 24 |
362210746 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.4247796152 |
|
|
Sep 09 11:15:29 AM UTC 24 |
Sep 09 11:15:32 AM UTC 24 |
37478622 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.2313853579 |
|
|
Sep 09 11:15:19 AM UTC 24 |
Sep 09 11:15:32 AM UTC 24 |
17517716474 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2120574980 |
|
|
Sep 09 11:13:22 AM UTC 24 |
Sep 09 11:15:32 AM UTC 24 |
32067229940 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1856681849 |
|
|
Sep 09 11:12:02 AM UTC 24 |
Sep 09 11:15:33 AM UTC 24 |
21101594559 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.3537007406 |
|
|
Sep 09 11:15:05 AM UTC 24 |
Sep 09 11:15:33 AM UTC 24 |
3517799213 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.1362426874 |
|
|
Sep 09 11:15:31 AM UTC 24 |
Sep 09 11:15:33 AM UTC 24 |
33902780 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.294442590 |
|
|
Sep 09 11:15:22 AM UTC 24 |
Sep 09 11:15:35 AM UTC 24 |
822301303 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.1616032158 |
|
|
Sep 09 11:15:17 AM UTC 24 |
Sep 09 11:15:35 AM UTC 24 |
6320839185 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3196110826 |
|
|
Sep 09 11:15:33 AM UTC 24 |
Sep 09 11:15:35 AM UTC 24 |
35403403 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.938035949 |
|
|
Sep 09 11:15:33 AM UTC 24 |
Sep 09 11:15:37 AM UTC 24 |
1548565793 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1723156241 |
|
|
Sep 09 11:15:32 AM UTC 24 |
Sep 09 11:15:38 AM UTC 24 |
1415710191 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3504591737 |
|
|
Sep 09 11:15:33 AM UTC 24 |
Sep 09 11:15:40 AM UTC 24 |
901367561 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1568656254 |
|
|
Sep 09 11:15:34 AM UTC 24 |
Sep 09 11:15:42 AM UTC 24 |
378035286 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.2591379044 |
|
|
Sep 09 11:15:36 AM UTC 24 |
Sep 09 11:15:42 AM UTC 24 |
1628107125 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.1405432378 |
|
|
Sep 09 11:15:34 AM UTC 24 |
Sep 09 11:15:42 AM UTC 24 |
163905875 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.3268330918 |
|
|
Sep 09 11:13:44 AM UTC 24 |
Sep 09 11:15:43 AM UTC 24 |
42823648014 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.70286455 |
|
|
Sep 09 11:15:22 AM UTC 24 |
Sep 09 11:15:44 AM UTC 24 |
7032681051 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.639880636 |
|
|
Sep 09 11:15:36 AM UTC 24 |
Sep 09 11:15:44 AM UTC 24 |
286830011 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.4065725509 |
|
|
Sep 09 11:15:39 AM UTC 24 |
Sep 09 11:15:45 AM UTC 24 |
106281183 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.3864314766 |
|
|
Sep 09 11:15:44 AM UTC 24 |
Sep 09 11:15:46 AM UTC 24 |
41870748 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.62385091 |
|
|
Sep 09 11:15:32 AM UTC 24 |
Sep 09 11:15:47 AM UTC 24 |
2134950767 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.2668003548 |
|
|
Sep 09 11:12:48 AM UTC 24 |
Sep 09 11:15:48 AM UTC 24 |
37224107674 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2196503109 |
|
|
Sep 09 11:16:45 AM UTC 24 |
Sep 09 11:16:50 AM UTC 24 |
189296383 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2495875803 |
|
|
Sep 09 11:15:47 AM UTC 24 |
Sep 09 11:15:50 AM UTC 24 |
117001804 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2990717206 |
|
|
Sep 09 11:15:09 AM UTC 24 |
Sep 09 11:15:50 AM UTC 24 |
11753793941 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.2427020863 |
|
|
Sep 09 11:13:31 AM UTC 24 |
Sep 09 11:15:50 AM UTC 24 |
11055822160 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.2698724082 |
|
|
Sep 09 11:15:47 AM UTC 24 |
Sep 09 11:15:51 AM UTC 24 |
31454073 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.2546979773 |
|
|
Sep 09 11:15:45 AM UTC 24 |
Sep 09 11:15:53 AM UTC 24 |
8094829231 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2291984192 |
|
|
Sep 09 11:15:13 AM UTC 24 |
Sep 09 11:15:54 AM UTC 24 |
3189382309 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.953325146 |
|
|
Sep 09 11:15:51 AM UTC 24 |
Sep 09 11:15:55 AM UTC 24 |
210061696 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1413842716 |
|
|
Sep 09 11:13:07 AM UTC 24 |
Sep 09 11:15:56 AM UTC 24 |
113521066211 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.1022461670 |
|
|
Sep 09 11:15:46 AM UTC 24 |
Sep 09 11:15:56 AM UTC 24 |
1204661047 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.3237289124 |
|
|
Sep 09 11:15:35 AM UTC 24 |
Sep 09 11:15:56 AM UTC 24 |
10996415874 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.2423567543 |
|
|
Sep 09 11:15:14 AM UTC 24 |
Sep 09 11:15:56 AM UTC 24 |
2690730637 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.202918797 |
|
|
Sep 09 11:15:51 AM UTC 24 |
Sep 09 11:15:58 AM UTC 24 |
309635639 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.114411613 |
|
|
Sep 09 11:10:23 AM UTC 24 |
Sep 09 11:15:58 AM UTC 24 |
28884456305 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1356239799 |
|
|
Sep 09 11:15:48 AM UTC 24 |
Sep 09 11:15:59 AM UTC 24 |
1553975304 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.29452394 |
|
|
Sep 09 11:15:52 AM UTC 24 |
Sep 09 11:16:00 AM UTC 24 |
659266508 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.335449678 |
|
|
Sep 09 11:15:57 AM UTC 24 |
Sep 09 11:16:00 AM UTC 24 |
41206302 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3429668972 |
|
|
Sep 09 11:15:58 AM UTC 24 |
Sep 09 11:16:00 AM UTC 24 |
46061318 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3080111016 |
|
|
Sep 09 11:15:59 AM UTC 24 |
Sep 09 11:16:02 AM UTC 24 |
16280398 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3135286160 |
|
|
Sep 09 11:16:01 AM UTC 24 |
Sep 09 11:16:03 AM UTC 24 |
72312505 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.3215462368 |
|
|
Sep 09 11:16:02 AM UTC 24 |
Sep 09 11:16:05 AM UTC 24 |
68801297 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3644966466 |
|
|
Sep 09 11:15:56 AM UTC 24 |
Sep 09 11:16:05 AM UTC 24 |
3360638877 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.426775400 |
|
|
Sep 09 11:15:47 AM UTC 24 |
Sep 09 11:16:07 AM UTC 24 |
19833529755 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.1380882980 |
|
|
Sep 09 11:14:37 AM UTC 24 |
Sep 09 11:16:08 AM UTC 24 |
11430091974 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3614445587 |
|
|
Sep 09 11:16:03 AM UTC 24 |
Sep 09 11:16:08 AM UTC 24 |
417220996 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2491301092 |
|
|
Sep 09 11:09:51 AM UTC 24 |
Sep 09 11:16:08 AM UTC 24 |
45527144857 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3066645483 |
|
|
Sep 09 11:16:01 AM UTC 24 |
Sep 09 11:16:11 AM UTC 24 |
690546277 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.4229858046 |
|
|
Sep 09 11:16:08 AM UTC 24 |
Sep 09 11:16:13 AM UTC 24 |
63165032 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.4288187059 |
|
|
Sep 09 11:16:05 AM UTC 24 |
Sep 09 11:16:14 AM UTC 24 |
445628211 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.4061485323 |
|
|
Sep 09 11:11:47 AM UTC 24 |
Sep 09 11:16:15 AM UTC 24 |
29401355786 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1554495059 |
|
|
Sep 09 11:16:04 AM UTC 24 |
Sep 09 11:16:16 AM UTC 24 |
5122117183 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1501546502 |
|
|
Sep 09 11:15:52 AM UTC 24 |
Sep 09 11:16:17 AM UTC 24 |
12192919599 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2831210870 |
|
|
Sep 09 11:16:12 AM UTC 24 |
Sep 09 11:16:18 AM UTC 24 |
851662477 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.282179756 |
|
|
Sep 09 11:16:06 AM UTC 24 |
Sep 09 11:16:19 AM UTC 24 |
1347475162 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.356419734 |
|
|
Sep 09 11:16:18 AM UTC 24 |
Sep 09 11:16:20 AM UTC 24 |
13089063 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.365076455 |
|
|
Sep 09 11:15:38 AM UTC 24 |
Sep 09 11:16:20 AM UTC 24 |
9481798807 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.4135604509 |
|
|
Sep 09 11:16:19 AM UTC 24 |
Sep 09 11:16:21 AM UTC 24 |
41544564 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.745330127 |
|
|
Sep 09 11:16:21 AM UTC 24 |
Sep 09 11:16:23 AM UTC 24 |
15372750 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.2318653587 |
|
|
Sep 09 11:14:05 AM UTC 24 |
Sep 09 11:16:24 AM UTC 24 |
63706846903 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.2366877031 |
|
|
Sep 09 11:12:47 AM UTC 24 |
Sep 09 11:16:24 AM UTC 24 |
106435751699 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.277571366 |
|
|
Sep 09 11:13:29 AM UTC 24 |
Sep 09 11:16:24 AM UTC 24 |
34637949048 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.734056375 |
|
|
Sep 09 11:16:22 AM UTC 24 |
Sep 09 11:16:25 AM UTC 24 |
104387455 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2868994997 |
|
|
Sep 09 11:16:07 AM UTC 24 |
Sep 09 11:16:27 AM UTC 24 |
2748794346 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2039653573 |
|
|
Sep 09 11:16:25 AM UTC 24 |
Sep 09 11:16:28 AM UTC 24 |
109663134 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.1538500875 |
|
|
Sep 09 11:15:54 AM UTC 24 |
Sep 09 11:16:29 AM UTC 24 |
1540114040 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1586191938 |
|
|
Sep 09 11:09:23 AM UTC 24 |
Sep 09 11:16:30 AM UTC 24 |
35719615807 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.3665047824 |
|
|
Sep 09 11:12:33 AM UTC 24 |
Sep 09 11:16:32 AM UTC 24 |
50753678035 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.938833522 |
|
|
Sep 09 11:16:28 AM UTC 24 |
Sep 09 11:16:33 AM UTC 24 |
297803543 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.1268373314 |
|
|
Sep 09 11:16:25 AM UTC 24 |
Sep 09 11:16:33 AM UTC 24 |
330389593 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.3336884553 |
|
|
Sep 09 11:16:33 AM UTC 24 |
Sep 09 11:16:35 AM UTC 24 |
18016052 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.2870424606 |
|
|
Sep 09 11:16:29 AM UTC 24 |
Sep 09 11:16:35 AM UTC 24 |
146887887 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3283561146 |
|
|
Sep 09 11:16:09 AM UTC 24 |
Sep 09 11:16:36 AM UTC 24 |
1903982740 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3205336385 |
|
|
Sep 09 11:16:30 AM UTC 24 |
Sep 09 11:16:37 AM UTC 24 |
537024676 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.1577308518 |
|
|
Sep 09 11:16:36 AM UTC 24 |
Sep 09 11:16:39 AM UTC 24 |
23425451 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.3804351996 |
|
|
Sep 09 11:16:38 AM UTC 24 |
Sep 09 11:16:40 AM UTC 24 |
15714382 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.4268701399 |
|
|
Sep 09 11:16:20 AM UTC 24 |
Sep 09 11:16:40 AM UTC 24 |
3787650202 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.23905913 |
|
|
Sep 09 11:16:24 AM UTC 24 |
Sep 09 11:16:40 AM UTC 24 |
1017692518 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2423132923 |
|
|
Sep 09 11:14:24 AM UTC 24 |
Sep 09 11:16:41 AM UTC 24 |
70903226195 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.1642252572 |
|
|
Sep 09 11:16:09 AM UTC 24 |
Sep 09 11:16:41 AM UTC 24 |
1436817453 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.4121335791 |
|
|
Sep 09 11:16:41 AM UTC 24 |
Sep 09 11:16:43 AM UTC 24 |
1430931589 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3894076531 |
|
|
Sep 09 11:16:39 AM UTC 24 |
Sep 09 11:16:44 AM UTC 24 |
2376762914 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.160607509 |
|
|
Sep 09 11:16:40 AM UTC 24 |
Sep 09 11:16:44 AM UTC 24 |
358132265 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1895575224 |
|
|
Sep 09 11:16:26 AM UTC 24 |
Sep 09 11:16:45 AM UTC 24 |
26980077507 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.529357478 |
|
|
Sep 09 11:15:21 AM UTC 24 |
Sep 09 11:16:46 AM UTC 24 |
6722455509 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.3274559606 |
|
|
Sep 09 11:14:39 AM UTC 24 |
Sep 09 11:16:46 AM UTC 24 |
31022766087 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.352768128 |
|
|
Sep 09 11:16:42 AM UTC 24 |
Sep 09 11:16:46 AM UTC 24 |
53619058 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.1408072558 |
|
|
Sep 09 11:16:41 AM UTC 24 |
Sep 09 11:16:46 AM UTC 24 |
1053750305 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1704233300 |
|
|
Sep 09 11:10:52 AM UTC 24 |
Sep 09 11:16:47 AM UTC 24 |
83954053284 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3010203238 |
|
|
Sep 09 11:09:32 AM UTC 24 |
Sep 09 11:16:47 AM UTC 24 |
46935093456 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1879270048 |
|
|
Sep 09 11:16:42 AM UTC 24 |
Sep 09 11:16:48 AM UTC 24 |
1051928608 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.244704325 |
|
|
Sep 09 11:15:43 AM UTC 24 |
Sep 09 11:16:48 AM UTC 24 |
18294164647 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.1789132105 |
|
|
Sep 09 11:16:44 AM UTC 24 |
Sep 09 11:16:48 AM UTC 24 |
119894726 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1009822805 |
|
|
Sep 09 11:14:56 AM UTC 24 |
Sep 09 11:16:49 AM UTC 24 |
74793804606 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.3129281231 |
|
|
Sep 09 11:16:49 AM UTC 24 |
Sep 09 11:16:51 AM UTC 24 |
41285081 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.802998247 |
|
|
Sep 09 11:16:49 AM UTC 24 |
Sep 09 11:16:51 AM UTC 24 |
15951119 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.22162104 |
|
|
Sep 09 11:16:50 AM UTC 24 |
Sep 09 11:16:52 AM UTC 24 |
114156942 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3030734529 |
|
|
Sep 09 11:16:44 AM UTC 24 |
Sep 09 11:16:52 AM UTC 24 |
292158573 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.1586445572 |
|
|
Sep 09 11:16:46 AM UTC 24 |
Sep 09 11:16:53 AM UTC 24 |
181217488 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.326121772 |
|
|
Sep 09 11:16:41 AM UTC 24 |
Sep 09 11:16:54 AM UTC 24 |
3591621833 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.3464229071 |
|
|
Sep 09 11:16:52 AM UTC 24 |
Sep 09 11:16:55 AM UTC 24 |
37656729 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.2152163699 |
|
|
Sep 09 11:14:53 AM UTC 24 |
Sep 09 11:16:57 AM UTC 24 |
82917304674 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.857763416 |
|
|
Sep 09 11:12:47 AM UTC 24 |
Sep 09 11:16:57 AM UTC 24 |
102061836874 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.329035264 |
|
|
Sep 09 11:16:49 AM UTC 24 |
Sep 09 11:16:58 AM UTC 24 |
791174137 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.4185684835 |
|
|
Sep 09 11:16:47 AM UTC 24 |
Sep 09 11:16:58 AM UTC 24 |
24043795649 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.3609205676 |
|
|
Sep 09 11:16:55 AM UTC 24 |
Sep 09 11:16:59 AM UTC 24 |
112599081 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.3217598510 |
|
|
Sep 09 11:16:21 AM UTC 24 |
Sep 09 11:16:59 AM UTC 24 |
18784048271 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.172153126 |
|
|
Sep 09 11:16:54 AM UTC 24 |
Sep 09 11:16:59 AM UTC 24 |
178975571 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.3234120371 |
|
|
Sep 09 11:16:56 AM UTC 24 |
Sep 09 11:17:00 AM UTC 24 |
152937169 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1771757658 |
|
|
Sep 09 11:16:55 AM UTC 24 |
Sep 09 11:17:00 AM UTC 24 |
295099835 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.363955143 |
|
|
Sep 09 11:17:00 AM UTC 24 |
Sep 09 11:17:02 AM UTC 24 |
14309598 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.3740030616 |
|
|
Sep 09 11:17:01 AM UTC 24 |
Sep 09 11:17:03 AM UTC 24 |
54165651 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3366136958 |
|
|
Sep 09 11:15:12 AM UTC 24 |
Sep 09 11:17:06 AM UTC 24 |
26837203570 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.4017934661 |
|
|
Sep 09 11:16:52 AM UTC 24 |
Sep 09 11:17:06 AM UTC 24 |
4196207813 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2338202264 |
|
|
Sep 09 11:13:47 AM UTC 24 |
Sep 09 11:17:07 AM UTC 24 |
27928247052 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2348878564 |
|
|
Sep 09 11:16:54 AM UTC 24 |
Sep 09 11:17:07 AM UTC 24 |
3724220305 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.3730103348 |
|
|
Sep 09 11:16:01 AM UTC 24 |
Sep 09 11:17:09 AM UTC 24 |
9463530920 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3862802408 |
|
|
Sep 09 11:17:07 AM UTC 24 |
Sep 09 11:17:09 AM UTC 24 |
44463163 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.2426629484 |
|
|
Sep 09 11:17:04 AM UTC 24 |
Sep 09 11:17:11 AM UTC 24 |
1440355550 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.187407820 |
|
|
Sep 09 11:16:59 AM UTC 24 |
Sep 09 11:17:11 AM UTC 24 |
3042295349 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.2774441909 |
|
|
Sep 09 11:17:07 AM UTC 24 |
Sep 09 11:17:13 AM UTC 24 |
202962358 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.4162589831 |
|
|
Sep 09 11:16:26 AM UTC 24 |
Sep 09 11:17:15 AM UTC 24 |
4563725998 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.868003348 |
|
|
Sep 09 11:16:17 AM UTC 24 |
Sep 09 11:17:15 AM UTC 24 |
3188717962 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1946807120 |
|
|
Sep 09 11:17:09 AM UTC 24 |
Sep 09 11:17:15 AM UTC 24 |
613224416 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3576089484 |
|
|
Sep 09 11:17:08 AM UTC 24 |
Sep 09 11:17:16 AM UTC 24 |
1567530144 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.4114124008 |
|
|
Sep 09 11:17:12 AM UTC 24 |
Sep 09 11:17:17 AM UTC 24 |
44968223 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1559579914 |
|
|
Sep 09 11:17:15 AM UTC 24 |
Sep 09 11:17:18 AM UTC 24 |
113811905 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1891628784 |
|
|
Sep 09 11:16:50 AM UTC 24 |
Sep 09 11:17:19 AM UTC 24 |
1793010197 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.235356691 |
|
|
Sep 09 11:11:33 AM UTC 24 |
Sep 09 11:17:19 AM UTC 24 |
26596889569 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1422173024 |
|
|
Sep 09 11:11:41 AM UTC 24 |
Sep 09 11:17:21 AM UTC 24 |
92016802764 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.671701271 |
|
|
Sep 09 11:17:20 AM UTC 24 |
Sep 09 11:17:22 AM UTC 24 |
14281655 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.1483775703 |
|
|
Sep 09 11:17:20 AM UTC 24 |
Sep 09 11:17:22 AM UTC 24 |
19210537 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.416441424 |
|
|
Sep 09 11:17:17 AM UTC 24 |
Sep 09 11:17:25 AM UTC 24 |
3556746217 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.3060165954 |
|
|
Sep 09 11:17:23 AM UTC 24 |
Sep 09 11:17:25 AM UTC 24 |
87432569 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.4237553779 |
|
|
Sep 09 11:15:34 AM UTC 24 |
Sep 09 11:17:26 AM UTC 24 |
54902508922 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3247313513 |
|
|
Sep 09 11:15:55 AM UTC 24 |
Sep 09 11:17:27 AM UTC 24 |
36441555334 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.3804323264 |
|
|
Sep 09 11:17:25 AM UTC 24 |
Sep 09 11:17:28 AM UTC 24 |
28035558 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1219460163 |
|
|
Sep 09 11:15:27 AM UTC 24 |
Sep 09 11:17:28 AM UTC 24 |
14906951735 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4093771135 |
|
|
Sep 09 11:17:08 AM UTC 24 |
Sep 09 11:17:29 AM UTC 24 |
31579158256 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2156418138 |
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Sep 09 11:16:14 AM UTC 24 |
Sep 09 11:17:32 AM UTC 24 |
5460435014 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.1147358724 |
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Sep 09 11:17:29 AM UTC 24 |
Sep 09 11:17:33 AM UTC 24 |
132208827 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.601454454 |
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Sep 09 11:17:30 AM UTC 24 |
Sep 09 11:17:36 AM UTC 24 |
231140318 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.965098056 |
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Sep 09 11:14:24 AM UTC 24 |
Sep 09 11:17:38 AM UTC 24 |
68743921887 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.2893899596 |
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Sep 09 11:16:58 AM UTC 24 |
Sep 09 11:17:39 AM UTC 24 |
16533514624 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1122702500 |
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Sep 09 11:17:04 AM UTC 24 |
Sep 09 11:17:39 AM UTC 24 |
4890475395 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.697077631 |
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Sep 09 11:16:33 AM UTC 24 |
Sep 09 11:17:39 AM UTC 24 |
15487452534 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.3406657459 |
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Sep 09 11:17:11 AM UTC 24 |
Sep 09 11:17:41 AM UTC 24 |
88409727201 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.1112448887 |
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Sep 09 11:15:57 AM UTC 24 |
Sep 09 11:17:41 AM UTC 24 |
18547636771 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.358591540 |
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Sep 09 11:14:57 AM UTC 24 |
Sep 09 11:17:41 AM UTC 24 |
29313704767 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.3804337348 |
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Sep 09 11:17:29 AM UTC 24 |
Sep 09 11:17:41 AM UTC 24 |
977674553 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1287678776 |
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Sep 09 11:17:36 AM UTC 24 |
Sep 09 11:17:42 AM UTC 24 |
297829540 ps |