| T369 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.4081879841 |
|
|
Oct 03 04:24:55 AM UTC 24 |
Oct 03 04:25:34 AM UTC 24 |
3124339631 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3338877552 |
|
|
Oct 03 04:25:30 AM UTC 24 |
Oct 03 04:25:34 AM UTC 24 |
868899171 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.8582266 |
|
|
Oct 03 04:25:31 AM UTC 24 |
Oct 03 04:25:35 AM UTC 24 |
75430299 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.3023081098 |
|
|
Oct 03 04:25:28 AM UTC 24 |
Oct 03 04:25:38 AM UTC 24 |
3216997957 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.1739806697 |
|
|
Oct 03 04:25:34 AM UTC 24 |
Oct 03 04:25:39 AM UTC 24 |
86426069 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2579512938 |
|
|
Oct 03 04:25:31 AM UTC 24 |
Oct 03 04:25:39 AM UTC 24 |
1209071368 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.2256907463 |
|
|
Oct 03 04:25:34 AM UTC 24 |
Oct 03 04:25:39 AM UTC 24 |
83518389 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.134657638 |
|
|
Oct 03 04:25:35 AM UTC 24 |
Oct 03 04:25:41 AM UTC 24 |
469601027 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.1934668060 |
|
|
Oct 03 04:25:34 AM UTC 24 |
Oct 03 04:25:42 AM UTC 24 |
1195376266 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.2975539764 |
|
|
Oct 03 04:25:40 AM UTC 24 |
Oct 03 04:25:43 AM UTC 24 |
40220352 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.3533899885 |
|
|
Oct 03 04:25:42 AM UTC 24 |
Oct 03 04:25:44 AM UTC 24 |
42537394 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.549894840 |
|
|
Oct 03 04:25:32 AM UTC 24 |
Oct 03 04:25:44 AM UTC 24 |
235088923 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.279935539 |
|
|
Oct 03 04:24:32 AM UTC 24 |
Oct 03 04:25:45 AM UTC 24 |
16038198642 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.492267363 |
|
|
Oct 03 04:25:44 AM UTC 24 |
Oct 03 04:25:47 AM UTC 24 |
92460100 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.1720848049 |
|
|
Oct 03 04:25:44 AM UTC 24 |
Oct 03 04:25:47 AM UTC 24 |
123551259 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3899899730 |
|
|
Oct 03 04:25:45 AM UTC 24 |
Oct 03 04:25:48 AM UTC 24 |
29938934 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.2281426328 |
|
|
Oct 03 04:25:13 AM UTC 24 |
Oct 03 04:25:50 AM UTC 24 |
23083621711 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.137104133 |
|
|
Oct 03 04:25:47 AM UTC 24 |
Oct 03 04:25:51 AM UTC 24 |
67963279 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2228456898 |
|
|
Oct 03 04:23:26 AM UTC 24 |
Oct 03 04:25:52 AM UTC 24 |
81100926861 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.1687201892 |
|
|
Oct 03 04:25:47 AM UTC 24 |
Oct 03 04:25:53 AM UTC 24 |
76652468 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.865399117 |
|
|
Oct 03 04:25:44 AM UTC 24 |
Oct 03 04:25:57 AM UTC 24 |
763672455 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.3474141243 |
|
|
Oct 03 04:25:51 AM UTC 24 |
Oct 03 04:25:57 AM UTC 24 |
494377789 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.1081171198 |
|
|
Oct 03 04:25:44 AM UTC 24 |
Oct 03 04:25:58 AM UTC 24 |
2516583768 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2766512105 |
|
|
Oct 03 04:21:50 AM UTC 24 |
Oct 03 04:25:58 AM UTC 24 |
22469629436 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.893650238 |
|
|
Oct 03 04:25:45 AM UTC 24 |
Oct 03 04:25:59 AM UTC 24 |
1029892537 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.3544312639 |
|
|
Oct 03 04:24:58 AM UTC 24 |
Oct 03 04:26:01 AM UTC 24 |
5381333220 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1220482738 |
|
|
Oct 03 04:22:24 AM UTC 24 |
Oct 03 04:26:01 AM UTC 24 |
20391037018 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.2462466190 |
|
|
Oct 03 04:25:59 AM UTC 24 |
Oct 03 04:26:01 AM UTC 24 |
477242992 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3522661442 |
|
|
Oct 03 04:26:00 AM UTC 24 |
Oct 03 04:26:02 AM UTC 24 |
12882989 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.1314947893 |
|
|
Oct 03 04:26:02 AM UTC 24 |
Oct 03 04:26:04 AM UTC 24 |
21135958 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.3767331012 |
|
|
Oct 03 04:26:02 AM UTC 24 |
Oct 03 04:26:04 AM UTC 24 |
344606047 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.166277263 |
|
|
Oct 03 04:26:05 AM UTC 24 |
Oct 03 04:26:07 AM UTC 24 |
54895748 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.3300154806 |
|
|
Oct 03 04:26:05 AM UTC 24 |
Oct 03 04:26:08 AM UTC 24 |
358427109 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1451736205 |
|
|
Oct 03 04:25:57 AM UTC 24 |
Oct 03 04:26:08 AM UTC 24 |
1061693735 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3791140865 |
|
|
Oct 03 04:26:02 AM UTC 24 |
Oct 03 04:26:13 AM UTC 24 |
4654349579 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.993004255 |
|
|
Oct 03 04:26:09 AM UTC 24 |
Oct 03 04:26:13 AM UTC 24 |
100715302 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.87286074 |
|
|
Oct 03 04:26:08 AM UTC 24 |
Oct 03 04:26:14 AM UTC 24 |
97066018 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2040465949 |
|
|
Oct 03 04:25:53 AM UTC 24 |
Oct 03 04:26:14 AM UTC 24 |
8817283543 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.2418164795 |
|
|
Oct 03 04:26:09 AM UTC 24 |
Oct 03 04:26:14 AM UTC 24 |
279602042 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.2407872759 |
|
|
Oct 03 04:25:54 AM UTC 24 |
Oct 03 04:26:22 AM UTC 24 |
1117295738 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3021482847 |
|
|
Oct 03 04:25:16 AM UTC 24 |
Oct 03 04:26:23 AM UTC 24 |
4674058241 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2680831544 |
|
|
Oct 03 04:25:18 AM UTC 24 |
Oct 03 04:26:25 AM UTC 24 |
17629851689 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2844031470 |
|
|
Oct 03 04:22:45 AM UTC 24 |
Oct 03 04:26:25 AM UTC 24 |
41092191237 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.3348749062 |
|
|
Oct 03 04:26:15 AM UTC 24 |
Oct 03 04:26:25 AM UTC 24 |
187511907 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.298750153 |
|
|
Oct 03 04:22:07 AM UTC 24 |
Oct 03 04:26:26 AM UTC 24 |
15566520343 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2970115476 |
|
|
Oct 03 04:25:35 AM UTC 24 |
Oct 03 04:26:27 AM UTC 24 |
9648239885 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.707061940 |
|
|
Oct 03 04:26:14 AM UTC 24 |
Oct 03 04:26:28 AM UTC 24 |
5209163988 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.1556682517 |
|
|
Oct 03 04:24:28 AM UTC 24 |
Oct 03 04:26:29 AM UTC 24 |
7240323140 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.209597376 |
|
|
Oct 03 04:26:27 AM UTC 24 |
Oct 03 04:26:29 AM UTC 24 |
55714072 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.2388443472 |
|
|
Oct 03 04:26:27 AM UTC 24 |
Oct 03 04:26:29 AM UTC 24 |
36571854 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.2592727035 |
|
|
Oct 03 04:26:13 AM UTC 24 |
Oct 03 04:26:29 AM UTC 24 |
794510189 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.344671095 |
|
|
Oct 03 04:26:28 AM UTC 24 |
Oct 03 04:26:31 AM UTC 24 |
33114369 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.4002492912 |
|
|
Oct 03 04:26:15 AM UTC 24 |
Oct 03 04:26:31 AM UTC 24 |
802943213 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.793437016 |
|
|
Oct 03 04:26:30 AM UTC 24 |
Oct 03 04:26:32 AM UTC 24 |
62426476 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.3175087598 |
|
|
Oct 03 04:26:30 AM UTC 24 |
Oct 03 04:26:33 AM UTC 24 |
29178178 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.196133430 |
|
|
Oct 03 04:24:06 AM UTC 24 |
Oct 03 04:26:34 AM UTC 24 |
26785238763 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1829977613 |
|
|
Oct 03 04:26:30 AM UTC 24 |
Oct 03 04:26:36 AM UTC 24 |
322815702 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.223136513 |
|
|
Oct 03 04:24:56 AM UTC 24 |
Oct 03 04:26:37 AM UTC 24 |
44671761275 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3964281777 |
|
|
Oct 03 04:26:29 AM UTC 24 |
Oct 03 04:26:39 AM UTC 24 |
3398904432 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.1636089572 |
|
|
Oct 03 04:26:34 AM UTC 24 |
Oct 03 04:26:39 AM UTC 24 |
173042264 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.174888277 |
|
|
Oct 03 04:26:03 AM UTC 24 |
Oct 03 04:26:40 AM UTC 24 |
7750067641 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2926124046 |
|
|
Oct 03 04:23:08 AM UTC 24 |
Oct 03 04:26:40 AM UTC 24 |
47577647401 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.1317001145 |
|
|
Oct 03 04:26:32 AM UTC 24 |
Oct 03 04:26:41 AM UTC 24 |
641194225 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1983432756 |
|
|
Oct 03 04:26:35 AM UTC 24 |
Oct 03 04:26:46 AM UTC 24 |
1478418507 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.3484519142 |
|
|
Oct 03 04:26:40 AM UTC 24 |
Oct 03 04:26:47 AM UTC 24 |
195559665 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.2707321524 |
|
|
Oct 03 04:26:46 AM UTC 24 |
Oct 03 04:26:48 AM UTC 24 |
25100141 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.4053714570 |
|
|
Oct 03 04:26:47 AM UTC 24 |
Oct 03 04:26:50 AM UTC 24 |
13884713 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.697576388 |
|
|
Oct 03 04:26:14 AM UTC 24 |
Oct 03 04:26:51 AM UTC 24 |
8247399124 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.2175099112 |
|
|
Oct 03 04:26:49 AM UTC 24 |
Oct 03 04:26:52 AM UTC 24 |
27833935 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.454594892 |
|
|
Oct 03 04:26:53 AM UTC 24 |
Oct 03 04:26:55 AM UTC 24 |
36043241 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.11445703 |
|
|
Oct 03 04:26:51 AM UTC 24 |
Oct 03 04:26:55 AM UTC 24 |
292282834 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.222255332 |
|
|
Oct 03 04:26:56 AM UTC 24 |
Oct 03 04:26:58 AM UTC 24 |
76094846 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1759718614 |
|
|
Oct 03 04:26:56 AM UTC 24 |
Oct 03 04:27:00 AM UTC 24 |
120860900 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2526519276 |
|
|
Oct 03 04:22:43 AM UTC 24 |
Oct 03 04:27:04 AM UTC 24 |
27866259830 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.2837525445 |
|
|
Oct 03 04:26:37 AM UTC 24 |
Oct 03 04:27:05 AM UTC 24 |
6658513932 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1719789832 |
|
|
Oct 03 04:26:59 AM UTC 24 |
Oct 03 04:27:06 AM UTC 24 |
1821781331 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2636115430 |
|
|
Oct 03 04:26:31 AM UTC 24 |
Oct 03 04:27:06 AM UTC 24 |
34899971737 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.288570667 |
|
|
Oct 03 04:27:07 AM UTC 24 |
Oct 03 04:27:11 AM UTC 24 |
126970413 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.3810264997 |
|
|
Oct 03 04:27:01 AM UTC 24 |
Oct 03 04:27:13 AM UTC 24 |
1521202026 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.3102434159 |
|
|
Oct 03 04:25:39 AM UTC 24 |
Oct 03 04:27:13 AM UTC 24 |
66592663293 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.4057212680 |
|
|
Oct 03 04:27:06 AM UTC 24 |
Oct 03 04:27:18 AM UTC 24 |
2999801386 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.3043667189 |
|
|
Oct 03 04:26:29 AM UTC 24 |
Oct 03 04:27:19 AM UTC 24 |
2251801734 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.1431069291 |
|
|
Oct 03 04:26:33 AM UTC 24 |
Oct 03 04:27:20 AM UTC 24 |
4499605138 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.2278015870 |
|
|
Oct 03 04:25:59 AM UTC 24 |
Oct 03 04:27:20 AM UTC 24 |
23077796270 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1202746239 |
|
|
Oct 03 04:27:14 AM UTC 24 |
Oct 03 04:27:21 AM UTC 24 |
6170551213 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.169092250 |
|
|
Oct 03 04:27:20 AM UTC 24 |
Oct 03 04:27:22 AM UTC 24 |
46592825 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.1122113243 |
|
|
Oct 03 04:26:40 AM UTC 24 |
Oct 03 04:27:23 AM UTC 24 |
6941379028 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.853582199 |
|
|
Oct 03 04:27:21 AM UTC 24 |
Oct 03 04:27:24 AM UTC 24 |
24461843 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.3586972064 |
|
|
Oct 03 04:27:22 AM UTC 24 |
Oct 03 04:27:25 AM UTC 24 |
15321354 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.838613207 |
|
|
Oct 03 04:21:42 AM UTC 24 |
Oct 03 04:27:25 AM UTC 24 |
293392256784 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.4063376118 |
|
|
Oct 03 04:27:25 AM UTC 24 |
Oct 03 04:27:27 AM UTC 24 |
139441309 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3021536177 |
|
|
Oct 03 04:26:15 AM UTC 24 |
Oct 03 04:27:27 AM UTC 24 |
39744024269 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.3114722575 |
|
|
Oct 03 04:27:24 AM UTC 24 |
Oct 03 04:27:28 AM UTC 24 |
805380645 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.575521179 |
|
|
Oct 03 04:26:52 AM UTC 24 |
Oct 03 04:27:28 AM UTC 24 |
11486310247 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.1603408164 |
|
|
Oct 03 04:27:26 AM UTC 24 |
Oct 03 04:27:28 AM UTC 24 |
74800240 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1836162355 |
|
|
Oct 03 04:27:26 AM UTC 24 |
Oct 03 04:27:31 AM UTC 24 |
222085789 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.3294271316 |
|
|
Oct 03 04:27:29 AM UTC 24 |
Oct 03 04:27:35 AM UTC 24 |
327589156 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1806285887 |
|
|
Oct 03 04:27:29 AM UTC 24 |
Oct 03 04:27:36 AM UTC 24 |
126475812 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.2037446435 |
|
|
Oct 03 04:25:57 AM UTC 24 |
Oct 03 04:27:36 AM UTC 24 |
28429297336 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.136956439 |
|
|
Oct 03 04:27:24 AM UTC 24 |
Oct 03 04:27:37 AM UTC 24 |
8590222534 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.739257848 |
|
|
Oct 03 04:27:28 AM UTC 24 |
Oct 03 04:27:38 AM UTC 24 |
313437051 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.2641146443 |
|
|
Oct 03 04:27:29 AM UTC 24 |
Oct 03 04:27:39 AM UTC 24 |
1025308609 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.890335699 |
|
|
Oct 03 04:25:39 AM UTC 24 |
Oct 03 04:27:39 AM UTC 24 |
26515466011 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.3164984902 |
|
|
Oct 03 04:25:49 AM UTC 24 |
Oct 03 04:27:40 AM UTC 24 |
8155798286 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3854588197 |
|
|
Oct 03 04:27:40 AM UTC 24 |
Oct 03 04:27:42 AM UTC 24 |
25935204 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.2271904118 |
|
|
Oct 03 04:27:41 AM UTC 24 |
Oct 03 04:27:43 AM UTC 24 |
49694080 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2699213545 |
|
|
Oct 03 04:26:41 AM UTC 24 |
Oct 03 04:27:44 AM UTC 24 |
10205328777 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.1413289656 |
|
|
Oct 03 04:27:44 AM UTC 24 |
Oct 03 04:27:46 AM UTC 24 |
22738909 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.19642659 |
|
|
Oct 03 04:27:45 AM UTC 24 |
Oct 03 04:27:47 AM UTC 24 |
16804148 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.564045085 |
|
|
Oct 03 04:27:37 AM UTC 24 |
Oct 03 04:27:48 AM UTC 24 |
4244264153 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.845581998 |
|
|
Oct 03 04:23:26 AM UTC 24 |
Oct 03 04:27:48 AM UTC 24 |
24073049233 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1304034287 |
|
|
Oct 03 04:27:43 AM UTC 24 |
Oct 03 04:27:49 AM UTC 24 |
1186344808 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.968445174 |
|
|
Oct 03 04:27:47 AM UTC 24 |
Oct 03 04:27:50 AM UTC 24 |
56568604 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.4154652546 |
|
|
Oct 03 04:27:04 AM UTC 24 |
Oct 03 04:27:51 AM UTC 24 |
3213715466 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.359829432 |
|
|
Oct 03 04:27:37 AM UTC 24 |
Oct 03 04:27:52 AM UTC 24 |
4788207844 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.587395009 |
|
|
Oct 03 04:27:39 AM UTC 24 |
Oct 03 04:27:54 AM UTC 24 |
725325306 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.842602413 |
|
|
Oct 03 04:26:42 AM UTC 24 |
Oct 03 04:27:55 AM UTC 24 |
9589953827 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.692569910 |
|
|
Oct 03 04:27:28 AM UTC 24 |
Oct 03 04:27:55 AM UTC 24 |
14331684525 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1790071231 |
|
|
Oct 03 04:27:52 AM UTC 24 |
Oct 03 04:27:56 AM UTC 24 |
147270060 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.224345411 |
|
|
Oct 03 04:27:31 AM UTC 24 |
Oct 03 04:27:57 AM UTC 24 |
3277015642 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.3479809444 |
|
|
Oct 03 04:27:51 AM UTC 24 |
Oct 03 04:28:00 AM UTC 24 |
2423494833 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.3928778302 |
|
|
Oct 03 04:27:50 AM UTC 24 |
Oct 03 04:28:00 AM UTC 24 |
5926833015 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.4042150287 |
|
|
Oct 03 04:23:26 AM UTC 24 |
Oct 03 04:28:01 AM UTC 24 |
100383279913 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3712635833 |
|
|
Oct 03 04:27:49 AM UTC 24 |
Oct 03 04:28:02 AM UTC 24 |
1572054040 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.1381250875 |
|
|
Oct 03 04:28:02 AM UTC 24 |
Oct 03 04:28:04 AM UTC 24 |
37654050 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.1871515053 |
|
|
Oct 03 04:28:03 AM UTC 24 |
Oct 03 04:28:05 AM UTC 24 |
36519016 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.2050587216 |
|
|
Oct 03 04:27:48 AM UTC 24 |
Oct 03 04:28:07 AM UTC 24 |
1849097142 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1499145653 |
|
|
Oct 03 04:25:19 AM UTC 24 |
Oct 03 04:28:09 AM UTC 24 |
69274555285 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3818194876 |
|
|
Oct 03 04:28:06 AM UTC 24 |
Oct 03 04:28:09 AM UTC 24 |
135820008 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.4022823839 |
|
|
Oct 03 04:27:50 AM UTC 24 |
Oct 03 04:28:09 AM UTC 24 |
2291781461 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2798710736 |
|
|
Oct 03 04:28:03 AM UTC 24 |
Oct 03 04:28:09 AM UTC 24 |
2279865174 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.2089767045 |
|
|
Oct 03 04:25:54 AM UTC 24 |
Oct 03 04:28:10 AM UTC 24 |
74058205005 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2455557804 |
|
|
Oct 03 04:26:41 AM UTC 24 |
Oct 03 04:28:14 AM UTC 24 |
6429916945 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.35018357 |
|
|
Oct 03 04:28:08 AM UTC 24 |
Oct 03 04:28:15 AM UTC 24 |
1650783080 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1769289996 |
|
|
Oct 03 04:27:55 AM UTC 24 |
Oct 03 04:28:15 AM UTC 24 |
3686184435 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.1473770329 |
|
|
Oct 03 04:28:09 AM UTC 24 |
Oct 03 04:28:16 AM UTC 24 |
1472252041 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3955295270 |
|
|
Oct 03 04:27:55 AM UTC 24 |
Oct 03 04:28:16 AM UTC 24 |
3267761611 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.257445472 |
|
|
Oct 03 04:28:12 AM UTC 24 |
Oct 03 04:28:17 AM UTC 24 |
108680168 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.2363099237 |
|
|
Oct 03 04:28:09 AM UTC 24 |
Oct 03 04:28:20 AM UTC 24 |
1226744110 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1766149961 |
|
|
Oct 03 04:26:24 AM UTC 24 |
Oct 03 04:28:21 AM UTC 24 |
9017332110 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.452755227 |
|
|
Oct 03 04:28:15 AM UTC 24 |
Oct 03 04:28:22 AM UTC 24 |
324801087 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.3212710724 |
|
|
Oct 03 04:28:08 AM UTC 24 |
Oct 03 04:28:22 AM UTC 24 |
1337400025 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.3997330220 |
|
|
Oct 03 04:28:21 AM UTC 24 |
Oct 03 04:28:24 AM UTC 24 |
77336499 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3319311805 |
|
|
Oct 03 04:27:53 AM UTC 24 |
Oct 03 04:28:24 AM UTC 24 |
15661468821 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.2485299255 |
|
|
Oct 03 04:28:22 AM UTC 24 |
Oct 03 04:28:25 AM UTC 24 |
38683892 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.547413251 |
|
|
Oct 03 04:27:07 AM UTC 24 |
Oct 03 04:28:25 AM UTC 24 |
26298067166 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.1913978580 |
|
|
Oct 03 04:28:23 AM UTC 24 |
Oct 03 04:28:25 AM UTC 24 |
22913936 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.30791129 |
|
|
Oct 03 04:24:31 AM UTC 24 |
Oct 03 04:28:25 AM UTC 24 |
18765779469 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3312216270 |
|
|
Oct 03 04:28:11 AM UTC 24 |
Oct 03 04:28:27 AM UTC 24 |
2769249576 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.1168858791 |
|
|
Oct 03 04:27:56 AM UTC 24 |
Oct 03 04:28:27 AM UTC 24 |
4098782052 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.296495587 |
|
|
Oct 03 04:27:14 AM UTC 24 |
Oct 03 04:28:28 AM UTC 24 |
4570131858 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.592409538 |
|
|
Oct 03 04:28:26 AM UTC 24 |
Oct 03 04:28:29 AM UTC 24 |
101482038 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.1792764035 |
|
|
Oct 03 04:27:20 AM UTC 24 |
Oct 03 04:28:29 AM UTC 24 |
9709064096 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.2850555071 |
|
|
Oct 03 04:28:26 AM UTC 24 |
Oct 03 04:28:30 AM UTC 24 |
120954116 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2375129781 |
|
|
Oct 03 04:28:26 AM UTC 24 |
Oct 03 04:28:31 AM UTC 24 |
285196188 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.228723534 |
|
|
Oct 03 04:28:16 AM UTC 24 |
Oct 03 04:28:31 AM UTC 24 |
1928960957 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.1781935753 |
|
|
Oct 03 04:29:10 AM UTC 24 |
Oct 03 04:29:20 AM UTC 24 |
995527513 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.4267426027 |
|
|
Oct 03 04:28:26 AM UTC 24 |
Oct 03 04:28:31 AM UTC 24 |
869243827 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.1470052485 |
|
|
Oct 03 04:28:10 AM UTC 24 |
Oct 03 04:28:32 AM UTC 24 |
2474870708 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.3510418022 |
|
|
Oct 03 04:28:23 AM UTC 24 |
Oct 03 04:28:32 AM UTC 24 |
3303373635 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.3799188962 |
|
|
Oct 03 04:28:28 AM UTC 24 |
Oct 03 04:28:33 AM UTC 24 |
1419331734 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.3041035435 |
|
|
Oct 03 04:28:29 AM UTC 24 |
Oct 03 04:28:33 AM UTC 24 |
1314360023 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.1734766657 |
|
|
Oct 03 04:28:33 AM UTC 24 |
Oct 03 04:28:35 AM UTC 24 |
68620061 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.2212082047 |
|
|
Oct 03 04:28:33 AM UTC 24 |
Oct 03 04:28:36 AM UTC 24 |
148122027 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1760862055 |
|
|
Oct 03 04:28:26 AM UTC 24 |
Oct 03 04:28:37 AM UTC 24 |
1019829114 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.2735160016 |
|
|
Oct 03 04:27:11 AM UTC 24 |
Oct 03 04:28:37 AM UTC 24 |
9236383824 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.3623982034 |
|
|
Oct 03 04:28:35 AM UTC 24 |
Oct 03 04:28:37 AM UTC 24 |
16022641 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.3579235427 |
|
|
Oct 03 04:28:35 AM UTC 24 |
Oct 03 04:28:37 AM UTC 24 |
44517126 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.671401774 |
|
|
Oct 03 04:28:29 AM UTC 24 |
Oct 03 04:28:38 AM UTC 24 |
334194763 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.160879905 |
|
|
Oct 03 04:28:36 AM UTC 24 |
Oct 03 04:28:38 AM UTC 24 |
31416042 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.2250868435 |
|
|
Oct 03 04:28:17 AM UTC 24 |
Oct 03 04:28:38 AM UTC 24 |
5655153731 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.2241938424 |
|
|
Oct 03 04:28:32 AM UTC 24 |
Oct 03 04:28:39 AM UTC 24 |
167133733 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.1934535686 |
|
|
Oct 03 04:28:05 AM UTC 24 |
Oct 03 04:28:41 AM UTC 24 |
18929307808 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.2982984487 |
|
|
Oct 03 04:28:28 AM UTC 24 |
Oct 03 04:28:41 AM UTC 24 |
977533350 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.1714860689 |
|
|
Oct 03 04:28:38 AM UTC 24 |
Oct 03 04:28:42 AM UTC 24 |
154206642 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1605395257 |
|
|
Oct 03 04:28:38 AM UTC 24 |
Oct 03 04:28:44 AM UTC 24 |
697506754 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.253566975 |
|
|
Oct 03 04:28:39 AM UTC 24 |
Oct 03 04:28:44 AM UTC 24 |
101550470 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.3818052888 |
|
|
Oct 03 04:26:27 AM UTC 24 |
Oct 03 04:28:45 AM UTC 24 |
14022722866 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4163258720 |
|
|
Oct 03 04:27:35 AM UTC 24 |
Oct 03 04:28:46 AM UTC 24 |
10027341356 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3049410303 |
|
|
Oct 03 04:23:43 AM UTC 24 |
Oct 03 04:28:46 AM UTC 24 |
33124445938 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.1530245962 |
|
|
Oct 03 04:28:37 AM UTC 24 |
Oct 03 04:28:46 AM UTC 24 |
960453586 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.1405904765 |
|
|
Oct 03 04:28:38 AM UTC 24 |
Oct 03 04:28:47 AM UTC 24 |
3167602038 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1339436828 |
|
|
Oct 03 04:28:35 AM UTC 24 |
Oct 03 04:28:47 AM UTC 24 |
1831015645 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.1139040111 |
|
|
Oct 03 04:28:46 AM UTC 24 |
Oct 03 04:28:48 AM UTC 24 |
22614131 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.3078842248 |
|
|
Oct 03 04:28:46 AM UTC 24 |
Oct 03 04:28:48 AM UTC 24 |
18252015 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.1411567345 |
|
|
Oct 03 04:28:25 AM UTC 24 |
Oct 03 04:28:50 AM UTC 24 |
1768375413 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1248232137 |
|
|
Oct 03 04:28:47 AM UTC 24 |
Oct 03 04:28:50 AM UTC 24 |
40942871 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.3185643833 |
|
|
Oct 03 04:28:49 AM UTC 24 |
Oct 03 04:28:51 AM UTC 24 |
26683289 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3805051136 |
|
|
Oct 03 04:28:47 AM UTC 24 |
Oct 03 04:28:51 AM UTC 24 |
325286022 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.3612749120 |
|
|
Oct 03 04:28:47 AM UTC 24 |
Oct 03 04:28:52 AM UTC 24 |
755995175 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3596938468 |
|
|
Oct 03 04:28:38 AM UTC 24 |
Oct 03 04:28:53 AM UTC 24 |
881928633 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.739803730 |
|
|
Oct 03 04:28:17 AM UTC 24 |
Oct 03 04:28:53 AM UTC 24 |
1527693758 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2264277302 |
|
|
Oct 03 04:23:28 AM UTC 24 |
Oct 03 04:28:55 AM UTC 24 |
29159670461 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.686920184 |
|
|
Oct 03 04:28:40 AM UTC 24 |
Oct 03 04:28:55 AM UTC 24 |
1337561448 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3694271271 |
|
|
Oct 03 04:28:50 AM UTC 24 |
Oct 03 04:28:55 AM UTC 24 |
269060619 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.3920759662 |
|
|
Oct 03 04:28:52 AM UTC 24 |
Oct 03 04:28:56 AM UTC 24 |
154802196 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3288929772 |
|
|
Oct 03 04:28:42 AM UTC 24 |
Oct 03 04:28:57 AM UTC 24 |
3427954612 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.3675694843 |
|
|
Oct 03 04:28:58 AM UTC 24 |
Oct 03 04:29:00 AM UTC 24 |
53384700 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3244908708 |
|
|
Oct 03 04:28:58 AM UTC 24 |
Oct 03 04:29:00 AM UTC 24 |
617560925 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3547210871 |
|
|
Oct 03 04:22:08 AM UTC 24 |
Oct 03 04:29:02 AM UTC 24 |
249299481116 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.1552292835 |
|
|
Oct 03 04:29:01 AM UTC 24 |
Oct 03 04:29:03 AM UTC 24 |
54949822 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.2922110820 |
|
|
Oct 03 04:28:39 AM UTC 24 |
Oct 03 04:29:04 AM UTC 24 |
37411671399 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.2852981511 |
|
|
Oct 03 04:28:53 AM UTC 24 |
Oct 03 04:29:04 AM UTC 24 |
219301151 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2066070126 |
|
|
Oct 03 04:28:50 AM UTC 24 |
Oct 03 04:29:05 AM UTC 24 |
10423371618 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3286067147 |
|
|
Oct 03 04:29:04 AM UTC 24 |
Oct 03 04:29:07 AM UTC 24 |
53279954 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.2449222586 |
|
|
Oct 03 04:29:04 AM UTC 24 |
Oct 03 04:29:07 AM UTC 24 |
79931010 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2770101746 |
|
|
Oct 03 04:29:05 AM UTC 24 |
Oct 03 04:29:09 AM UTC 24 |
30863053 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.4252311412 |
|
|
Oct 03 04:24:02 AM UTC 24 |
Oct 03 04:29:09 AM UTC 24 |
28548178230 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2130763907 |
|
|
Oct 03 04:28:18 AM UTC 24 |
Oct 03 04:29:10 AM UTC 24 |
3912892543 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.262935300 |
|
|
Oct 03 04:23:05 AM UTC 24 |
Oct 03 04:29:13 AM UTC 24 |
44561355253 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.15765950 |
|
|
Oct 03 04:28:51 AM UTC 24 |
Oct 03 04:29:13 AM UTC 24 |
2120186026 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.1722728991 |
|
|
Oct 03 04:26:22 AM UTC 24 |
Oct 03 04:29:14 AM UTC 24 |
17386928390 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.1964775962 |
|
|
Oct 03 04:28:51 AM UTC 24 |
Oct 03 04:29:16 AM UTC 24 |
4307185928 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3462588402 |
|
|
Oct 03 04:29:12 AM UTC 24 |
Oct 03 04:29:17 AM UTC 24 |
104918661 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1325776415 |
|
|
Oct 03 04:28:52 AM UTC 24 |
Oct 03 04:29:19 AM UTC 24 |
2548086017 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3180008632 |
|
|
Oct 03 04:28:53 AM UTC 24 |
Oct 03 04:29:17 AM UTC 24 |
5408185798 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2306599937 |
|
|
Oct 03 04:29:01 AM UTC 24 |
Oct 03 04:29:18 AM UTC 24 |
1516817629 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.2377689385 |
|
|
Oct 03 04:29:18 AM UTC 24 |
Oct 03 04:29:20 AM UTC 24 |
13419252 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.2862247567 |
|
|
Oct 03 04:29:18 AM UTC 24 |
Oct 03 04:29:20 AM UTC 24 |
17652710 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.2502938263 |
|
|
Oct 03 04:25:58 AM UTC 24 |
Oct 03 04:29:22 AM UTC 24 |
81906397261 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.1639998296 |
|
|
Oct 03 04:29:20 AM UTC 24 |
Oct 03 04:29:23 AM UTC 24 |
91972645 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.2223685919 |
|
|
Oct 03 04:29:21 AM UTC 24 |
Oct 03 04:29:25 AM UTC 24 |
146640529 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.1893164917 |
|
|
Oct 03 04:21:49 AM UTC 24 |
Oct 03 04:29:25 AM UTC 24 |
253148612815 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.4195794518 |
|
|
Oct 03 04:21:26 AM UTC 24 |
Oct 03 04:29:25 AM UTC 24 |
108254277674 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.1160618522 |
|
|
Oct 03 04:29:03 AM UTC 24 |
Oct 03 04:29:26 AM UTC 24 |
14119463556 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.3453643631 |
|
|
Oct 03 04:29:10 AM UTC 24 |
Oct 03 04:29:26 AM UTC 24 |
1052231488 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.2659532681 |
|
|
Oct 03 04:29:19 AM UTC 24 |
Oct 03 04:29:26 AM UTC 24 |
3527684511 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3795749462 |
|
|
Oct 03 04:28:57 AM UTC 24 |
Oct 03 04:29:27 AM UTC 24 |
4126093023 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.830783273 |
|
|
Oct 03 04:29:08 AM UTC 24 |
Oct 03 04:29:27 AM UTC 24 |
4039849137 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3865758444 |
|
|
Oct 03 04:29:06 AM UTC 24 |
Oct 03 04:29:29 AM UTC 24 |
4615029437 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.1562517048 |
|
|
Oct 03 04:29:26 AM UTC 24 |
Oct 03 04:29:30 AM UTC 24 |
56542503 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3646179006 |
|
|
Oct 03 04:23:13 AM UTC 24 |
Oct 03 04:29:31 AM UTC 24 |
318532681512 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.2862888894 |
|
|
Oct 03 04:26:38 AM UTC 24 |
Oct 03 04:29:31 AM UTC 24 |
16016801386 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.713671037 |
|
|
Oct 03 04:29:24 AM UTC 24 |
Oct 03 04:29:33 AM UTC 24 |
1179812799 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.2234455715 |
|
|
Oct 03 04:29:32 AM UTC 24 |
Oct 03 04:29:34 AM UTC 24 |
14763539 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.308035435 |
|
|
Oct 03 04:29:32 AM UTC 24 |
Oct 03 04:29:34 AM UTC 24 |
55066711 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1623366925 |
|
|
Oct 03 04:29:27 AM UTC 24 |
Oct 03 04:29:34 AM UTC 24 |
262574817 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.3432124327 |
|
|
Oct 03 04:29:32 AM UTC 24 |
Oct 03 04:29:34 AM UTC 24 |
197366075 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.1461459297 |
|
|
Oct 03 04:29:28 AM UTC 24 |
Oct 03 04:29:35 AM UTC 24 |
1877580808 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.551840227 |
|
|
Oct 03 04:29:26 AM UTC 24 |
Oct 03 04:29:35 AM UTC 24 |
280637192 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.4071263501 |
|
|
Oct 03 04:29:35 AM UTC 24 |
Oct 03 04:29:37 AM UTC 24 |
50481480 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.2985349192 |
|
|
Oct 03 04:29:20 AM UTC 24 |
Oct 03 04:29:37 AM UTC 24 |
3550007929 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.1945514707 |
|
|
Oct 03 04:29:35 AM UTC 24 |
Oct 03 04:29:38 AM UTC 24 |
39724465 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2983740704 |
|
|
Oct 03 04:29:24 AM UTC 24 |
Oct 03 04:29:38 AM UTC 24 |
8153468868 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1352823212 |
|
|
Oct 03 04:27:19 AM UTC 24 |
Oct 03 04:29:41 AM UTC 24 |
54954276192 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3314576391 |
|
|
Oct 03 04:27:58 AM UTC 24 |
Oct 03 04:29:41 AM UTC 24 |
13312807996 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.4201147409 |
|
|
Oct 03 04:28:32 AM UTC 24 |
Oct 03 04:29:41 AM UTC 24 |
2541709784 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.2786208413 |
|
|
Oct 03 04:29:32 AM UTC 24 |
Oct 03 04:29:42 AM UTC 24 |
1798579634 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3499659758 |
|
|
Oct 03 04:29:38 AM UTC 24 |
Oct 03 04:29:43 AM UTC 24 |
461674256 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.1296865267 |
|
|
Oct 03 04:29:08 AM UTC 24 |
Oct 03 04:29:43 AM UTC 24 |
19187361012 ps |