| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.555348032 |
|
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Oct 03 04:29:37 AM UTC 24 |
Oct 03 04:29:44 AM UTC 24 |
429942532 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.972376866 |
|
|
Oct 03 04:29:44 AM UTC 24 |
Oct 03 04:29:47 AM UTC 24 |
78299954 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.1746479443 |
|
|
Oct 03 04:29:45 AM UTC 24 |
Oct 03 04:29:48 AM UTC 24 |
19157583 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.2726491460 |
|
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Oct 03 04:29:08 AM UTC 24 |
Oct 03 04:29:48 AM UTC 24 |
16044351645 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.3080198559 |
|
|
Oct 03 04:29:28 AM UTC 24 |
Oct 03 04:29:48 AM UTC 24 |
3993329943 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.2107918880 |
|
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Oct 03 04:29:35 AM UTC 24 |
Oct 03 04:29:49 AM UTC 24 |
9359298146 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2374402235 |
|
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Oct 03 04:29:49 AM UTC 24 |
Oct 03 04:29:52 AM UTC 24 |
60492835 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2940758574 |
|
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Oct 03 04:29:41 AM UTC 24 |
Oct 03 04:29:52 AM UTC 24 |
457510475 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.1598738649 |
|
|
Oct 03 04:29:49 AM UTC 24 |
Oct 03 04:29:52 AM UTC 24 |
28576697 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.3085655929 |
|
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Oct 03 04:29:21 AM UTC 24 |
Oct 03 04:29:52 AM UTC 24 |
14344426389 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1748544935 |
|
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Oct 03 04:29:38 AM UTC 24 |
Oct 03 04:29:53 AM UTC 24 |
654101729 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.2621729452 |
|
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Oct 03 04:29:37 AM UTC 24 |
Oct 03 04:29:55 AM UTC 24 |
9500317529 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3309570182 |
|
|
Oct 03 04:29:53 AM UTC 24 |
Oct 03 04:29:58 AM UTC 24 |
67941730 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3755089345 |
|
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Oct 03 04:27:56 AM UTC 24 |
Oct 03 04:29:58 AM UTC 24 |
13902011326 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.653990360 |
|
|
Oct 03 04:29:55 AM UTC 24 |
Oct 03 04:29:59 AM UTC 24 |
31954789 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.4218993495 |
|
|
Oct 03 04:29:47 AM UTC 24 |
Oct 03 04:30:01 AM UTC 24 |
8301218882 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.3926870778 |
|
|
Oct 03 04:29:53 AM UTC 24 |
Oct 03 04:30:03 AM UTC 24 |
264006022 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3165166679 |
|
|
Oct 03 04:29:35 AM UTC 24 |
Oct 03 04:30:03 AM UTC 24 |
6322444033 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2174838817 |
|
|
Oct 03 04:29:59 AM UTC 24 |
Oct 03 04:30:06 AM UTC 24 |
114477184 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.2149819380 |
|
|
Oct 03 04:29:39 AM UTC 24 |
Oct 03 04:30:08 AM UTC 24 |
1002063161 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.885637917 |
|
|
Oct 03 04:30:07 AM UTC 24 |
Oct 03 04:30:09 AM UTC 24 |
22457835 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.2954106838 |
|
|
Oct 03 04:30:09 AM UTC 24 |
Oct 03 04:30:11 AM UTC 24 |
28882067 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.2815495817 |
|
|
Oct 03 04:29:43 AM UTC 24 |
Oct 03 04:30:12 AM UTC 24 |
2576916716 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.3130501180 |
|
|
Oct 03 04:29:54 AM UTC 24 |
Oct 03 04:30:13 AM UTC 24 |
2405361144 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1211620851 |
|
|
Oct 03 04:29:14 AM UTC 24 |
Oct 03 04:30:14 AM UTC 24 |
5534693814 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3425488831 |
|
|
Oct 03 04:29:34 AM UTC 24 |
Oct 03 04:30:15 AM UTC 24 |
5379976092 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.3403605874 |
|
|
Oct 03 04:30:12 AM UTC 24 |
Oct 03 04:30:15 AM UTC 24 |
174646803 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.1449385114 |
|
|
Oct 03 04:30:15 AM UTC 24 |
Oct 03 04:30:19 AM UTC 24 |
708917301 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.2152895340 |
|
|
Oct 03 04:28:44 AM UTC 24 |
Oct 03 04:30:20 AM UTC 24 |
5012000542 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.4151956464 |
|
|
Oct 03 04:29:10 AM UTC 24 |
Oct 03 04:30:20 AM UTC 24 |
31021310116 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.1769494657 |
|
|
Oct 03 04:29:56 AM UTC 24 |
Oct 03 04:30:21 AM UTC 24 |
11519680867 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3608909200 |
|
|
Oct 03 04:30:16 AM UTC 24 |
Oct 03 04:30:21 AM UTC 24 |
599066950 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.3924251427 |
|
|
Oct 03 04:27:40 AM UTC 24 |
Oct 03 04:30:21 AM UTC 24 |
8493070397 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1206505071 |
|
|
Oct 03 04:29:50 AM UTC 24 |
Oct 03 04:30:21 AM UTC 24 |
51335511933 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.3344456746 |
|
|
Oct 03 04:30:16 AM UTC 24 |
Oct 03 04:30:23 AM UTC 24 |
116539379 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2502642391 |
|
|
Oct 03 04:30:16 AM UTC 24 |
Oct 03 04:30:25 AM UTC 24 |
1062119154 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3550040230 |
|
|
Oct 03 04:30:26 AM UTC 24 |
Oct 03 04:30:28 AM UTC 24 |
155498077 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3638373386 |
|
|
Oct 03 04:30:22 AM UTC 24 |
Oct 03 04:30:28 AM UTC 24 |
243842196 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1551938977 |
|
|
Oct 03 04:30:21 AM UTC 24 |
Oct 03 04:30:28 AM UTC 24 |
319305528 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.2579858478 |
|
|
Oct 03 04:28:00 AM UTC 24 |
Oct 03 04:30:29 AM UTC 24 |
6828500346 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3720966552 |
|
|
Oct 03 04:28:43 AM UTC 24 |
Oct 03 04:30:31 AM UTC 24 |
28490426393 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.3697763988 |
|
|
Oct 03 04:30:29 AM UTC 24 |
Oct 03 04:30:31 AM UTC 24 |
39938693 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.522899017 |
|
|
Oct 03 04:30:29 AM UTC 24 |
Oct 03 04:30:31 AM UTC 24 |
26452282 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2598704895 |
|
|
Oct 03 04:30:10 AM UTC 24 |
Oct 03 04:30:32 AM UTC 24 |
15808285616 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1627142270 |
|
|
Oct 03 04:30:31 AM UTC 24 |
Oct 03 04:30:34 AM UTC 24 |
138897593 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2797369431 |
|
|
Oct 03 04:29:28 AM UTC 24 |
Oct 03 04:30:35 AM UTC 24 |
42954598253 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.2437188260 |
|
|
Oct 03 04:26:27 AM UTC 24 |
Oct 03 04:30:37 AM UTC 24 |
11772831006 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2741501235 |
|
|
Oct 03 04:30:33 AM UTC 24 |
Oct 03 04:30:37 AM UTC 24 |
67840414 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.2289738075 |
|
|
Oct 03 04:29:49 AM UTC 24 |
Oct 03 04:30:37 AM UTC 24 |
8019483799 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1052924914 |
|
|
Oct 03 04:30:33 AM UTC 24 |
Oct 03 04:30:37 AM UTC 24 |
116294212 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.1525450899 |
|
|
Oct 03 04:30:31 AM UTC 24 |
Oct 03 04:30:38 AM UTC 24 |
191810846 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.2537419109 |
|
|
Oct 03 04:30:22 AM UTC 24 |
Oct 03 04:30:39 AM UTC 24 |
4634148129 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3654437293 |
|
|
Oct 03 04:28:55 AM UTC 24 |
Oct 03 04:30:40 AM UTC 24 |
41930139869 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.3555857446 |
|
|
Oct 03 04:28:43 AM UTC 24 |
Oct 03 04:30:40 AM UTC 24 |
22860406753 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.1107151580 |
|
|
Oct 03 04:30:30 AM UTC 24 |
Oct 03 04:30:40 AM UTC 24 |
2064844740 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3310521567 |
|
|
Oct 03 04:30:39 AM UTC 24 |
Oct 03 04:30:41 AM UTC 24 |
67413022 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.24655154 |
|
|
Oct 03 04:30:29 AM UTC 24 |
Oct 03 04:30:41 AM UTC 24 |
32210308342 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2662316247 |
|
|
Oct 03 04:28:31 AM UTC 24 |
Oct 03 04:30:42 AM UTC 24 |
13386795987 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3992893032 |
|
|
Oct 03 04:30:41 AM UTC 24 |
Oct 03 04:30:44 AM UTC 24 |
11173539 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.1825547250 |
|
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Oct 03 04:30:43 AM UTC 24 |
Oct 03 04:30:45 AM UTC 24 |
20996320 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3251777124 |
|
|
Oct 03 04:30:43 AM UTC 24 |
Oct 03 04:30:45 AM UTC 24 |
69796141 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.1883222370 |
|
|
Oct 03 04:30:22 AM UTC 24 |
Oct 03 04:30:46 AM UTC 24 |
1310972327 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.615674278 |
|
|
Oct 03 04:30:45 AM UTC 24 |
Oct 03 04:30:47 AM UTC 24 |
40634355 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.4158011592 |
|
|
Oct 03 04:30:36 AM UTC 24 |
Oct 03 04:30:47 AM UTC 24 |
901613590 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2606852426 |
|
|
Oct 03 04:30:46 AM UTC 24 |
Oct 03 04:30:49 AM UTC 24 |
128312402 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.1256382133 |
|
|
Oct 03 04:30:46 AM UTC 24 |
Oct 03 04:30:50 AM UTC 24 |
65049471 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1506917477 |
|
|
Oct 03 04:30:41 AM UTC 24 |
Oct 03 04:30:50 AM UTC 24 |
3035179280 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2237583106 |
|
|
Oct 03 04:30:35 AM UTC 24 |
Oct 03 04:30:51 AM UTC 24 |
24216085637 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2535688487 |
|
|
Oct 03 04:30:47 AM UTC 24 |
Oct 03 04:30:51 AM UTC 24 |
31924454 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3507032312 |
|
|
Oct 03 04:28:40 AM UTC 24 |
Oct 03 04:30:53 AM UTC 24 |
249814984766 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.2848382753 |
|
|
Oct 03 04:30:39 AM UTC 24 |
Oct 03 04:30:53 AM UTC 24 |
673337726 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.1218233593 |
|
|
Oct 03 04:30:00 AM UTC 24 |
Oct 03 04:30:54 AM UTC 24 |
17131850398 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1036844414 |
|
|
Oct 03 04:30:40 AM UTC 24 |
Oct 03 04:30:55 AM UTC 24 |
1421452735 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1308723352 |
|
|
Oct 03 04:30:51 AM UTC 24 |
Oct 03 04:30:55 AM UTC 24 |
200616134 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.2066117415 |
|
|
Oct 03 04:30:49 AM UTC 24 |
Oct 03 04:30:56 AM UTC 24 |
863621129 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.4157750263 |
|
|
Oct 03 04:30:20 AM UTC 24 |
Oct 03 04:30:57 AM UTC 24 |
5956738184 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.596807561 |
|
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Oct 03 04:30:52 AM UTC 24 |
Oct 03 04:30:57 AM UTC 24 |
370876849 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.1533372974 |
|
|
Oct 03 04:30:12 AM UTC 24 |
Oct 03 04:30:58 AM UTC 24 |
16179280772 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.294178067 |
|
|
Oct 03 04:30:56 AM UTC 24 |
Oct 03 04:30:59 AM UTC 24 |
188798335 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.4054070027 |
|
|
Oct 03 04:30:57 AM UTC 24 |
Oct 03 04:30:59 AM UTC 24 |
12017898 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.3527878308 |
|
|
Oct 03 04:30:49 AM UTC 24 |
Oct 03 04:31:00 AM UTC 24 |
4029465514 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1075558895 |
|
|
Oct 03 04:30:02 AM UTC 24 |
Oct 03 04:31:01 AM UTC 24 |
41606148783 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.2921911946 |
|
|
Oct 03 04:30:58 AM UTC 24 |
Oct 03 04:31:01 AM UTC 24 |
83996236 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1424384257 |
|
|
Oct 03 04:31:00 AM UTC 24 |
Oct 03 04:31:02 AM UTC 24 |
48512363 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.3813561502 |
|
|
Oct 03 04:31:00 AM UTC 24 |
Oct 03 04:31:03 AM UTC 24 |
76582983 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.1203772965 |
|
|
Oct 03 04:30:37 AM UTC 24 |
Oct 03 04:31:03 AM UTC 24 |
3581703753 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.1116004475 |
|
|
Oct 03 04:25:20 AM UTC 24 |
Oct 03 04:31:05 AM UTC 24 |
117780964432 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.4206529994 |
|
|
Oct 03 04:30:55 AM UTC 24 |
Oct 03 04:31:07 AM UTC 24 |
846781463 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2941341027 |
|
|
Oct 03 04:30:51 AM UTC 24 |
Oct 03 04:31:08 AM UTC 24 |
1734953400 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.2041781842 |
|
|
Oct 03 04:31:01 AM UTC 24 |
Oct 03 04:31:09 AM UTC 24 |
774353322 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.796047210 |
|
|
Oct 03 04:30:39 AM UTC 24 |
Oct 03 04:31:10 AM UTC 24 |
4303818676 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.1835971214 |
|
|
Oct 03 04:31:01 AM UTC 24 |
Oct 03 04:31:10 AM UTC 24 |
7638377054 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.2991843215 |
|
|
Oct 03 04:31:05 AM UTC 24 |
Oct 03 04:31:11 AM UTC 24 |
208914063 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.2543587460 |
|
|
Oct 03 04:30:59 AM UTC 24 |
Oct 03 04:31:11 AM UTC 24 |
1327152138 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.4284829663 |
|
|
Oct 03 04:31:10 AM UTC 24 |
Oct 03 04:31:12 AM UTC 24 |
12977063 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.1179203806 |
|
|
Oct 03 04:31:12 AM UTC 24 |
Oct 03 04:31:14 AM UTC 24 |
20576399 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.1446533983 |
|
|
Oct 03 04:30:50 AM UTC 24 |
Oct 03 04:31:15 AM UTC 24 |
8084913531 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.473177604 |
|
|
Oct 03 04:29:53 AM UTC 24 |
Oct 03 04:31:15 AM UTC 24 |
14392243860 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.500590990 |
|
|
Oct 03 04:31:13 AM UTC 24 |
Oct 03 04:31:15 AM UTC 24 |
71106475 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2515434077 |
|
|
Oct 03 04:30:41 AM UTC 24 |
Oct 03 04:31:18 AM UTC 24 |
3699615860 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.2190448294 |
|
|
Oct 03 04:31:16 AM UTC 24 |
Oct 03 04:31:19 AM UTC 24 |
79427261 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.2398542928 |
|
|
Oct 03 04:31:07 AM UTC 24 |
Oct 03 04:31:20 AM UTC 24 |
312960272 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.2757860020 |
|
|
Oct 03 04:30:58 AM UTC 24 |
Oct 03 04:31:20 AM UTC 24 |
30044055074 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.2391545508 |
|
|
Oct 03 04:31:16 AM UTC 24 |
Oct 03 04:31:21 AM UTC 24 |
470047578 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.25689690 |
|
|
Oct 03 04:31:09 AM UTC 24 |
Oct 03 04:31:24 AM UTC 24 |
2741310851 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.357821686 |
|
|
Oct 03 04:29:30 AM UTC 24 |
Oct 03 04:31:24 AM UTC 24 |
14124598045 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3638666918 |
|
|
Oct 03 04:31:01 AM UTC 24 |
Oct 03 04:31:25 AM UTC 24 |
6597934262 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.2658684010 |
|
|
Oct 03 04:31:21 AM UTC 24 |
Oct 03 04:31:26 AM UTC 24 |
97763961 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.187644582 |
|
|
Oct 03 04:30:20 AM UTC 24 |
Oct 03 04:31:26 AM UTC 24 |
18759902417 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1170306652 |
|
|
Oct 03 04:31:20 AM UTC 24 |
Oct 03 04:31:27 AM UTC 24 |
180750061 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.303145978 |
|
|
Oct 03 04:31:21 AM UTC 24 |
Oct 03 04:31:28 AM UTC 24 |
822279154 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.3554069834 |
|
|
Oct 03 04:31:15 AM UTC 24 |
Oct 03 04:31:29 AM UTC 24 |
1359763659 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3772501026 |
|
|
Oct 03 04:31:20 AM UTC 24 |
Oct 03 04:31:30 AM UTC 24 |
469613954 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.196776756 |
|
|
Oct 03 04:31:16 AM UTC 24 |
Oct 03 04:31:31 AM UTC 24 |
2495389621 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3031644089 |
|
|
Oct 03 04:31:24 AM UTC 24 |
Oct 03 04:31:32 AM UTC 24 |
261951008 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.3834156711 |
|
|
Oct 03 04:31:31 AM UTC 24 |
Oct 03 04:31:33 AM UTC 24 |
30362388 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.247685411 |
|
|
Oct 03 04:31:32 AM UTC 24 |
Oct 03 04:31:34 AM UTC 24 |
25247872 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1188862314 |
|
|
Oct 03 04:29:28 AM UTC 24 |
Oct 03 04:31:36 AM UTC 24 |
6970811042 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.1852113881 |
|
|
Oct 03 04:31:26 AM UTC 24 |
Oct 03 04:31:37 AM UTC 24 |
1353491809 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3629407391 |
|
|
Oct 03 04:29:43 AM UTC 24 |
Oct 03 04:31:37 AM UTC 24 |
8294831397 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3032853000 |
|
|
Oct 03 04:31:27 AM UTC 24 |
Oct 03 04:31:37 AM UTC 24 |
620996121 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.941837457 |
|
|
Oct 03 04:31:35 AM UTC 24 |
Oct 03 04:31:38 AM UTC 24 |
138532650 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.543547355 |
|
|
Oct 03 04:31:34 AM UTC 24 |
Oct 03 04:31:39 AM UTC 24 |
1005169294 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.4026805899 |
|
|
Oct 03 04:30:04 AM UTC 24 |
Oct 03 04:31:39 AM UTC 24 |
2672897809 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.702650872 |
|
|
Oct 03 04:31:38 AM UTC 24 |
Oct 03 04:31:40 AM UTC 24 |
35846704 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.2189849955 |
|
|
Oct 03 04:25:36 AM UTC 24 |
Oct 03 04:31:43 AM UTC 24 |
45290900302 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2315457120 |
|
|
Oct 03 04:31:39 AM UTC 24 |
Oct 03 04:31:43 AM UTC 24 |
156436611 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1054171791 |
|
|
Oct 03 04:31:40 AM UTC 24 |
Oct 03 04:31:46 AM UTC 24 |
62092477 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.1981756109 |
|
|
Oct 03 04:31:40 AM UTC 24 |
Oct 03 04:31:47 AM UTC 24 |
1780346225 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.3896762727 |
|
|
Oct 03 04:31:41 AM UTC 24 |
Oct 03 04:31:48 AM UTC 24 |
238587428 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.2844705384 |
|
|
Oct 03 04:31:03 AM UTC 24 |
Oct 03 04:31:49 AM UTC 24 |
7522113712 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1551409065 |
|
|
Oct 03 04:31:39 AM UTC 24 |
Oct 03 04:31:50 AM UTC 24 |
2104002337 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.1588508767 |
|
|
Oct 03 04:31:44 AM UTC 24 |
Oct 03 04:31:51 AM UTC 24 |
679326805 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.3916598917 |
|
|
Oct 03 04:29:15 AM UTC 24 |
Oct 03 04:31:52 AM UTC 24 |
36950777186 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.250640898 |
|
|
Oct 03 04:30:25 AM UTC 24 |
Oct 03 04:31:52 AM UTC 24 |
14337165269 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.3037427254 |
|
|
Oct 03 04:30:40 AM UTC 24 |
Oct 03 04:31:53 AM UTC 24 |
11780119722 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1270236029 |
|
|
Oct 03 04:31:38 AM UTC 24 |
Oct 03 04:31:53 AM UTC 24 |
936371660 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.2136145345 |
|
|
Oct 03 04:31:52 AM UTC 24 |
Oct 03 04:31:54 AM UTC 24 |
15739660 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1159326062 |
|
|
Oct 03 04:24:04 AM UTC 24 |
Oct 03 04:31:54 AM UTC 24 |
57681574450 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3942866353 |
|
|
Oct 03 04:31:52 AM UTC 24 |
Oct 03 04:31:54 AM UTC 24 |
27408047 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2096450542 |
|
|
Oct 03 04:22:06 AM UTC 24 |
Oct 03 04:31:55 AM UTC 24 |
54087560523 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.2074737722 |
|
|
Oct 03 04:31:33 AM UTC 24 |
Oct 03 04:31:56 AM UTC 24 |
13655235343 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2201900327 |
|
|
Oct 03 04:31:54 AM UTC 24 |
Oct 03 04:31:57 AM UTC 24 |
47938723 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.1181690364 |
|
|
Oct 03 04:29:14 AM UTC 24 |
Oct 03 04:31:57 AM UTC 24 |
12747781457 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3153216182 |
|
|
Oct 03 04:31:54 AM UTC 24 |
Oct 03 04:31:58 AM UTC 24 |
33700779 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.368039788 |
|
|
Oct 03 04:31:53 AM UTC 24 |
Oct 03 04:31:59 AM UTC 24 |
2362716742 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.663138716 |
|
|
Oct 03 04:31:54 AM UTC 24 |
Oct 03 04:31:59 AM UTC 24 |
96280229 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.57294029 |
|
|
Oct 03 04:31:56 AM UTC 24 |
Oct 03 04:32:00 AM UTC 24 |
109919450 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.376053933 |
|
|
Oct 03 04:31:57 AM UTC 24 |
Oct 03 04:32:02 AM UTC 24 |
910331880 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1849112332 |
|
|
Oct 03 04:28:53 AM UTC 24 |
Oct 03 04:32:02 AM UTC 24 |
103764031370 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.3968192060 |
|
|
Oct 03 04:31:57 AM UTC 24 |
Oct 03 04:32:02 AM UTC 24 |
470363833 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2574335056 |
|
|
Oct 03 04:27:39 AM UTC 24 |
Oct 03 04:32:02 AM UTC 24 |
107371697948 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2870268894 |
|
|
Oct 03 04:32:00 AM UTC 24 |
Oct 03 04:32:02 AM UTC 24 |
58936928 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.2231994427 |
|
|
Oct 03 04:31:21 AM UTC 24 |
Oct 03 04:32:02 AM UTC 24 |
5743981432 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2695039099 |
|
|
Oct 03 04:31:44 AM UTC 24 |
Oct 03 04:32:03 AM UTC 24 |
1959886530 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.725877729 |
|
|
Oct 03 04:31:56 AM UTC 24 |
Oct 03 04:32:04 AM UTC 24 |
366580908 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.3574229835 |
|
|
Oct 03 04:32:03 AM UTC 24 |
Oct 03 04:32:05 AM UTC 24 |
19870959 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1975624034 |
|
|
Oct 03 04:31:38 AM UTC 24 |
Oct 03 04:32:05 AM UTC 24 |
50165454487 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.3242042503 |
|
|
Oct 03 04:32:03 AM UTC 24 |
Oct 03 04:32:05 AM UTC 24 |
18086500 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.746936230 |
|
|
Oct 03 04:32:04 AM UTC 24 |
Oct 03 04:32:06 AM UTC 24 |
150586098 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2290858851 |
|
|
Oct 03 04:28:33 AM UTC 24 |
Oct 03 04:32:06 AM UTC 24 |
81156099465 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1289968433 |
|
|
Oct 03 04:32:34 AM UTC 24 |
Oct 03 04:32:36 AM UTC 24 |
22638695 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.1518051629 |
|
|
Oct 03 04:32:04 AM UTC 24 |
Oct 03 04:32:08 AM UTC 24 |
439146674 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.3637655975 |
|
|
Oct 03 04:32:04 AM UTC 24 |
Oct 03 04:32:09 AM UTC 24 |
170898491 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1474451434 |
|
|
Oct 03 04:32:00 AM UTC 24 |
Oct 03 04:32:10 AM UTC 24 |
223744269 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.3032636798 |
|
|
Oct 03 04:32:07 AM UTC 24 |
Oct 03 04:32:12 AM UTC 24 |
396997019 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2498473176 |
|
|
Oct 03 04:32:06 AM UTC 24 |
Oct 03 04:32:12 AM UTC 24 |
946506551 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.1082095669 |
|
|
Oct 03 04:32:06 AM UTC 24 |
Oct 03 04:32:14 AM UTC 24 |
821361945 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.3924211689 |
|
|
Oct 03 04:31:58 AM UTC 24 |
Oct 03 04:32:14 AM UTC 24 |
2899357042 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.441679463 |
|
|
Oct 03 04:32:06 AM UTC 24 |
Oct 03 04:32:14 AM UTC 24 |
1239352384 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.902909071 |
|
|
Oct 03 04:32:08 AM UTC 24 |
Oct 03 04:32:15 AM UTC 24 |
284820263 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.2794405323 |
|
|
Oct 03 04:31:47 AM UTC 24 |
Oct 03 04:32:16 AM UTC 24 |
5296111335 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.2204840675 |
|
|
Oct 03 04:32:16 AM UTC 24 |
Oct 03 04:32:18 AM UTC 24 |
32337650 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.3252093802 |
|
|
Oct 03 04:32:16 AM UTC 24 |
Oct 03 04:32:18 AM UTC 24 |
40976892 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2656546500 |
|
|
Oct 03 04:32:04 AM UTC 24 |
Oct 03 04:32:19 AM UTC 24 |
6134607584 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.4149568765 |
|
|
Oct 03 04:32:13 AM UTC 24 |
Oct 03 04:32:19 AM UTC 24 |
114244243 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.2908856868 |
|
|
Oct 03 04:32:17 AM UTC 24 |
Oct 03 04:32:19 AM UTC 24 |
16952556 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2114888745 |
|
|
Oct 03 04:29:39 AM UTC 24 |
Oct 03 04:32:20 AM UTC 24 |
74924768955 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2362260670 |
|
|
Oct 03 04:32:20 AM UTC 24 |
Oct 03 04:32:22 AM UTC 24 |
126070577 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2440257343 |
|
|
Oct 03 04:25:02 AM UTC 24 |
Oct 03 04:32:22 AM UTC 24 |
43516222749 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.4006013309 |
|
|
Oct 03 04:32:21 AM UTC 24 |
Oct 03 04:32:23 AM UTC 24 |
98532698 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.1502789811 |
|
|
Oct 03 04:31:03 AM UTC 24 |
Oct 03 04:32:23 AM UTC 24 |
10664642027 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.161802795 |
|
|
Oct 03 04:28:33 AM UTC 24 |
Oct 03 04:32:24 AM UTC 24 |
23526155211 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.4277802137 |
|
|
Oct 03 04:31:12 AM UTC 24 |
Oct 03 04:32:28 AM UTC 24 |
4020969740 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.13304980 |
|
|
Oct 03 04:32:21 AM UTC 24 |
Oct 03 04:32:28 AM UTC 24 |
129357119 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2605854067 |
|
|
Oct 03 04:32:19 AM UTC 24 |
Oct 03 04:32:28 AM UTC 24 |
1415849197 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.819185291 |
|
|
Oct 03 04:32:22 AM UTC 24 |
Oct 03 04:32:28 AM UTC 24 |
157359782 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2033494249 |
|
|
Oct 03 04:31:27 AM UTC 24 |
Oct 03 04:32:29 AM UTC 24 |
2069283468 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.348508942 |
|
|
Oct 03 04:32:19 AM UTC 24 |
Oct 03 04:32:33 AM UTC 24 |
1437240458 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.1521883881 |
|
|
Oct 03 04:32:25 AM UTC 24 |
Oct 03 04:32:33 AM UTC 24 |
2469961656 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.449451744 |
|
|
Oct 03 04:28:45 AM UTC 24 |
Oct 03 04:32:33 AM UTC 24 |
11239659966 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.243027871 |
|
|
Oct 03 04:32:21 AM UTC 24 |
Oct 03 04:32:35 AM UTC 24 |
925421433 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.4110022228 |
|
|
Oct 03 04:32:23 AM UTC 24 |
Oct 03 04:32:36 AM UTC 24 |
3971234912 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.446144082 |
|
|
Oct 03 04:32:34 AM UTC 24 |
Oct 03 04:32:36 AM UTC 24 |
18937991 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.2208812649 |
|
|
Oct 03 04:32:11 AM UTC 24 |
Oct 03 04:32:36 AM UTC 24 |
2925293610 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.2845219116 |
|
|
Oct 03 04:32:29 AM UTC 24 |
Oct 03 04:32:37 AM UTC 24 |
2191606868 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1398489565 |
|
|
Oct 03 04:32:03 AM UTC 24 |
Oct 03 04:32:37 AM UTC 24 |
5279837035 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3691896097 |
|
|
Oct 03 04:32:25 AM UTC 24 |
Oct 03 04:32:40 AM UTC 24 |
6425366673 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3393575025 |
|
|
Oct 03 04:32:38 AM UTC 24 |
Oct 03 04:32:40 AM UTC 24 |
67331945 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.127709960 |
|
|
Oct 03 04:32:38 AM UTC 24 |
Oct 03 04:32:41 AM UTC 24 |
29833685 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3833166441 |
|
|
Oct 03 04:32:38 AM UTC 24 |
Oct 03 04:32:42 AM UTC 24 |
52660253 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.2109219260 |
|
|
Oct 03 04:32:38 AM UTC 24 |
Oct 03 04:32:44 AM UTC 24 |
145897936 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2757407546 |
|
|
Oct 03 04:32:42 AM UTC 24 |
Oct 03 04:32:46 AM UTC 24 |
58703054 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1654820744 |
|
|
Oct 03 04:32:38 AM UTC 24 |
Oct 03 04:32:47 AM UTC 24 |
337058597 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.1696997044 |
|
|
Oct 03 04:32:25 AM UTC 24 |
Oct 03 04:32:47 AM UTC 24 |
1025489474 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.2941867673 |
|
|
Oct 03 04:30:56 AM UTC 24 |
Oct 03 04:32:47 AM UTC 24 |
54092659878 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.2269391891 |
|
|
Oct 03 04:31:56 AM UTC 24 |
Oct 03 04:32:48 AM UTC 24 |
17505470894 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.607541031 |
|
|
Oct 03 04:32:36 AM UTC 24 |
Oct 03 04:32:50 AM UTC 24 |
4592790229 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2993036014 |
|
|
Oct 03 04:32:29 AM UTC 24 |
Oct 03 04:32:51 AM UTC 24 |
1218232312 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.884351506 |
|
|
Oct 03 04:31:48 AM UTC 24 |
Oct 03 04:32:51 AM UTC 24 |
17414831787 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.2801127080 |
|
|
Oct 03 04:31:53 AM UTC 24 |
Oct 03 04:32:52 AM UTC 24 |
12734734613 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.400099817 |
|
|
Oct 03 04:32:42 AM UTC 24 |
Oct 03 04:32:52 AM UTC 24 |
2398263827 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1368643912 |
|
|
Oct 03 04:28:16 AM UTC 24 |
Oct 03 04:32:52 AM UTC 24 |
440809684615 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.655243902 |
|
|
Oct 03 04:32:46 AM UTC 24 |
Oct 03 04:32:53 AM UTC 24 |
761241340 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.1757821611 |
|
|
Oct 03 04:32:51 AM UTC 24 |
Oct 03 04:32:53 AM UTC 24 |
40747356 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.120582770 |
|
|
Oct 03 04:32:43 AM UTC 24 |
Oct 03 04:32:54 AM UTC 24 |
1763486071 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.1340755548 |
|
|
Oct 03 04:32:53 AM UTC 24 |
Oct 03 04:32:55 AM UTC 24 |
40162504 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.4165562563 |
|
|
Oct 03 04:32:53 AM UTC 24 |
Oct 03 04:32:55 AM UTC 24 |
71770899 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.688901405 |
|
|
Oct 03 04:32:54 AM UTC 24 |
Oct 03 04:32:58 AM UTC 24 |
113850019 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.2815548417 |
|
|
Oct 03 04:32:56 AM UTC 24 |
Oct 03 04:32:59 AM UTC 24 |
117370105 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.104821010 |
|
|
Oct 03 04:32:56 AM UTC 24 |
Oct 03 04:33:01 AM UTC 24 |
112557483 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.1255546496 |
|
|
Oct 03 04:31:29 AM UTC 24 |
Oct 03 04:33:01 AM UTC 24 |
17652913749 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.229668920 |
|
|
Oct 03 04:32:53 AM UTC 24 |
Oct 03 04:33:02 AM UTC 24 |
579568835 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.2204396118 |
|
|
Oct 03 04:30:41 AM UTC 24 |
Oct 03 04:33:03 AM UTC 24 |
30370477074 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.2597891148 |
|
|
Oct 03 04:32:56 AM UTC 24 |
Oct 03 04:33:03 AM UTC 24 |
958636504 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.3510276963 |
|
|
Oct 03 04:27:14 AM UTC 24 |
Oct 03 04:33:05 AM UTC 24 |
48631908046 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1668597140 |
|
|
Oct 03 04:33:02 AM UTC 24 |
Oct 03 04:33:07 AM UTC 24 |
290916049 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.413647477 |
|
|
Oct 03 04:31:12 AM UTC 24 |
Oct 03 04:33:08 AM UTC 24 |
6545549560 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.3150410375 |
|
|
Oct 03 04:28:57 AM UTC 24 |
Oct 03 04:33:09 AM UTC 24 |
30589945527 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.2397993464 |
|
|
Oct 03 04:33:07 AM UTC 24 |
Oct 03 04:33:09 AM UTC 24 |
13173474 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.1732102322 |
|
|
Oct 03 04:32:54 AM UTC 24 |
Oct 03 04:33:09 AM UTC 24 |
2178784569 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.2294268990 |
|
|
Oct 03 04:33:08 AM UTC 24 |
Oct 03 04:33:10 AM UTC 24 |
18325741 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.3323104475 |
|
|
Oct 03 04:32:59 AM UTC 24 |
Oct 03 04:33:13 AM UTC 24 |
771944789 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.3751518559 |
|
|
Oct 03 04:33:10 AM UTC 24 |
Oct 03 04:33:13 AM UTC 24 |
38186462 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2220932815 |
|
|
Oct 03 04:33:11 AM UTC 24 |
Oct 03 04:33:13 AM UTC 24 |
50505573 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2148471078 |
|
|
Oct 03 04:32:29 AM UTC 24 |
Oct 03 04:33:14 AM UTC 24 |
3843095388 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1460611504 |
|
|
Oct 03 04:33:09 AM UTC 24 |
Oct 03 04:33:14 AM UTC 24 |
614182039 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.626812353 |
|
|
Oct 03 04:23:06 AM UTC 24 |
Oct 03 04:33:14 AM UTC 24 |
872713700371 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4025266271 |
|
|
Oct 03 04:32:54 AM UTC 24 |
Oct 03 04:33:15 AM UTC 24 |
10499028788 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3913359700 |
|
|
Oct 03 04:33:14 AM UTC 24 |
Oct 03 04:33:18 AM UTC 24 |
467356200 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.3482017593 |
|
|
Oct 03 04:32:56 AM UTC 24 |
Oct 03 04:33:18 AM UTC 24 |
2112642026 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.3453464592 |
|
|
Oct 03 04:33:11 AM UTC 24 |
Oct 03 04:33:18 AM UTC 24 |
547150154 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1790219051 |
|
|
Oct 03 04:32:38 AM UTC 24 |
Oct 03 04:33:19 AM UTC 24 |
2686756702 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.91920150 |
|
|
Oct 03 04:33:14 AM UTC 24 |
Oct 03 04:33:19 AM UTC 24 |
121307955 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.752890150 |
|
|
Oct 03 04:33:16 AM UTC 24 |
Oct 03 04:33:20 AM UTC 24 |
159410465 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.2987936161 |
|
|
Oct 03 04:30:55 AM UTC 24 |
Oct 03 04:33:21 AM UTC 24 |
42330750469 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1767352859 |
|
|
Oct 03 04:32:42 AM UTC 24 |
Oct 03 04:33:22 AM UTC 24 |
14023756807 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.3429532129 |
|
|
Oct 03 04:33:21 AM UTC 24 |
Oct 03 04:33:24 AM UTC 24 |
144150449 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.1274330790 |
|
|
Oct 03 04:33:22 AM UTC 24 |
Oct 03 04:33:24 AM UTC 24 |
13543129 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2916452325 |
|
|
Oct 03 04:33:22 AM UTC 24 |
Oct 03 04:33:24 AM UTC 24 |
60654554 ps |