| T836 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.470588964 |
|
|
Oct 03 04:33:00 AM UTC 24 |
Oct 03 04:33:24 AM UTC 24 |
4532751119 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.3900025269 |
|
|
Oct 03 04:33:16 AM UTC 24 |
Oct 03 04:33:25 AM UTC 24 |
238667406 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.2310713123 |
|
|
Oct 03 04:33:14 AM UTC 24 |
Oct 03 04:33:26 AM UTC 24 |
829149689 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.2451816541 |
|
|
Oct 03 04:33:16 AM UTC 24 |
Oct 03 04:33:27 AM UTC 24 |
2481646999 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.2142374409 |
|
|
Oct 03 04:33:26 AM UTC 24 |
Oct 03 04:33:28 AM UTC 24 |
27004185 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.18129420 |
|
|
Oct 03 04:33:23 AM UTC 24 |
Oct 03 04:33:29 AM UTC 24 |
2861917597 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2661162900 |
|
|
Oct 03 04:33:31 AM UTC 24 |
Oct 03 04:33:44 AM UTC 24 |
207004586 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3761560832 |
|
|
Oct 03 04:33:19 AM UTC 24 |
Oct 03 04:33:29 AM UTC 24 |
1071592745 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.2415669090 |
|
|
Oct 03 04:33:26 AM UTC 24 |
Oct 03 04:33:29 AM UTC 24 |
265350149 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1037322059 |
|
|
Oct 03 04:29:43 AM UTC 24 |
Oct 03 04:33:34 AM UTC 24 |
25712318999 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.922440054 |
|
|
Oct 03 04:33:27 AM UTC 24 |
Oct 03 04:33:35 AM UTC 24 |
606732571 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.1674911920 |
|
|
Oct 03 04:33:29 AM UTC 24 |
Oct 03 04:33:36 AM UTC 24 |
833487048 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.982497111 |
|
|
Oct 03 04:32:53 AM UTC 24 |
Oct 03 04:33:37 AM UTC 24 |
16625902075 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.359108399 |
|
|
Oct 03 04:33:31 AM UTC 24 |
Oct 03 04:33:40 AM UTC 24 |
367018290 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3564219046 |
|
|
Oct 03 04:33:10 AM UTC 24 |
Oct 03 04:33:40 AM UTC 24 |
12558905524 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2431712723 |
|
|
Oct 03 04:33:02 AM UTC 24 |
Oct 03 04:33:40 AM UTC 24 |
2072463704 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.969986404 |
|
|
Oct 03 04:33:28 AM UTC 24 |
Oct 03 04:33:41 AM UTC 24 |
1983010235 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3332575631 |
|
|
Oct 03 04:33:35 AM UTC 24 |
Oct 03 04:33:41 AM UTC 24 |
63684842 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.99627874 |
|
|
Oct 03 04:33:26 AM UTC 24 |
Oct 03 04:33:42 AM UTC 24 |
4752855475 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.1332424845 |
|
|
Oct 03 04:33:41 AM UTC 24 |
Oct 03 04:33:43 AM UTC 24 |
14908822 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1145001687 |
|
|
Oct 03 04:33:26 AM UTC 24 |
Oct 03 04:33:43 AM UTC 24 |
8028258373 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.1773251672 |
|
|
Oct 03 04:33:41 AM UTC 24 |
Oct 03 04:33:43 AM UTC 24 |
207355442 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2033591341 |
|
|
Oct 03 04:32:07 AM UTC 24 |
Oct 03 04:33:46 AM UTC 24 |
151220600096 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.2714641121 |
|
|
Oct 03 04:33:44 AM UTC 24 |
Oct 03 04:33:47 AM UTC 24 |
115872342 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2075080640 |
|
|
Oct 03 04:33:44 AM UTC 24 |
Oct 03 04:33:49 AM UTC 24 |
104260045 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.3063630037 |
|
|
Oct 03 04:33:44 AM UTC 24 |
Oct 03 04:33:50 AM UTC 24 |
131280993 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2460098617 |
|
|
Oct 03 04:32:49 AM UTC 24 |
Oct 03 04:33:52 AM UTC 24 |
13489320857 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1130684816 |
|
|
Oct 03 04:32:11 AM UTC 24 |
Oct 03 04:33:52 AM UTC 24 |
9742199916 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1138791495 |
|
|
Oct 03 04:33:42 AM UTC 24 |
Oct 03 04:33:52 AM UTC 24 |
607564687 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.1076870992 |
|
|
Oct 03 04:33:48 AM UTC 24 |
Oct 03 04:33:52 AM UTC 24 |
350618765 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1235518685 |
|
|
Oct 03 04:33:50 AM UTC 24 |
Oct 03 04:33:54 AM UTC 24 |
46429699 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.907565854 |
|
|
Oct 03 04:33:46 AM UTC 24 |
Oct 03 04:33:55 AM UTC 24 |
1568598264 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3347818137 |
|
|
Oct 03 04:32:48 AM UTC 24 |
Oct 03 04:33:55 AM UTC 24 |
5053463202 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3118568148 |
|
|
Oct 03 04:33:44 AM UTC 24 |
Oct 03 04:33:56 AM UTC 24 |
2410570050 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.890796569 |
|
|
Oct 03 04:33:54 AM UTC 24 |
Oct 03 04:33:56 AM UTC 24 |
20756433 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1451951477 |
|
|
Oct 03 04:32:31 AM UTC 24 |
Oct 03 04:33:56 AM UTC 24 |
6445484117 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.3186769040 |
|
|
Oct 03 04:33:45 AM UTC 24 |
Oct 03 04:33:58 AM UTC 24 |
1085938111 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.844117214 |
|
|
Oct 03 04:33:56 AM UTC 24 |
Oct 03 04:33:58 AM UTC 24 |
15864055 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.586048185 |
|
|
Oct 03 04:29:59 AM UTC 24 |
Oct 03 04:33:59 AM UTC 24 |
26191105375 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.1413067716 |
|
|
Oct 03 04:33:58 AM UTC 24 |
Oct 03 04:34:00 AM UTC 24 |
15547892 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3267503641 |
|
|
Oct 03 04:33:42 AM UTC 24 |
Oct 03 04:34:01 AM UTC 24 |
2472380061 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.353137971 |
|
|
Oct 03 04:33:59 AM UTC 24 |
Oct 03 04:34:01 AM UTC 24 |
113097594 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3895300999 |
|
|
Oct 03 04:33:59 AM UTC 24 |
Oct 03 04:34:02 AM UTC 24 |
59018344 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3508211183 |
|
|
Oct 03 04:31:59 AM UTC 24 |
Oct 03 04:34:04 AM UTC 24 |
32893082600 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.779238551 |
|
|
Oct 03 04:33:59 AM UTC 24 |
Oct 03 04:34:04 AM UTC 24 |
60615891 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.1044199820 |
|
|
Oct 03 04:25:39 AM UTC 24 |
Oct 03 04:34:07 AM UTC 24 |
206601618293 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.3010505480 |
|
|
Oct 03 04:33:54 AM UTC 24 |
Oct 03 04:34:07 AM UTC 24 |
3848353482 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.923618171 |
|
|
Oct 03 04:33:24 AM UTC 24 |
Oct 03 04:34:07 AM UTC 24 |
19160382166 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.2726213408 |
|
|
Oct 03 04:34:05 AM UTC 24 |
Oct 03 04:34:08 AM UTC 24 |
72542971 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.131267946 |
|
|
Oct 03 04:34:03 AM UTC 24 |
Oct 03 04:34:10 AM UTC 24 |
402875017 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1522629214 |
|
|
Oct 03 04:31:10 AM UTC 24 |
Oct 03 04:34:12 AM UTC 24 |
49784913192 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.306523137 |
|
|
Oct 03 04:34:02 AM UTC 24 |
Oct 03 04:34:12 AM UTC 24 |
634289316 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.3541464590 |
|
|
Oct 03 04:34:11 AM UTC 24 |
Oct 03 04:34:13 AM UTC 24 |
49559894 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3456373794 |
|
|
Oct 03 04:32:14 AM UTC 24 |
Oct 03 04:34:13 AM UTC 24 |
15413263986 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.570209787 |
|
|
Oct 03 04:34:01 AM UTC 24 |
Oct 03 04:34:13 AM UTC 24 |
961107526 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.1954703897 |
|
|
Oct 03 04:33:04 AM UTC 24 |
Oct 03 04:34:14 AM UTC 24 |
9426905162 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1999570793 |
|
|
Oct 03 04:33:58 AM UTC 24 |
Oct 03 04:34:15 AM UTC 24 |
1333718677 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.3056930526 |
|
|
Oct 03 04:34:13 AM UTC 24 |
Oct 03 04:34:15 AM UTC 24 |
56362463 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3486136892 |
|
|
Oct 03 04:34:14 AM UTC 24 |
Oct 03 04:34:17 AM UTC 24 |
56401242 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.801656288 |
|
|
Oct 03 04:34:14 AM UTC 24 |
Oct 03 04:34:17 AM UTC 24 |
68377717 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.2837652129 |
|
|
Oct 03 04:32:48 AM UTC 24 |
Oct 03 04:34:17 AM UTC 24 |
5011187335 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1631932599 |
|
|
Oct 03 04:33:58 AM UTC 24 |
Oct 03 04:34:17 AM UTC 24 |
4263608405 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.106260643 |
|
|
Oct 03 04:34:13 AM UTC 24 |
Oct 03 04:34:19 AM UTC 24 |
883642939 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2102666073 |
|
|
Oct 03 04:34:16 AM UTC 24 |
Oct 03 04:34:20 AM UTC 24 |
33112579 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3700951360 |
|
|
Oct 03 04:34:05 AM UTC 24 |
Oct 03 04:34:20 AM UTC 24 |
3401034712 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3184655900 |
|
|
Oct 03 04:33:51 AM UTC 24 |
Oct 03 04:34:20 AM UTC 24 |
2150377086 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2287351329 |
|
|
Oct 03 04:34:19 AM UTC 24 |
Oct 03 04:34:23 AM UTC 24 |
32565955 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1478467624 |
|
|
Oct 03 04:34:16 AM UTC 24 |
Oct 03 04:34:23 AM UTC 24 |
146250169 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.1367668040 |
|
|
Oct 03 04:34:21 AM UTC 24 |
Oct 03 04:34:23 AM UTC 24 |
34234103 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.728172367 |
|
|
Oct 03 04:34:19 AM UTC 24 |
Oct 03 04:34:24 AM UTC 24 |
2774854756 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2318996471 |
|
|
Oct 03 04:34:16 AM UTC 24 |
Oct 03 04:34:26 AM UTC 24 |
418952649 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.4189863011 |
|
|
Oct 03 04:34:01 AM UTC 24 |
Oct 03 04:34:26 AM UTC 24 |
81404721778 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.4018820359 |
|
|
Oct 03 04:34:17 AM UTC 24 |
Oct 03 04:34:27 AM UTC 24 |
856343723 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.1158453202 |
|
|
Oct 03 04:34:25 AM UTC 24 |
Oct 03 04:34:27 AM UTC 24 |
28646918 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.2751625503 |
|
|
Oct 03 04:34:26 AM UTC 24 |
Oct 03 04:34:28 AM UTC 24 |
74062582 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.259532351 |
|
|
Oct 03 04:34:27 AM UTC 24 |
Oct 03 04:34:30 AM UTC 24 |
36242438 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2150680134 |
|
|
Oct 03 04:34:28 AM UTC 24 |
Oct 03 04:34:30 AM UTC 24 |
26299146 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.2151782340 |
|
|
Oct 03 04:33:41 AM UTC 24 |
Oct 03 04:34:31 AM UTC 24 |
9464288340 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.2948473542 |
|
|
Oct 03 04:34:29 AM UTC 24 |
Oct 03 04:34:32 AM UTC 24 |
119189778 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3804214831 |
|
|
Oct 03 04:34:21 AM UTC 24 |
Oct 03 04:34:32 AM UTC 24 |
751972558 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.3239616008 |
|
|
Oct 03 04:32:03 AM UTC 24 |
Oct 03 04:34:33 AM UTC 24 |
8710977826 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2573209989 |
|
|
Oct 03 04:33:16 AM UTC 24 |
Oct 03 04:34:37 AM UTC 24 |
6154311122 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3213548373 |
|
|
Oct 03 04:34:32 AM UTC 24 |
Oct 03 04:34:37 AM UTC 24 |
391279624 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.802195512 |
|
|
Oct 03 04:34:33 AM UTC 24 |
Oct 03 04:34:38 AM UTC 24 |
171547625 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1166803072 |
|
|
Oct 03 04:34:30 AM UTC 24 |
Oct 03 04:34:38 AM UTC 24 |
264532648 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.893206329 |
|
|
Oct 03 04:34:34 AM UTC 24 |
Oct 03 04:34:42 AM UTC 24 |
300530067 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.3930199998 |
|
|
Oct 03 04:30:52 AM UTC 24 |
Oct 03 04:34:45 AM UTC 24 |
97254205501 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1587247369 |
|
|
Oct 03 04:34:39 AM UTC 24 |
Oct 03 04:34:45 AM UTC 24 |
279081244 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2167576628 |
|
|
Oct 03 04:34:33 AM UTC 24 |
Oct 03 04:34:45 AM UTC 24 |
2293294342 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.2707957792 |
|
|
Oct 03 04:34:27 AM UTC 24 |
Oct 03 04:34:45 AM UTC 24 |
2793959066 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2020140863 |
|
|
Oct 03 04:30:22 AM UTC 24 |
Oct 03 04:34:47 AM UTC 24 |
28287061686 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.1063955430 |
|
|
Oct 03 04:34:45 AM UTC 24 |
Oct 03 04:34:48 AM UTC 24 |
14330613 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.2128216251 |
|
|
Oct 03 04:34:14 AM UTC 24 |
Oct 03 04:34:48 AM UTC 24 |
4524812026 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3112030951 |
|
|
Oct 03 04:33:19 AM UTC 24 |
Oct 03 04:34:48 AM UTC 24 |
3956515833 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.221788645 |
|
|
Oct 03 04:33:54 AM UTC 24 |
Oct 03 04:34:49 AM UTC 24 |
17819615896 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.1260716672 |
|
|
Oct 03 04:34:47 AM UTC 24 |
Oct 03 04:34:49 AM UTC 24 |
22619225 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1044267483 |
|
|
Oct 03 04:34:48 AM UTC 24 |
Oct 03 04:34:51 AM UTC 24 |
43275404 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.980423985 |
|
|
Oct 03 04:34:50 AM UTC 24 |
Oct 03 04:34:52 AM UTC 24 |
12119059 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.1731722710 |
|
|
Oct 03 04:34:50 AM UTC 24 |
Oct 03 04:34:54 AM UTC 24 |
50608577 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.2306628723 |
|
|
Oct 03 04:34:19 AM UTC 24 |
Oct 03 04:34:54 AM UTC 24 |
7089278750 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.4087780121 |
|
|
Oct 03 04:34:21 AM UTC 24 |
Oct 03 04:34:55 AM UTC 24 |
6821856657 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.342486401 |
|
|
Oct 03 04:34:43 AM UTC 24 |
Oct 03 04:34:56 AM UTC 24 |
3327510641 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.1391139000 |
|
|
Oct 03 04:34:07 AM UTC 24 |
Oct 03 04:34:57 AM UTC 24 |
11565326192 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.1410074748 |
|
|
Oct 03 04:34:55 AM UTC 24 |
Oct 03 04:35:00 AM UTC 24 |
258808351 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.826080033 |
|
|
Oct 03 04:34:53 AM UTC 24 |
Oct 03 04:35:02 AM UTC 24 |
553685153 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.316953077 |
|
|
Oct 03 04:34:39 AM UTC 24 |
Oct 03 04:35:02 AM UTC 24 |
1779298073 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.843502039 |
|
|
Oct 03 04:34:57 AM UTC 24 |
Oct 03 04:35:04 AM UTC 24 |
166989678 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.4184072634 |
|
|
Oct 03 04:34:48 AM UTC 24 |
Oct 03 04:35:05 AM UTC 24 |
2459629447 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.4035298512 |
|
|
Oct 03 04:34:50 AM UTC 24 |
Oct 03 04:35:06 AM UTC 24 |
440932593 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.2042268473 |
|
|
Oct 03 04:34:09 AM UTC 24 |
Oct 03 04:35:06 AM UTC 24 |
26275253491 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.1753682982 |
|
|
Oct 03 04:35:05 AM UTC 24 |
Oct 03 04:35:07 AM UTC 24 |
30357096 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.2326129162 |
|
|
Oct 03 04:35:06 AM UTC 24 |
Oct 03 04:35:08 AM UTC 24 |
28566805 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3951786514 |
|
|
Oct 03 04:34:47 AM UTC 24 |
Oct 03 04:35:10 AM UTC 24 |
22086768070 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1202614317 |
|
|
Oct 03 04:35:07 AM UTC 24 |
Oct 03 04:35:10 AM UTC 24 |
2813284106 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.584859955 |
|
|
Oct 03 04:35:08 AM UTC 24 |
Oct 03 04:35:11 AM UTC 24 |
212802910 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.4011647472 |
|
|
Oct 03 04:34:02 AM UTC 24 |
Oct 03 04:35:11 AM UTC 24 |
5579985864 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1057912600 |
|
|
Oct 03 04:33:56 AM UTC 24 |
Oct 03 04:35:11 AM UTC 24 |
8610184648 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.584944289 |
|
|
Oct 03 04:35:09 AM UTC 24 |
Oct 03 04:35:12 AM UTC 24 |
126728683 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3455198957 |
|
|
Oct 03 04:34:50 AM UTC 24 |
Oct 03 04:35:13 AM UTC 24 |
8783428216 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.2505051519 |
|
|
Oct 03 04:34:32 AM UTC 24 |
Oct 03 04:35:14 AM UTC 24 |
6617847245 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.188313329 |
|
|
Oct 03 04:33:31 AM UTC 24 |
Oct 03 04:35:17 AM UTC 24 |
29954104136 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2400422998 |
|
|
Oct 03 04:35:16 AM UTC 24 |
Oct 03 04:35:18 AM UTC 24 |
67338971 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.3531158888 |
|
|
Oct 03 04:35:13 AM UTC 24 |
Oct 03 04:35:18 AM UTC 24 |
56386981 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.515466334 |
|
|
Oct 03 04:35:11 AM UTC 24 |
Oct 03 04:35:19 AM UTC 24 |
2894073956 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.4149434778 |
|
|
Oct 03 04:23:46 AM UTC 24 |
Oct 03 04:35:21 AM UTC 24 |
145989252409 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2744103461 |
|
|
Oct 03 04:34:52 AM UTC 24 |
Oct 03 04:35:21 AM UTC 24 |
9386962251 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.588902711 |
|
|
Oct 03 04:33:19 AM UTC 24 |
Oct 03 04:35:22 AM UTC 24 |
4471410340 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3694766216 |
|
|
Oct 03 04:35:13 AM UTC 24 |
Oct 03 04:35:23 AM UTC 24 |
240470292 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3009203564 |
|
|
Oct 03 04:29:28 AM UTC 24 |
Oct 03 04:35:23 AM UTC 24 |
116581968447 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.1388387443 |
|
|
Oct 03 04:35:22 AM UTC 24 |
Oct 03 04:35:24 AM UTC 24 |
36539297 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.679995319 |
|
|
Oct 03 04:35:18 AM UTC 24 |
Oct 03 04:35:24 AM UTC 24 |
72404603 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.4193512108 |
|
|
Oct 03 04:34:07 AM UTC 24 |
Oct 03 04:35:24 AM UTC 24 |
40851676767 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.104709333 |
|
|
Oct 03 04:35:23 AM UTC 24 |
Oct 03 04:35:25 AM UTC 24 |
17152180 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2026157144 |
|
|
Oct 03 04:35:14 AM UTC 24 |
Oct 03 04:35:26 AM UTC 24 |
480477565 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.2886711022 |
|
|
Oct 03 04:32:34 AM UTC 24 |
Oct 03 04:35:26 AM UTC 24 |
52256281362 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.524848651 |
|
|
Oct 03 04:35:23 AM UTC 24 |
Oct 03 04:35:26 AM UTC 24 |
174652625 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.1652475334 |
|
|
Oct 03 04:35:25 AM UTC 24 |
Oct 03 04:35:27 AM UTC 24 |
28875990 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.34846183 |
|
|
Oct 03 04:35:25 AM UTC 24 |
Oct 03 04:35:27 AM UTC 24 |
109471113 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.1038347526 |
|
|
Oct 03 04:35:07 AM UTC 24 |
Oct 03 04:35:29 AM UTC 24 |
827895889 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.1934469716 |
|
|
Oct 03 04:35:25 AM UTC 24 |
Oct 03 04:35:30 AM UTC 24 |
1314747722 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2251077505 |
|
|
Oct 03 04:35:26 AM UTC 24 |
Oct 03 04:35:30 AM UTC 24 |
2011052517 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.3912956403 |
|
|
Oct 03 04:35:27 AM UTC 24 |
Oct 03 04:35:32 AM UTC 24 |
134889259 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3467413357 |
|
|
Oct 03 04:31:28 AM UTC 24 |
Oct 03 04:35:32 AM UTC 24 |
25636902757 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2191057326 |
|
|
Oct 03 04:35:12 AM UTC 24 |
Oct 03 04:35:33 AM UTC 24 |
6190934421 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.1899148334 |
|
|
Oct 03 04:35:29 AM UTC 24 |
Oct 03 04:35:33 AM UTC 24 |
35768420 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.295917628 |
|
|
Oct 03 04:35:34 AM UTC 24 |
Oct 03 04:35:36 AM UTC 24 |
14477132 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.2995540531 |
|
|
Oct 03 04:35:12 AM UTC 24 |
Oct 03 04:35:37 AM UTC 24 |
19337001544 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.1079794581 |
|
|
Oct 03 04:35:12 AM UTC 24 |
Oct 03 04:35:37 AM UTC 24 |
2016899172 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.2219210893 |
|
|
Oct 03 04:35:37 AM UTC 24 |
Oct 03 04:35:39 AM UTC 24 |
20301409 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3565788637 |
|
|
Oct 03 04:35:29 AM UTC 24 |
Oct 03 04:35:40 AM UTC 24 |
2494988827 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2078880308 |
|
|
Oct 03 04:35:38 AM UTC 24 |
Oct 03 04:35:41 AM UTC 24 |
138257116 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2213675605 |
|
|
Oct 03 04:35:41 AM UTC 24 |
Oct 03 04:35:43 AM UTC 24 |
224140611 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.3189266329 |
|
|
Oct 03 04:35:27 AM UTC 24 |
Oct 03 04:35:44 AM UTC 24 |
4736188306 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.3819895244 |
|
|
Oct 03 04:34:55 AM UTC 24 |
Oct 03 04:35:45 AM UTC 24 |
6157645397 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2748499660 |
|
|
Oct 03 04:35:30 AM UTC 24 |
Oct 03 04:35:47 AM UTC 24 |
684628757 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3284157338 |
|
|
Oct 03 04:33:52 AM UTC 24 |
Oct 03 04:35:47 AM UTC 24 |
7405992615 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.297855558 |
|
|
Oct 03 04:35:42 AM UTC 24 |
Oct 03 04:35:47 AM UTC 24 |
513953527 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1053495851 |
|
|
Oct 03 04:35:31 AM UTC 24 |
Oct 03 04:35:48 AM UTC 24 |
988684098 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.3875495213 |
|
|
Oct 03 04:35:41 AM UTC 24 |
Oct 03 04:35:53 AM UTC 24 |
239780513 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1145146119 |
|
|
Oct 03 04:35:48 AM UTC 24 |
Oct 03 04:35:53 AM UTC 24 |
100377398 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1593734590 |
|
|
Oct 03 04:35:19 AM UTC 24 |
Oct 03 04:35:53 AM UTC 24 |
1272904512 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.2957425011 |
|
|
Oct 03 04:35:47 AM UTC 24 |
Oct 03 04:35:56 AM UTC 24 |
853314993 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3250297107 |
|
|
Oct 03 04:35:48 AM UTC 24 |
Oct 03 04:35:58 AM UTC 24 |
766746301 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.882716056 |
|
|
Oct 03 04:31:27 AM UTC 24 |
Oct 03 04:36:02 AM UTC 24 |
61462017506 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.1194111817 |
|
|
Oct 03 04:35:25 AM UTC 24 |
Oct 03 04:36:03 AM UTC 24 |
6542455196 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1623796830 |
|
|
Oct 03 04:35:48 AM UTC 24 |
Oct 03 04:36:04 AM UTC 24 |
1441495219 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3922252409 |
|
|
Oct 03 04:34:07 AM UTC 24 |
Oct 03 04:36:04 AM UTC 24 |
6792971292 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.3112839284 |
|
|
Oct 03 04:35:54 AM UTC 24 |
Oct 03 04:36:04 AM UTC 24 |
2425809515 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3080593224 |
|
|
Oct 03 04:36:02 AM UTC 24 |
Oct 03 04:36:05 AM UTC 24 |
59261764 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1352126536 |
|
|
Oct 03 04:33:03 AM UTC 24 |
Oct 03 04:36:09 AM UTC 24 |
46251771418 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.2896908705 |
|
|
Oct 03 04:31:08 AM UTC 24 |
Oct 03 04:36:11 AM UTC 24 |
46823481905 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.1928869423 |
|
|
Oct 03 04:34:33 AM UTC 24 |
Oct 03 04:36:12 AM UTC 24 |
37453258822 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3721084167 |
|
|
Oct 03 04:31:28 AM UTC 24 |
Oct 03 04:36:12 AM UTC 24 |
24723202231 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.107438659 |
|
|
Oct 03 04:35:45 AM UTC 24 |
Oct 03 04:36:15 AM UTC 24 |
3498252547 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.7685571 |
|
|
Oct 03 04:35:44 AM UTC 24 |
Oct 03 04:36:16 AM UTC 24 |
8704107248 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3779768582 |
|
|
Oct 03 04:33:36 AM UTC 24 |
Oct 03 04:36:17 AM UTC 24 |
16546181233 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.1180436867 |
|
|
Oct 03 04:35:31 AM UTC 24 |
Oct 03 04:36:20 AM UTC 24 |
4111920380 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.701843086 |
|
|
Oct 03 04:32:29 AM UTC 24 |
Oct 03 04:36:21 AM UTC 24 |
77048387293 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.2641887752 |
|
|
Oct 03 04:34:58 AM UTC 24 |
Oct 03 04:36:22 AM UTC 24 |
6831781588 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2264281253 |
|
|
Oct 03 04:35:49 AM UTC 24 |
Oct 03 04:36:22 AM UTC 24 |
2340735386 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1105897795 |
|
|
Oct 03 04:24:06 AM UTC 24 |
Oct 03 04:36:23 AM UTC 24 |
1058451245114 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3260111889 |
|
|
Oct 03 04:35:27 AM UTC 24 |
Oct 03 04:36:26 AM UTC 24 |
19009487168 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.965546103 |
|
|
Oct 03 04:25:02 AM UTC 24 |
Oct 03 04:36:35 AM UTC 24 |
363986549448 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.2964975565 |
|
|
Oct 03 04:35:38 AM UTC 24 |
Oct 03 04:36:36 AM UTC 24 |
7038785987 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3784980381 |
|
|
Oct 03 04:33:39 AM UTC 24 |
Oct 03 04:36:36 AM UTC 24 |
19542826293 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2349288260 |
|
|
Oct 03 04:35:01 AM UTC 24 |
Oct 03 04:36:51 AM UTC 24 |
14019180438 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1716301156 |
|
|
Oct 03 04:35:03 AM UTC 24 |
Oct 03 04:36:53 AM UTC 24 |
9135236608 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3498823905 |
|
|
Oct 03 04:35:19 AM UTC 24 |
Oct 03 04:36:54 AM UTC 24 |
20398304775 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.1966873830 |
|
|
Oct 03 04:35:59 AM UTC 24 |
Oct 03 04:36:54 AM UTC 24 |
34948729429 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.573382627 |
|
|
Oct 03 04:34:57 AM UTC 24 |
Oct 03 04:36:55 AM UTC 24 |
43609431229 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.435258749 |
|
|
Oct 03 04:35:54 AM UTC 24 |
Oct 03 04:37:05 AM UTC 24 |
2969027633 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1746386845 |
|
|
Oct 03 04:34:25 AM UTC 24 |
Oct 03 04:37:16 AM UTC 24 |
15140341943 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.4293186140 |
|
|
Oct 03 04:31:49 AM UTC 24 |
Oct 03 04:37:16 AM UTC 24 |
336735673999 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3747005414 |
|
|
Oct 03 04:32:01 AM UTC 24 |
Oct 03 04:37:40 AM UTC 24 |
38114688346 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.1654641560 |
|
|
Oct 03 04:31:50 AM UTC 24 |
Oct 03 04:37:43 AM UTC 24 |
170595845986 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.1715700914 |
|
|
Oct 03 04:35:03 AM UTC 24 |
Oct 03 04:37:54 AM UTC 24 |
96060761170 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.732982054 |
|
|
Oct 03 04:29:44 AM UTC 24 |
Oct 03 04:37:58 AM UTC 24 |
43545634995 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2857539808 |
|
|
Oct 03 04:34:20 AM UTC 24 |
Oct 03 04:38:10 AM UTC 24 |
99381722250 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.2754337564 |
|
|
Oct 03 04:33:19 AM UTC 24 |
Oct 03 04:38:16 AM UTC 24 |
67488751560 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2317284434 |
|
|
Oct 03 04:33:56 AM UTC 24 |
Oct 03 04:38:25 AM UTC 24 |
29867612230 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.888770502 |
|
|
Oct 03 04:29:17 AM UTC 24 |
Oct 03 04:38:32 AM UTC 24 |
95395869481 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1123240007 |
|
|
Oct 03 04:35:57 AM UTC 24 |
Oct 03 04:38:39 AM UTC 24 |
195671553405 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.4004338636 |
|
|
Oct 03 04:22:44 AM UTC 24 |
Oct 03 04:38:42 AM UTC 24 |
84322330225 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.2857094434 |
|
|
Oct 03 04:32:13 AM UTC 24 |
Oct 03 04:39:04 AM UTC 24 |
60685995412 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1300522483 |
|
|
Oct 03 04:35:34 AM UTC 24 |
Oct 03 04:39:07 AM UTC 24 |
61478918853 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.1262985897 |
|
|
Oct 03 04:32:45 AM UTC 24 |
Oct 03 04:39:13 AM UTC 24 |
41652594616 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2481805813 |
|
|
Oct 03 04:34:05 AM UTC 24 |
Oct 03 04:39:33 AM UTC 24 |
629190808267 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.4097940914 |
|
|
Oct 03 04:30:22 AM UTC 24 |
Oct 03 04:39:48 AM UTC 24 |
75382976755 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.2439500651 |
|
|
Oct 03 04:30:04 AM UTC 24 |
Oct 03 04:40:12 AM UTC 24 |
111977041878 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3216005525 |
|
|
Oct 03 04:32:49 AM UTC 24 |
Oct 03 04:40:16 AM UTC 24 |
214459435302 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3072236847 |
|
|
Oct 03 04:34:23 AM UTC 24 |
Oct 03 04:40:18 AM UTC 24 |
172210950194 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3521557393 |
|
|
Oct 03 04:33:37 AM UTC 24 |
Oct 03 04:40:24 AM UTC 24 |
526277508453 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1826935015 |
|
|
Oct 03 04:32:14 AM UTC 24 |
Oct 03 04:40:41 AM UTC 24 |
77488479259 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1305560669 |
|
|
Oct 03 04:35:20 AM UTC 24 |
Oct 03 04:41:02 AM UTC 24 |
27268067465 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.1055439126 |
|
|
Oct 03 04:35:32 AM UTC 24 |
Oct 03 04:41:19 AM UTC 24 |
120962792769 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.473346539 |
|
|
Oct 03 04:22:47 AM UTC 24 |
Oct 03 04:41:32 AM UTC 24 |
1868855168727 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1746161502 |
|
|
Oct 03 04:34:45 AM UTC 24 |
Oct 03 04:41:58 AM UTC 24 |
33678944002 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1124260193 |
|
|
Oct 03 04:35:34 AM UTC 24 |
Oct 03 04:42:04 AM UTC 24 |
53689017363 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1388245317 |
|
|
Oct 03 04:25:20 AM UTC 24 |
Oct 03 04:43:07 AM UTC 24 |
100424605803 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1764697133 |
|
|
Oct 03 04:34:37 AM UTC 24 |
Oct 03 04:43:32 AM UTC 24 |
257577217092 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2448893769 |
|
|
Oct 03 04:35:55 AM UTC 24 |
Oct 03 04:43:46 AM UTC 24 |
176250343926 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.73327436 |
|
|
Oct 03 04:35:22 AM UTC 24 |
Oct 03 04:43:48 AM UTC 24 |
141250835306 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.2737924825 |
|
|
Oct 03 04:30:55 AM UTC 24 |
Oct 03 04:45:52 AM UTC 24 |
131948160525 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2606354182 |
|
|
Oct 03 04:33:04 AM UTC 24 |
Oct 03 04:47:27 AM UTC 24 |
245291507483 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.608651584 |
|
|
Oct 03 04:34:40 AM UTC 24 |
Oct 03 04:51:53 AM UTC 24 |
194245291002 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3665747216 |
|
|
Oct 03 01:07:16 AM UTC 24 |
Oct 03 01:07:18 AM UTC 24 |
34297229 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2217895351 |
|
|
Oct 03 01:07:16 AM UTC 24 |
Oct 03 01:07:18 AM UTC 24 |
44062487 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2613455923 |
|
|
Oct 03 01:07:14 AM UTC 24 |
Oct 03 01:07:18 AM UTC 24 |
60242088 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.111192541 |
|
|
Oct 03 01:07:17 AM UTC 24 |
Oct 03 01:07:20 AM UTC 24 |
41869895 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.4273422342 |
|
|
Oct 03 01:07:16 AM UTC 24 |
Oct 03 01:07:21 AM UTC 24 |
204322395 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3750284724 |
|
|
Oct 03 01:07:18 AM UTC 24 |
Oct 03 01:07:23 AM UTC 24 |
107116999 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.147276830 |
|
|
Oct 03 01:07:19 AM UTC 24 |
Oct 03 01:07:23 AM UTC 24 |
177108915 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4175537862 |
|
|
Oct 03 01:07:21 AM UTC 24 |
Oct 03 01:07:26 AM UTC 24 |
42567000 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1349959181 |
|
|
Oct 03 01:07:24 AM UTC 24 |
Oct 03 01:07:26 AM UTC 24 |
41503019 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1792993714 |
|
|
Oct 03 01:07:24 AM UTC 24 |
Oct 03 01:07:26 AM UTC 24 |
12738237 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.298085633 |
|
|
Oct 03 01:07:22 AM UTC 24 |
Oct 03 01:07:27 AM UTC 24 |
367530947 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4190370603 |
|
|
Oct 03 01:07:24 AM UTC 24 |
Oct 03 01:07:28 AM UTC 24 |
178456829 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2694521772 |
|
|
Oct 03 01:07:26 AM UTC 24 |
Oct 03 01:07:29 AM UTC 24 |
187713430 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2633943538 |
|
|
Oct 03 01:07:22 AM UTC 24 |
Oct 03 01:07:31 AM UTC 24 |
2088728494 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1705945144 |
|
|
Oct 03 01:07:27 AM UTC 24 |
Oct 03 01:07:31 AM UTC 24 |
217944833 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.699537000 |
|
|
Oct 03 01:07:14 AM UTC 24 |
Oct 03 01:07:32 AM UTC 24 |
411364436 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2335542876 |
|
|
Oct 03 01:07:30 AM UTC 24 |
Oct 03 01:07:34 AM UTC 24 |
162871407 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2555138505 |
|
|
Oct 03 01:07:30 AM UTC 24 |
Oct 03 01:07:34 AM UTC 24 |
67621648 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.4122405993 |
|
|
Oct 03 01:07:32 AM UTC 24 |
Oct 03 01:07:34 AM UTC 24 |
118689711 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.3278712833 |
|
|
Oct 03 01:07:33 AM UTC 24 |
Oct 03 01:07:35 AM UTC 24 |
15903944 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3336332051 |
|
|
Oct 03 01:07:56 AM UTC 24 |
Oct 03 01:08:08 AM UTC 24 |
287928725 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.742782780 |
|
|
Oct 03 01:07:33 AM UTC 24 |
Oct 03 01:07:36 AM UTC 24 |
93870920 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3024999645 |
|
|
Oct 03 01:07:34 AM UTC 24 |
Oct 03 01:07:37 AM UTC 24 |
395873984 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3368449700 |
|
|
Oct 03 01:07:34 AM UTC 24 |
Oct 03 01:07:37 AM UTC 24 |
35879811 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2575538194 |
|
|
Oct 03 01:07:31 AM UTC 24 |
Oct 03 01:07:40 AM UTC 24 |
402730653 ps |