SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_scanmode_sync | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 976 | 976 | 0 | 0 |
OutputsKnown_A | 417740699 | 417650903 | 0 | 0 |
gen_no_flops.OutputDelay_A | 417740699 | 417650903 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 976 | 976 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 417740699 | 417650903 | 0 | 0 |
T1 | 1548 | 1484 | 0 | 0 |
T2 | 999 | 912 | 0 | 0 |
T3 | 1783 | 1683 | 0 | 0 |
T4 | 1281 | 1224 | 0 | 0 |
T5 | 1069 | 999 | 0 | 0 |
T6 | 69410 | 69310 | 0 | 0 |
T7 | 96749 | 96678 | 0 | 0 |
T8 | 13829 | 13734 | 0 | 0 |
T9 | 53869 | 53784 | 0 | 0 |
T10 | 440049 | 439974 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 417740699 | 417650903 | 0 | 0 |
T1 | 1548 | 1484 | 0 | 0 |
T2 | 999 | 912 | 0 | 0 |
T3 | 1783 | 1683 | 0 | 0 |
T4 | 1281 | 1224 | 0 | 0 |
T5 | 1069 | 999 | 0 | 0 |
T6 | 69410 | 69310 | 0 | 0 |
T7 | 96749 | 96678 | 0 | 0 |
T8 | 13829 | 13734 | 0 | 0 |
T9 | 53869 | 53784 | 0 | 0 |
T10 | 440049 | 439974 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |