Assert Coverage for Module : 
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
976 | 
976 | 
0 | 
0 | 
| T1 | 
1 | 
1 | 
0 | 
0 | 
| T2 | 
1 | 
1 | 
0 | 
0 | 
| T3 | 
1 | 
1 | 
0 | 
0 | 
| T4 | 
1 | 
1 | 
0 | 
0 | 
| T5 | 
1 | 
1 | 
0 | 
0 | 
| T6 | 
1 | 
1 | 
0 | 
0 | 
| T7 | 
1 | 
1 | 
0 | 
0 | 
| T8 | 
1 | 
1 | 
0 | 
0 | 
| T9 | 
1 | 
1 | 
0 | 
0 | 
| T10 | 
1 | 
1 | 
0 | 
0 | 
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
417740699 | 
417650903 | 
0 | 
0 | 
| T1 | 
1548 | 
1484 | 
0 | 
0 | 
| T2 | 
999 | 
912 | 
0 | 
0 | 
| T3 | 
1783 | 
1683 | 
0 | 
0 | 
| T4 | 
1281 | 
1224 | 
0 | 
0 | 
| T5 | 
1069 | 
999 | 
0 | 
0 | 
| T6 | 
69410 | 
69310 | 
0 | 
0 | 
| T7 | 
96749 | 
96678 | 
0 | 
0 | 
| T8 | 
13829 | 
13734 | 
0 | 
0 | 
| T9 | 
53869 | 
53784 | 
0 | 
0 | 
| T10 | 
440049 | 
439974 | 
0 | 
0 | 
gen_no_flops.OutputDelay_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
417740699 | 
417650903 | 
0 | 
0 | 
| T1 | 
1548 | 
1484 | 
0 | 
0 | 
| T2 | 
999 | 
912 | 
0 | 
0 | 
| T3 | 
1783 | 
1683 | 
0 | 
0 | 
| T4 | 
1281 | 
1224 | 
0 | 
0 | 
| T5 | 
1069 | 
999 | 
0 | 
0 | 
| T6 | 
69410 | 
69310 | 
0 | 
0 | 
| T7 | 
96749 | 
96678 | 
0 | 
0 | 
| T8 | 
13829 | 
13734 | 
0 | 
0 | 
| T9 | 
53869 | 
53784 | 
0 | 
0 | 
| T10 | 
440049 | 
439974 | 
0 | 
0 |