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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
spi_device_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00
 u_clk_csb_buf 100.00 100.00
 u_clk_csb_mux 64.81 100.00 44.44 50.00
 u_clk_spi 85.19 100.00 55.56 100.00
 u_clk_spi_in_buf 100.00 100.00
 u_clk_spi_in_mux 64.81 100.00 44.44 50.00
 u_clk_spi_out_buf 100.00 100.00
 u_clk_spi_out_mux 64.81 100.00 44.44 50.00
u_cmdparse 98.26 100.00 95.40 100.00 95.92 100.00
 u_csb_buf 100.00 100.00
 u_csb_rst_out_scan_mux 64.81 100.00 44.44 50.00
 u_csb_rst_scan_mux 64.81 100.00 44.44 50.00
 u_flash_readbuf_flip_pulse_sync 100.00 100.00 100.00 100.00 100.00
 u_flash_readbuf_watermark_pulse_sync 100.00 100.00 100.00 100.00 100.00
u_intr_cmdfifo_not_empty 100.00 100.00 100.00 100.00 100.00
u_intr_payload_not_empty 100.00 100.00 100.00 100.00 100.00
u_intr_payload_overflow 100.00 100.00 100.00 100.00 100.00
u_intr_readbuf_flip 100.00 100.00 100.00 100.00 100.00
u_intr_readbuf_watermark 100.00 100.00 100.00 100.00 100.00
u_intr_tpm_cmdaddr_notempty 100.00 100.00 100.00 100.00 100.00
u_intr_tpm_rdfifo_cmd_end 100.00 100.00 100.00 100.00 100.00
u_intr_tpm_rdfifo_drop 97.92 100.00 91.67 100.00 100.00
u_intr_upload_edge 100.00 100.00 100.00
u_jedec 100.00 100.00 100.00 100.00 100.00 100.00
u_p2s 85.98 100.00 71.43 72.50 100.00
 u_passthrough 91.08 94.95 91.92 75.00 93.52 100.00
 u_read_en_pipe_stg1 100.00 100.00 100.00
 u_read_en_pipe_stg2 100.00 100.00 100.00
 u_read_intercept_pipe_stg1 100.00 100.00 100.00
 u_read_intercept_pipe_stg2 100.00 100.00 100.00
 u_read_pipe_stg1 100.00 100.00 100.00
 u_read_pipe_stg2 100.00 100.00 100.00
 u_readcmd 90.33 93.62 93.33 87.50 85.56 91.67
 u_reg 99.90 99.61 99.88 100.00 100.00 100.00
 u_rst_spi_out_sync 100.00 100.00 100.00
u_s2p 89.38 100.00 78.57 78.95 100.00
u_scanmode_sync 100.00 100.00
 u_spi_tpm 94.15 99.28 90.60 91.67 96.73 92.45
 u_spid_addr_4b 91.90 97.59 100.00 95.00 75.00
 u_spid_csb_sync 100.00 100.00 100.00 100.00
 u_spid_dpram 100.00 100.00 100.00 100.00 100.00
 u_spid_status 92.95 100.00 88.46 100.00 83.33
 u_sys_csb_syncd 100.00 100.00 100.00
 u_sys_sram_arbiter 96.59 100.00 100.00 100.00 86.36
 u_sys_tpm_csb_sync 100.00 100.00 100.00
 u_tlul2sram_egress 84.73 86.70 82.99 86.36 82.86
 u_tlul2sram_ingress 93.79 90.79 88.16 96.20 100.00
 u_tpm_csb_buf 100.00 100.00
 u_tpm_csb_rst_scan_mux 64.81 100.00 44.44 50.00
 u_tpm_csb_rst_sync 70.83 88.89 44.44 100.00 50.00
 u_tpm_rst_out_scan_mux 64.81 100.00 44.44 50.00
 u_tpm_rst_out_sync 100.00 100.00 100.00
 u_upload 92.79 99.29 79.37 100.00 95.81 89.47