Line Coverage for Module :
spid_status
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 65 | 65 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
| ALWAYS | 166 | 6 | 6 | 100.00 |
| ALWAYS | 177 | 8 | 8 | 100.00 |
| ALWAYS | 190 | 4 | 4 | 100.00 |
| ALWAYS | 202 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 226 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
| ALWAYS | 264 | 3 | 3 | 100.00 |
| ALWAYS | 309 | 4 | 4 | 100.00 |
| ALWAYS | 322 | 5 | 5 | 100.00 |
| ALWAYS | 336 | 3 | 3 | 100.00 |
| ALWAYS | 344 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| ALWAYS | 365 | 3 | 3 | 100.00 |
| ALWAYS | 370 | 9 | 9 | 100.00 |
94 logic unused_cmd_info;
95 1/1 assign unused_cmd_info = ^cmd_info_i;
Tests: T1 T2 T3
96
97 logic unused_p2s_sent;
98 1/1 assign unused_p2s_sent = outclk_p2s_sent_i;
Tests: T1 T2 T3
99
100 assign io_mode_o = SingleIO;
101
102 typedef enum logic {
103 StIdle,
104 StActive
105 } st_e;
106 st_e st_q, st_d;
107
108 typedef enum int unsigned {
109 BitBusy = 0, // BUSY bit [0]
110 BitWe = 1 // WEL bit [1]
111 } status_bit_e;
112
113 ////////////
114 // Signal //
115 ////////////
116 logic [StatusW-1:0] sck_status_committed, csb_status_committed;
117 logic [StatusW-1:0] sck_status_staged;
118 logic [StatusW-1:0] sck_sw_status;
119 logic [StatusW-1:0] sck_status_to_commit;
120
121 logic p2s_valid_inclk;
122 spi_byte_t p2s_byte_inclk;
123
124 // FIFO rvalid , rready
125 logic sck_sw_we, sck_sw_ack;
126 ////////////////////////////
127 // Status CSR (incl. CDC) //
128 ////////////////////////////
129 //
130 // Flash mode STATUS register is implemented in this module rather than
131 // relying on the regtool. The reason is that the STATUS read by the SPI
132 // host system. The value should be propagated into SCK domain. Due to the
133 // lack of SCK while CSb is de-asserted, it needs special cares to safely
134 // used in SCK.
135 //
136 // Before returning the STATUS register value to the host system
137 // corresponding to the Read Status commands (05h, 35h, 15h), the logic can
138 // get 8 SCK clock edges. The logic synchronizes CSb into SCK domain first.
139 // Then create a pulse to latch the STATUS register in SCK domain.
140 //
141 // If a command is uploaded (handled by spid_upload), it sets BUSY bit to 1.
142 // The value is latched in the SCK domain first. Then, when CSb is
143 // de-asserted, the logic synchronizes CSb into the bus clock domain to
144 // create a pulse signal. That pulse signal will latch the STATUS register
145 // from SCK domain into the bus clock domain.
146 //
147 // The STATUS register in the bus clock domain can be updated only when CSb
148 // is not asserted in order to prevent any CDC issue. The safest way is to
149 // hand the busclock synched CSb signal over to SCK clock domain again but
150 // it may not be possible to latch the register within the 8th posedge of
151 // the SCK if the bus clock is slow.
152 //
153 // BUSY is set by HW. The value is not directly broadcasted to the
154 // passthrough module. It is, first, applied into the bus clock domain. Then
155 // the signal is broadcasted to Passthrough to filter-out the following
156 // commands until the BUSY signal is released.
157
158 // Design Doc
159 // https://docs.google.com/document/d/1wUIynMYVfVg9HmCL0q5-6r9BuN-XM0z--wGqU0bXRQ0
160
161 // assumes BUSY bit as 0
162 `ASSERT_INIT(BusyBitZero_A, BitBusy == 0)
163
164 // BUSY status in SCK
165 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
166 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
167 1/1 sck_status_staged[BitBusy] <= 1'b 0;
Tests: T1 T2 T3
168 1/1 end else if (inclk_busy_set_i) begin
Tests: T4 T5 T6
169 1/1 sck_status_staged[BitBusy] <= 1'b 1;
Tests: T19 T32 T54
170 1/1 end else if (sck_sw_we && (sck_sw_status[BitBusy] == 1'b 0)) begin
Tests: T4 T5 T6
171 1/1 sck_status_staged[BitBusy] <= 1'b 0;
Tests: T9 T11 T12
172 end
MISSING_ELSE
173 end
174
175 // WEL handling
176 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
177 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
178 1/1 sck_status_staged[BitWe] <= 1'b 0;
Tests: T1 T2 T3
179 1/1 end else if (inclk_we_set_i) begin
Tests: T4 T5 T6
180 1/1 sck_status_staged[BitWe] <= 1'b 1;
Tests: T19 T55 T32
181 1/1 end else if (inclk_we_clr_i) begin
Tests: T4 T5 T6
182 1/1 sck_status_staged[BitWe] <= 1'b 0;
Tests: T19 T32 T54
183 1/1 end else if (sck_sw_we && (sck_sw_status[BitWe] == 1'b0)) begin
Tests: T4 T5 T6
184 1/1 sck_status_staged[BitWe] <= sck_sw_status[BitWe];
Tests: T9 T11 T12
185 end
MISSING_ELSE
186 end
187
188 // Rest of Status
189 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
190 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
191 1/1 sck_status_staged[StatusW-1:BitWe+1] <= '0;
Tests: T1 T2 T3
192 1/1 end else if (sck_sw_we) begin
Tests: T4 T5 T6
193 1/1 sck_status_staged[StatusW-1:BitWe+1] <= sck_sw_status[StatusW-1:BitWe+1];
Tests: T9 T11 T12
194 end
MISSING_ELSE
195 end
196
197 // HW-originated WEL and WIP updates bypass the flop so they are committed
198 // immediately. The changes still must be placed in the flops above, so the
199 // staged values are correct for the next update.
200 // TODO(#21700): HW changes should not be allowed while BUSY
201 always_comb begin
202 1/1 sck_status_to_commit = sck_status_staged;
Tests: T1 T2 T3
203 1/1 if (inclk_we_set_i) begin
Tests: T1 T2 T3
204 1/1 sck_status_to_commit[BitWe] = 1'b1;
Tests: T19 T55 T32
205 1/1 end else if (inclk_we_clr_i) begin
Tests: T1 T2 T3
206 1/1 sck_status_to_commit[BitWe] = 1'b0;
Tests: T19 T30 T32
207 end
MISSING_ELSE
208 1/1 if (inclk_busy_set_i) begin
Tests: T1 T2 T3
209 1/1 sck_status_to_commit[BitBusy] = 1'b1;
Tests: T19 T32 T54
210 end
MISSING_ELSE
211 end
212
213 prim_flop_en #(
214 .Width ($bits(sck_status_committed)),
215 .ResetValue('0)
216 ) u_stage_to_commit (
217 .clk_i (clk_i),
218 .rst_ni (sys_rst_ni),
219 .en_i (inclk_status_commit_i),
220 .d_i (sck_status_to_commit),
221 .q_o (sck_status_committed)
222 );
223
224 1/1 assign cmd_sync_status_busy_o = sck_status_to_commit[BitBusy];
Tests: T1 T2 T3
225 1/1 assign cmd_sync_status_wel_o = sck_status_to_commit[BitWe];
Tests: T1 T2 T3
226 1/1 assign sck_status_busy_o = sck_status_committed[BitBusy];
Tests: T1 T2 T3
227
228 // Staged to Committed at CSb de-assertion
229 // SW and the passthrough gate only receive the final values of
230 // a transaction.
231 prim_flop #(
232 .Width ($bits(sck_status_committed)),
233 .ResetValue ('0)
234 ) u_sck2csb_status (
235 .clk_i (clk_csb_i),
236 .rst_ni (sys_rst_ni),
237 .d_i (sck_status_committed),
238 .q_o (csb_status_committed)
239 );
240
241 1/1 assign csb_busy_broadcast_o = csb_status_committed[BitBusy];
Tests: T1 T2 T3
242
243 // Status in SCK
244 assign sck_sw_ack = 1'b 1; // always accept when clock is valid.
245
246 // For normal SPI flash operation, there should only ever be one write from
247 // the SYS domain to update the status register in response to any command.
248 // Status register bits should never update outside of direct command
249 // responses. Thus, there should never be enough writes to fill the FIFO,
250 // since any subsequent command would clear the prior write.
251 // Note that this means that spi_device does not support using the status
252 // register for anything but the following:
253 // - initial "power-on / reset" values shown to the upstream host
254 // - values the host explicitly programmed via WRITE STATUS REGISTER types
255 // - hardware-updated BUSY and WEL bits
256 // Some SPI flash devices support reporting the address mode in one of the
257 // status bits. This IP does not. Support here would require another
258 // hardware-updated bit, to respond to EN4B and EX4B.
259 //
260 // To effect reliable support for initial values, allow resetting the FIFO
261 // to clear any state that may have built up from a prior session.
262 logic status_fifo_clr_n, status_fifo_rst_n;
263 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
264 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
265 1/1 status_fifo_clr_n <= 1'b0;
Tests: T1 T2 T3
266 end else begin
267 1/1 status_fifo_clr_n <= !sys_update_clr_i;
Tests: T1 T2 T3
268 end
269 end
270
271 prim_clock_mux2 #(
272 .NoFpgaBufG(1'b1)
273 ) u_csb_rst_scan_mux (
274 .clk0_i(status_fifo_clr_n),
275 .clk1_i(scan_rst_ni),
276 .sel_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)),
277 .clk_o(status_fifo_rst_n)
278 );
279
280 prim_fifo_async #(
281 .Width (StatusW),
282 .Depth (2),
283 .OutputZeroIfEmpty (1'b 1)
284 ) u_sw_status_update_sync (
285 .clk_wr_i (sys_clk_i ),
286 .rst_wr_ni (status_fifo_rst_n),
287 .wvalid_i (sys_status_we_i ),
288 .wready_o ( ), // ignore
289 .wdata_i (sys_status_i ),
290 .wdepth_o ( ),
291
292 .clk_rd_i (clk_i ),
293 .rst_rd_ni (status_fifo_rst_n),
294 .rvalid_o (sck_sw_we ),
295 .rready_i (sck_sw_ack ),
296 .rdata_o (sck_sw_status ),
297 .rdepth_o ( )
298 );
299
300 // Committed to SYS clk
301 // Timing requirements:
302 // - 3x sys_clk cycles < 8x spi_clk cycles + 1 CSB "cycle"
303 // Breakdown:
304 // - 2 sys_clk cycles to produce sys_csb_deasserted_pulse_i
305 // - 1 sys_clk cycle to latch csb_status_committed
306 // - Must execute before back-to-back WREN -> WRDI
307 // - Other bits have much longer stability
308 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
309 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
310 1/1 sys_status_o <= '0;
Tests: T1 T2 T3
311 1/1 end else if (sys_csb_deasserted_pulse_i) begin
Tests: T1 T2 T3
312 1/1 sys_status_o <= csb_status_committed;
Tests: T7 T8 T9
313 end
MISSING_ELSE
314 end
315
316 /////////////////
317 // Data Return //
318 /////////////////
319
320 // Latch in clk_out
321 always_ff @(posedge clk_out_i or negedge rst_out_ni) begin
322 1/1 if (!rst_out_ni) begin
Tests: T1 T2 T3
323 1/1 outclk_p2s_valid_o <= 1'b 0;
Tests: T1 T2 T3
324 1/1 outclk_p2s_byte_o <= '0;
Tests: T1 T2 T3
325 end else begin
326 1/1 outclk_p2s_valid_o <= p2s_valid_inclk;
Tests: T7 T8 T9
327 1/1 outclk_p2s_byte_o <= p2s_byte_inclk;
Tests: T7 T8 T9
328 end
329 end
330
331 // cmd_idx to data selector
332 logic [1:0] byte_sel_d, byte_sel_q;
333 logic byte_sel_update;
334
335 always_ff @(posedge clk_i or negedge rst_ni) begin
336 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
337 1/1 byte_sel_q <= 2'b 00;
Tests: T1 T2 T3
338 end else begin
339 1/1 byte_sel_q <= byte_sel_d;
Tests: T7 T8 T9
340 end
341 end
342
343 always_comb begin : byte_sel_input
344 1/1 byte_sel_d = byte_sel_q;
Tests: T1 T2 T3
345
346 1/1 if (byte_sel_update) begin
Tests: T1 T2 T3
347 // Check input command index and assign initial byte_sel
348 1/1 byte_sel_d = 2'b 00; // default value
Tests: T19 T51 T56
349
350 1/1 for (int unsigned i = 0 ; i <= 2 ; i++) begin
Tests: T19 T51 T56
351 1/1 if (cmd_info_idx_i == CmdInfoIdxW'(StatusCmdIdx[i])) begin
Tests: T19 T51 T56
352 1/1 byte_sel_d = i;
Tests: T19 T51 T56
353 end
MISSING_ELSE
354 end
355 end
MISSING_ELSE
356 end : byte_sel_input
357
358 1/1 assign p2s_byte_inclk = (st_q == StIdle)
Tests: T1 T2 T3
359 ? sck_status_committed[8*byte_sel_d+:8]
360 : sck_status_committed[8*byte_sel_q+:8];
361
362 // State Machine
363
364 always_ff @(posedge clk_i or negedge rst_ni) begin
365 2/2 if (!rst_ni) st_q <= StIdle;
Tests: T1 T2 T3 | T1 T2 T3
366 1/1 else st_q <= st_d;
Tests: T7 T8 T9
367 end
368
369 always_comb begin
370 1/1 st_d = st_q;
Tests: T1 T2 T3
371
372 1/1 byte_sel_update = 1'b 0;
Tests: T1 T2 T3
373
374 1/1 p2s_valid_inclk = 1'b 0;
Tests: T1 T2 T3
375
376 1/1 unique case (st_q)
Tests: T1 T2 T3
377 StIdle: begin
378 1/1 if (sel_dp_i == DpReadStatus) begin
Tests: T1 T2 T3
379 1/1 st_d = StActive;
Tests: T19 T51 T56
380 // dp asserted after 8th SCK. Should send out the data right away.
381 1/1 byte_sel_update = 1'b 1;
Tests: T19 T51 T56
382 1/1 p2s_valid_inclk = 1'b 1;
Tests: T19 T51 T56
383 end
MISSING_ELSE
384 end
385
386 StActive: begin
387 1/1 p2s_valid_inclk = 1'b 1;
Tests: T19 T51 T56
388 // deadend state
389 end
390
391 default: begin
392 st_d = StIdle;
Cond Coverage for Module :
spid_status
| Total | Covered | Percent |
|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 170
EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
----1---- ----------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T9,T11,T12 |
| 1 | 1 | Covered | T9,T11,T12 |
LINE 170
SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9,T11,T12 |
| 1 | Covered | T4,T5,T6 |
LINE 183
EXPRESSION (sck_sw_we && (sck_sw_status[BitWe] == 1'b0))
----1---- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T9,T11,T12 |
| 1 | 1 | Covered | T9,T11,T12 |
LINE 183
SUB-EXPRESSION (sck_sw_status[BitWe] == 1'b0)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9,T11,T12 |
| 1 | Covered | T4,T5,T6 |
LINE 351
EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T51,T56 |
| 1 | Covered | T19,T51,T56 |
LINE 358
EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T51,T56 |
| 1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (st_q == StIdle)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 378
EXPRESSION (sel_dp_i == DpReadStatus)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T51,T56 |
Branch Coverage for Module :
spid_status
| Line No. | Total | Covered | Percent |
| Branches |
|
36 |
35 |
97.22 |
| TERNARY |
358 |
2 |
2 |
100.00 |
| IF |
166 |
4 |
4 |
100.00 |
| IF |
177 |
5 |
5 |
100.00 |
| IF |
190 |
3 |
3 |
100.00 |
| IF |
203 |
3 |
3 |
100.00 |
| IF |
208 |
2 |
2 |
100.00 |
| IF |
264 |
2 |
2 |
100.00 |
| IF |
309 |
3 |
3 |
100.00 |
| IF |
322 |
2 |
2 |
100.00 |
| IF |
336 |
2 |
2 |
100.00 |
| IF |
346 |
2 |
2 |
100.00 |
| IF |
365 |
2 |
2 |
100.00 |
| CASE |
376 |
4 |
3 |
75.00 |
358 assign p2s_byte_inclk = (st_q == StIdle)
359 ? sck_status_committed[8*byte_sel_d+:8]
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T19,T51,T56 |
166 if (!sys_rst_ni) begin
-1-
167 sck_status_staged[BitBusy] <= 1'b 0;
==>
168 end else if (inclk_busy_set_i) begin
-2-
169 sck_status_staged[BitBusy] <= 1'b 1;
==>
170 end else if (sck_sw_we && (sck_sw_status[BitBusy] == 1'b 0)) begin
-3-
171 sck_status_staged[BitBusy] <= 1'b 0;
==>
172 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
Covered |
T9,T11,T12 |
| 0 |
0 |
0 |
Covered |
T4,T5,T6 |
177 if (!sys_rst_ni) begin
-1-
178 sck_status_staged[BitWe] <= 1'b 0;
==>
179 end else if (inclk_we_set_i) begin
-2-
180 sck_status_staged[BitWe] <= 1'b 1;
==>
181 end else if (inclk_we_clr_i) begin
-3-
182 sck_status_staged[BitWe] <= 1'b 0;
==>
183 end else if (sck_sw_we && (sck_sw_status[BitWe] == 1'b0)) begin
-4-
184 sck_status_staged[BitWe] <= sck_sw_status[BitWe];
==>
185 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T55,T32 |
| 0 |
0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
1 |
Covered |
T9,T11,T12 |
| 0 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
190 if (!sys_rst_ni) begin
-1-
191 sck_status_staged[StatusW-1:BitWe+1] <= '0;
==>
192 end else if (sck_sw_we) begin
-2-
193 sck_status_staged[StatusW-1:BitWe+1] <= sck_sw_status[StatusW-1:BitWe+1];
==>
194 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T9,T11,T12 |
| 0 |
0 |
Covered |
T4,T5,T6 |
203 if (inclk_we_set_i) begin
-1-
204 sck_status_to_commit[BitWe] = 1'b1;
==>
205 end else if (inclk_we_clr_i) begin
-2-
206 sck_status_to_commit[BitWe] = 1'b0;
==>
207 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T19,T55,T32 |
| 0 |
1 |
Covered |
T19,T30,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
208 if (inclk_busy_set_i) begin
-1-
209 sck_status_to_commit[BitBusy] = 1'b1;
==>
210 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T32,T54 |
| 0 |
Covered |
T1,T2,T3 |
264 if (!sys_rst_ni) begin
-1-
265 status_fifo_clr_n <= 1'b0;
==>
266 end else begin
267 status_fifo_clr_n <= !sys_update_clr_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
309 if (!sys_rst_ni) begin
-1-
310 sys_status_o <= '0;
==>
311 end else if (sys_csb_deasserted_pulse_i) begin
-2-
312 sys_status_o <= csb_status_committed;
==>
313 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T7,T8,T9 |
| 0 |
0 |
Covered |
T1,T2,T3 |
322 if (!rst_out_ni) begin
-1-
323 outclk_p2s_valid_o <= 1'b 0;
==>
324 outclk_p2s_byte_o <= '0;
325 end else begin
326 outclk_p2s_valid_o <= p2s_valid_inclk;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
336 if (!rst_ni) begin
-1-
337 byte_sel_q <= 2'b 00;
==>
338 end else begin
339 byte_sel_q <= byte_sel_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
346 if (byte_sel_update) begin
-1-
347 // Check input command index and assign initial byte_sel
348 byte_sel_d = 2'b 00; // default value
==>
349
350 for (int unsigned i = 0 ; i <= 2 ; i++) begin
351 if (cmd_info_idx_i == CmdInfoIdxW'(StatusCmdIdx[i])) begin
352 byte_sel_d = i;
353 end
354 end
355 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T51,T56 |
| 0 |
Covered |
T1,T2,T3 |
365 if (!rst_ni) st_q <= StIdle;
-1-
==>
366 else st_q <= st_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
376 unique case (st_q)
-1-
377 StIdle: begin
378 if (sel_dp_i == DpReadStatus) begin
-2-
379 st_d = StActive;
==>
380 // dp asserted after 8th SCK. Should send out the data right away.
381 byte_sel_update = 1'b 1;
382 p2s_valid_inclk = 1'b 1;
383 end
MISSING_ELSE
==>
384 end
385
386 StActive: begin
387 p2s_valid_inclk = 1'b 1;
==>
388 // deadend state
389 end
390
391 default: begin
392 st_d = StIdle;
==>
Branches:
| -1- | -2- | Status | Tests |
| StIdle |
1 |
Covered |
T19,T51,T56 |
| StIdle |
0 |
Covered |
T1,T2,T3 |
| StActive |
- |
Covered |
T19,T51,T56 |
| default |
- |
Not Covered |
|
Assert Coverage for Module :
spid_status
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
BusyBitZero_A |
976 |
976 |
0 |
0 |
BusyBitZero_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spid_status
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 65 | 65 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
| ALWAYS | 166 | 6 | 6 | 100.00 |
| ALWAYS | 177 | 8 | 8 | 100.00 |
| ALWAYS | 190 | 4 | 4 | 100.00 |
| ALWAYS | 202 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 226 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
| ALWAYS | 264 | 3 | 3 | 100.00 |
| ALWAYS | 309 | 4 | 4 | 100.00 |
| ALWAYS | 322 | 5 | 5 | 100.00 |
| ALWAYS | 336 | 3 | 3 | 100.00 |
| ALWAYS | 344 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| ALWAYS | 365 | 3 | 3 | 100.00 |
| ALWAYS | 370 | 9 | 9 | 100.00 |
94 logic unused_cmd_info;
95 1/1 assign unused_cmd_info = ^cmd_info_i;
Tests: T1 T2 T3
96
97 logic unused_p2s_sent;
98 1/1 assign unused_p2s_sent = outclk_p2s_sent_i;
Tests: T1 T2 T3
99
100 assign io_mode_o = SingleIO;
101
102 typedef enum logic {
103 StIdle,
104 StActive
105 } st_e;
106 st_e st_q, st_d;
107
108 typedef enum int unsigned {
109 BitBusy = 0, // BUSY bit [0]
110 BitWe = 1 // WEL bit [1]
111 } status_bit_e;
112
113 ////////////
114 // Signal //
115 ////////////
116 logic [StatusW-1:0] sck_status_committed, csb_status_committed;
117 logic [StatusW-1:0] sck_status_staged;
118 logic [StatusW-1:0] sck_sw_status;
119 logic [StatusW-1:0] sck_status_to_commit;
120
121 logic p2s_valid_inclk;
122 spi_byte_t p2s_byte_inclk;
123
124 // FIFO rvalid , rready
125 logic sck_sw_we, sck_sw_ack;
126 ////////////////////////////
127 // Status CSR (incl. CDC) //
128 ////////////////////////////
129 //
130 // Flash mode STATUS register is implemented in this module rather than
131 // relying on the regtool. The reason is that the STATUS read by the SPI
132 // host system. The value should be propagated into SCK domain. Due to the
133 // lack of SCK while CSb is de-asserted, it needs special cares to safely
134 // used in SCK.
135 //
136 // Before returning the STATUS register value to the host system
137 // corresponding to the Read Status commands (05h, 35h, 15h), the logic can
138 // get 8 SCK clock edges. The logic synchronizes CSb into SCK domain first.
139 // Then create a pulse to latch the STATUS register in SCK domain.
140 //
141 // If a command is uploaded (handled by spid_upload), it sets BUSY bit to 1.
142 // The value is latched in the SCK domain first. Then, when CSb is
143 // de-asserted, the logic synchronizes CSb into the bus clock domain to
144 // create a pulse signal. That pulse signal will latch the STATUS register
145 // from SCK domain into the bus clock domain.
146 //
147 // The STATUS register in the bus clock domain can be updated only when CSb
148 // is not asserted in order to prevent any CDC issue. The safest way is to
149 // hand the busclock synched CSb signal over to SCK clock domain again but
150 // it may not be possible to latch the register within the 8th posedge of
151 // the SCK if the bus clock is slow.
152 //
153 // BUSY is set by HW. The value is not directly broadcasted to the
154 // passthrough module. It is, first, applied into the bus clock domain. Then
155 // the signal is broadcasted to Passthrough to filter-out the following
156 // commands until the BUSY signal is released.
157
158 // Design Doc
159 // https://docs.google.com/document/d/1wUIynMYVfVg9HmCL0q5-6r9BuN-XM0z--wGqU0bXRQ0
160
161 // assumes BUSY bit as 0
162 `ASSERT_INIT(BusyBitZero_A, BitBusy == 0)
163
164 // BUSY status in SCK
165 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
166 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
167 1/1 sck_status_staged[BitBusy] <= 1'b 0;
Tests: T1 T2 T3
168 1/1 end else if (inclk_busy_set_i) begin
Tests: T4 T5 T6
169 1/1 sck_status_staged[BitBusy] <= 1'b 1;
Tests: T19 T32 T54
170 1/1 end else if (sck_sw_we && (sck_sw_status[BitBusy] == 1'b 0)) begin
Tests: T4 T5 T6
171 1/1 sck_status_staged[BitBusy] <= 1'b 0;
Tests: T9 T11 T12
172 end
MISSING_ELSE
173 end
174
175 // WEL handling
176 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
177 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
178 1/1 sck_status_staged[BitWe] <= 1'b 0;
Tests: T1 T2 T3
179 1/1 end else if (inclk_we_set_i) begin
Tests: T4 T5 T6
180 1/1 sck_status_staged[BitWe] <= 1'b 1;
Tests: T19 T55 T32
181 1/1 end else if (inclk_we_clr_i) begin
Tests: T4 T5 T6
182 1/1 sck_status_staged[BitWe] <= 1'b 0;
Tests: T19 T32 T54
183 1/1 end else if (sck_sw_we && (sck_sw_status[BitWe] == 1'b0)) begin
Tests: T4 T5 T6
184 1/1 sck_status_staged[BitWe] <= sck_sw_status[BitWe];
Tests: T9 T11 T12
185 end
MISSING_ELSE
186 end
187
188 // Rest of Status
189 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
190 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
191 1/1 sck_status_staged[StatusW-1:BitWe+1] <= '0;
Tests: T1 T2 T3
192 1/1 end else if (sck_sw_we) begin
Tests: T4 T5 T6
193 1/1 sck_status_staged[StatusW-1:BitWe+1] <= sck_sw_status[StatusW-1:BitWe+1];
Tests: T9 T11 T12
194 end
MISSING_ELSE
195 end
196
197 // HW-originated WEL and WIP updates bypass the flop so they are committed
198 // immediately. The changes still must be placed in the flops above, so the
199 // staged values are correct for the next update.
200 // TODO(#21700): HW changes should not be allowed while BUSY
201 always_comb begin
202 1/1 sck_status_to_commit = sck_status_staged;
Tests: T1 T2 T3
203 1/1 if (inclk_we_set_i) begin
Tests: T1 T2 T3
204 1/1 sck_status_to_commit[BitWe] = 1'b1;
Tests: T19 T55 T32
205 1/1 end else if (inclk_we_clr_i) begin
Tests: T1 T2 T3
206 1/1 sck_status_to_commit[BitWe] = 1'b0;
Tests: T19 T30 T32
207 end
MISSING_ELSE
208 1/1 if (inclk_busy_set_i) begin
Tests: T1 T2 T3
209 1/1 sck_status_to_commit[BitBusy] = 1'b1;
Tests: T19 T32 T54
210 end
MISSING_ELSE
211 end
212
213 prim_flop_en #(
214 .Width ($bits(sck_status_committed)),
215 .ResetValue('0)
216 ) u_stage_to_commit (
217 .clk_i (clk_i),
218 .rst_ni (sys_rst_ni),
219 .en_i (inclk_status_commit_i),
220 .d_i (sck_status_to_commit),
221 .q_o (sck_status_committed)
222 );
223
224 1/1 assign cmd_sync_status_busy_o = sck_status_to_commit[BitBusy];
Tests: T1 T2 T3
225 1/1 assign cmd_sync_status_wel_o = sck_status_to_commit[BitWe];
Tests: T1 T2 T3
226 1/1 assign sck_status_busy_o = sck_status_committed[BitBusy];
Tests: T1 T2 T3
227
228 // Staged to Committed at CSb de-assertion
229 // SW and the passthrough gate only receive the final values of
230 // a transaction.
231 prim_flop #(
232 .Width ($bits(sck_status_committed)),
233 .ResetValue ('0)
234 ) u_sck2csb_status (
235 .clk_i (clk_csb_i),
236 .rst_ni (sys_rst_ni),
237 .d_i (sck_status_committed),
238 .q_o (csb_status_committed)
239 );
240
241 1/1 assign csb_busy_broadcast_o = csb_status_committed[BitBusy];
Tests: T1 T2 T3
242
243 // Status in SCK
244 assign sck_sw_ack = 1'b 1; // always accept when clock is valid.
245
246 // For normal SPI flash operation, there should only ever be one write from
247 // the SYS domain to update the status register in response to any command.
248 // Status register bits should never update outside of direct command
249 // responses. Thus, there should never be enough writes to fill the FIFO,
250 // since any subsequent command would clear the prior write.
251 // Note that this means that spi_device does not support using the status
252 // register for anything but the following:
253 // - initial "power-on / reset" values shown to the upstream host
254 // - values the host explicitly programmed via WRITE STATUS REGISTER types
255 // - hardware-updated BUSY and WEL bits
256 // Some SPI flash devices support reporting the address mode in one of the
257 // status bits. This IP does not. Support here would require another
258 // hardware-updated bit, to respond to EN4B and EX4B.
259 //
260 // To effect reliable support for initial values, allow resetting the FIFO
261 // to clear any state that may have built up from a prior session.
262 logic status_fifo_clr_n, status_fifo_rst_n;
263 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
264 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
265 1/1 status_fifo_clr_n <= 1'b0;
Tests: T1 T2 T3
266 end else begin
267 1/1 status_fifo_clr_n <= !sys_update_clr_i;
Tests: T1 T2 T3
268 end
269 end
270
271 prim_clock_mux2 #(
272 .NoFpgaBufG(1'b1)
273 ) u_csb_rst_scan_mux (
274 .clk0_i(status_fifo_clr_n),
275 .clk1_i(scan_rst_ni),
276 .sel_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)),
277 .clk_o(status_fifo_rst_n)
278 );
279
280 prim_fifo_async #(
281 .Width (StatusW),
282 .Depth (2),
283 .OutputZeroIfEmpty (1'b 1)
284 ) u_sw_status_update_sync (
285 .clk_wr_i (sys_clk_i ),
286 .rst_wr_ni (status_fifo_rst_n),
287 .wvalid_i (sys_status_we_i ),
288 .wready_o ( ), // ignore
289 .wdata_i (sys_status_i ),
290 .wdepth_o ( ),
291
292 .clk_rd_i (clk_i ),
293 .rst_rd_ni (status_fifo_rst_n),
294 .rvalid_o (sck_sw_we ),
295 .rready_i (sck_sw_ack ),
296 .rdata_o (sck_sw_status ),
297 .rdepth_o ( )
298 );
299
300 // Committed to SYS clk
301 // Timing requirements:
302 // - 3x sys_clk cycles < 8x spi_clk cycles + 1 CSB "cycle"
303 // Breakdown:
304 // - 2 sys_clk cycles to produce sys_csb_deasserted_pulse_i
305 // - 1 sys_clk cycle to latch csb_status_committed
306 // - Must execute before back-to-back WREN -> WRDI
307 // - Other bits have much longer stability
308 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
309 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
310 1/1 sys_status_o <= '0;
Tests: T1 T2 T3
311 1/1 end else if (sys_csb_deasserted_pulse_i) begin
Tests: T1 T2 T3
312 1/1 sys_status_o <= csb_status_committed;
Tests: T7 T8 T9
313 end
MISSING_ELSE
314 end
315
316 /////////////////
317 // Data Return //
318 /////////////////
319
320 // Latch in clk_out
321 always_ff @(posedge clk_out_i or negedge rst_out_ni) begin
322 1/1 if (!rst_out_ni) begin
Tests: T1 T2 T3
323 1/1 outclk_p2s_valid_o <= 1'b 0;
Tests: T1 T2 T3
324 1/1 outclk_p2s_byte_o <= '0;
Tests: T1 T2 T3
325 end else begin
326 1/1 outclk_p2s_valid_o <= p2s_valid_inclk;
Tests: T7 T8 T9
327 1/1 outclk_p2s_byte_o <= p2s_byte_inclk;
Tests: T7 T8 T9
328 end
329 end
330
331 // cmd_idx to data selector
332 logic [1:0] byte_sel_d, byte_sel_q;
333 logic byte_sel_update;
334
335 always_ff @(posedge clk_i or negedge rst_ni) begin
336 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
337 1/1 byte_sel_q <= 2'b 00;
Tests: T1 T2 T3
338 end else begin
339 1/1 byte_sel_q <= byte_sel_d;
Tests: T7 T8 T9
340 end
341 end
342
343 always_comb begin : byte_sel_input
344 1/1 byte_sel_d = byte_sel_q;
Tests: T1 T2 T3
345
346 1/1 if (byte_sel_update) begin
Tests: T1 T2 T3
347 // Check input command index and assign initial byte_sel
348 1/1 byte_sel_d = 2'b 00; // default value
Tests: T19 T51 T56
349
350 1/1 for (int unsigned i = 0 ; i <= 2 ; i++) begin
Tests: T19 T51 T56
351 1/1 if (cmd_info_idx_i == CmdInfoIdxW'(StatusCmdIdx[i])) begin
Tests: T19 T51 T56
352 1/1 byte_sel_d = i;
Tests: T19 T51 T56
353 end
MISSING_ELSE
354 end
355 end
MISSING_ELSE
356 end : byte_sel_input
357
358 1/1 assign p2s_byte_inclk = (st_q == StIdle)
Tests: T1 T2 T3
359 ? sck_status_committed[8*byte_sel_d+:8]
360 : sck_status_committed[8*byte_sel_q+:8];
361
362 // State Machine
363
364 always_ff @(posedge clk_i or negedge rst_ni) begin
365 2/2 if (!rst_ni) st_q <= StIdle;
Tests: T1 T2 T3 | T1 T2 T3
366 1/1 else st_q <= st_d;
Tests: T7 T8 T9
367 end
368
369 always_comb begin
370 1/1 st_d = st_q;
Tests: T1 T2 T3
371
372 1/1 byte_sel_update = 1'b 0;
Tests: T1 T2 T3
373
374 1/1 p2s_valid_inclk = 1'b 0;
Tests: T1 T2 T3
375
376 1/1 unique case (st_q)
Tests: T1 T2 T3
377 StIdle: begin
378 1/1 if (sel_dp_i == DpReadStatus) begin
Tests: T1 T2 T3
379 1/1 st_d = StActive;
Tests: T19 T51 T56
380 // dp asserted after 8th SCK. Should send out the data right away.
381 1/1 byte_sel_update = 1'b 1;
Tests: T19 T51 T56
382 1/1 p2s_valid_inclk = 1'b 1;
Tests: T19 T51 T56
383 end
MISSING_ELSE
384 end
385
386 StActive: begin
387 1/1 p2s_valid_inclk = 1'b 1;
Tests: T19 T51 T56
388 // deadend state
389 end
390
391 default: begin
392 st_d = StIdle;
Exclude Annotation: VC_COV_UNR
Cond Coverage for Instance : tb.dut.u_spid_status
| Total | Covered | Percent |
|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 170
EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
----1---- ----------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T9,T11,T12 |
| 1 | 1 | Covered | T9,T11,T12 |
LINE 170
SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9,T11,T12 |
| 1 | Covered | T4,T5,T6 |
LINE 183
EXPRESSION (sck_sw_we && (sck_sw_status[BitWe] == 1'b0))
----1---- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T9,T11,T12 |
| 1 | 1 | Covered | T9,T11,T12 |
LINE 183
SUB-EXPRESSION (sck_sw_status[BitWe] == 1'b0)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9,T11,T12 |
| 1 | Covered | T4,T5,T6 |
LINE 351
EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T51,T56 |
| 1 | Covered | T19,T51,T56 |
LINE 358
EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T51,T56 |
| 1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (st_q == StIdle)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 378
EXPRESSION (sel_dp_i == DpReadStatus)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T51,T56 |
Branch Coverage for Instance : tb.dut.u_spid_status
| Line No. | Total | Covered | Percent |
| Branches |
|
35 |
35 |
100.00 |
| TERNARY |
358 |
2 |
2 |
100.00 |
| IF |
166 |
4 |
4 |
100.00 |
| IF |
177 |
5 |
5 |
100.00 |
| IF |
190 |
3 |
3 |
100.00 |
| IF |
203 |
3 |
3 |
100.00 |
| IF |
208 |
2 |
2 |
100.00 |
| IF |
264 |
2 |
2 |
100.00 |
| IF |
309 |
3 |
3 |
100.00 |
| IF |
322 |
2 |
2 |
100.00 |
| IF |
336 |
2 |
2 |
100.00 |
| IF |
346 |
2 |
2 |
100.00 |
| IF |
365 |
2 |
2 |
100.00 |
| CASE |
376 |
3 |
3 |
100.00 |
358 assign p2s_byte_inclk = (st_q == StIdle)
359 ? sck_status_committed[8*byte_sel_d+:8]
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T19,T51,T56 |
166 if (!sys_rst_ni) begin
-1-
167 sck_status_staged[BitBusy] <= 1'b 0;
==>
168 end else if (inclk_busy_set_i) begin
-2-
169 sck_status_staged[BitBusy] <= 1'b 1;
==>
170 end else if (sck_sw_we && (sck_sw_status[BitBusy] == 1'b 0)) begin
-3-
171 sck_status_staged[BitBusy] <= 1'b 0;
==>
172 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
Covered |
T9,T11,T12 |
| 0 |
0 |
0 |
Covered |
T4,T5,T6 |
177 if (!sys_rst_ni) begin
-1-
178 sck_status_staged[BitWe] <= 1'b 0;
==>
179 end else if (inclk_we_set_i) begin
-2-
180 sck_status_staged[BitWe] <= 1'b 1;
==>
181 end else if (inclk_we_clr_i) begin
-3-
182 sck_status_staged[BitWe] <= 1'b 0;
==>
183 end else if (sck_sw_we && (sck_sw_status[BitWe] == 1'b0)) begin
-4-
184 sck_status_staged[BitWe] <= sck_sw_status[BitWe];
==>
185 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T55,T32 |
| 0 |
0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
1 |
Covered |
T9,T11,T12 |
| 0 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
190 if (!sys_rst_ni) begin
-1-
191 sck_status_staged[StatusW-1:BitWe+1] <= '0;
==>
192 end else if (sck_sw_we) begin
-2-
193 sck_status_staged[StatusW-1:BitWe+1] <= sck_sw_status[StatusW-1:BitWe+1];
==>
194 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T9,T11,T12 |
| 0 |
0 |
Covered |
T4,T5,T6 |
203 if (inclk_we_set_i) begin
-1-
204 sck_status_to_commit[BitWe] = 1'b1;
==>
205 end else if (inclk_we_clr_i) begin
-2-
206 sck_status_to_commit[BitWe] = 1'b0;
==>
207 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T19,T55,T32 |
| 0 |
1 |
Covered |
T19,T30,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
208 if (inclk_busy_set_i) begin
-1-
209 sck_status_to_commit[BitBusy] = 1'b1;
==>
210 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T32,T54 |
| 0 |
Covered |
T1,T2,T3 |
264 if (!sys_rst_ni) begin
-1-
265 status_fifo_clr_n <= 1'b0;
==>
266 end else begin
267 status_fifo_clr_n <= !sys_update_clr_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
309 if (!sys_rst_ni) begin
-1-
310 sys_status_o <= '0;
==>
311 end else if (sys_csb_deasserted_pulse_i) begin
-2-
312 sys_status_o <= csb_status_committed;
==>
313 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T7,T8,T9 |
| 0 |
0 |
Covered |
T1,T2,T3 |
322 if (!rst_out_ni) begin
-1-
323 outclk_p2s_valid_o <= 1'b 0;
==>
324 outclk_p2s_byte_o <= '0;
325 end else begin
326 outclk_p2s_valid_o <= p2s_valid_inclk;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
336 if (!rst_ni) begin
-1-
337 byte_sel_q <= 2'b 00;
==>
338 end else begin
339 byte_sel_q <= byte_sel_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
346 if (byte_sel_update) begin
-1-
347 // Check input command index and assign initial byte_sel
348 byte_sel_d = 2'b 00; // default value
==>
349
350 for (int unsigned i = 0 ; i <= 2 ; i++) begin
351 if (cmd_info_idx_i == CmdInfoIdxW'(StatusCmdIdx[i])) begin
352 byte_sel_d = i;
353 end
354 end
355 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T51,T56 |
| 0 |
Covered |
T1,T2,T3 |
365 if (!rst_ni) st_q <= StIdle;
-1-
==>
366 else st_q <= st_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
376 unique case (st_q)
-1-
377 StIdle: begin
378 if (sel_dp_i == DpReadStatus) begin
-2-
379 st_d = StActive;
==>
380 // dp asserted after 8th SCK. Should send out the data right away.
381 byte_sel_update = 1'b 1;
382 p2s_valid_inclk = 1'b 1;
383 end
MISSING_ELSE
==>
384 end
385
386 StActive: begin
387 p2s_valid_inclk = 1'b 1;
==>
388 // deadend state
389 end
390
391 default: begin
392 st_d = StIdle;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| StIdle |
1 |
Covered |
T19,T51,T56 |
|
| StIdle |
0 |
Covered |
T1,T2,T3 |
|
| StActive |
- |
Covered |
T19,T51,T56 |
|
| default |
- |
Excluded |
|
VC_COV_UNR |
Assert Coverage for Instance : tb.dut.u_spid_status
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
BusyBitZero_A |
976 |
976 |
0 |
0 |
BusyBitZero_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |