Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	80.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.58	95.00	80.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.36	98.25	100.00		100.00	93.55	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	90.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	95.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.36	98.25	100.00		100.00	93.55	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.94	92.31	45.45			83.33	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.46	91.67	44.83			66.67	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
70.00	100.00	40.00					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.77	91.30	44.44			55.56

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.25	100.00	85.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	95.00	82.50			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.34	99.29	93.36		91.67	97.40	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.31	100.00	69.23			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.07	100.00	81.82			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.94	95.83	76.84			90.48	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.93	85.71	100.00			83.33	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.97	94.29	100.00			90.91	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.94	95.83	76.84			90.48	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T7 T8 T9 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T7 T8 T9 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T7 T9 T12 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T7 T9 T12 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T7 T9 T12 

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	20	16	80.00
Logical	20	16	80.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T7,T9,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T8,T9
1	0	1	Not Covered
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T7,T9,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T7,T9,T12
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T9,T12,T13

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T12

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T9,T12

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T12
1	0	Covered	T7,T9,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T12
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T12
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	146533180	22220204	0	0
DataKnown_AKnownEnable	146533180	119952536	0	0
DepthKnown_A	146533180	119952536	0	0
RvalidKnown_A	146533180	119952536	0	0
WreadyKnown_A	146533180	119952536	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	146533180	22220204	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	22220204	0	0
T7	31058	22	0	0
T8	10480	0	0	0
T9	8888	1708	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	1942	0	0
T13	93908	10016	0	0
T14	16979	15913	0	0
T26	1159	0	0	0
T27	3656	0	0	0
T30	0	16297	0	0
T32	0	19459	0	0
T45	0	9644	0	0
T51	0	3980	0	0
T52	0	22092	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	22220204	0	0
T7	31058	22	0	0
T8	10480	0	0	0
T9	8888	1708	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	1942	0	0
T13	93908	10016	0	0
T14	16979	15913	0	0
T26	1159	0	0	0
T27	3656	0	0	0
T30	0	16297	0	0
T32	0	19459	0	0
T45	0	9644	0	0
T51	0	3980	0	0
T52	0	22092	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T7 T8 T9 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T7 T8 T9 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T7 T9 T12 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T7 T9 T12 

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	20	18	90.00
Logical	20	18	90.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T7,T9,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T8,T9
1	0	1	Covered	T7,T9,T12
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T7,T9,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T7,T9,T12
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T7,T9,T12

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T12

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T9,T12

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T13
1	0	Covered	T7,T9,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T12
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T12
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	146533180	23363989	0	0
DataKnown_AKnownEnable	146533180	119952536	0	0
DepthKnown_A	146533180	119952536	0	0
RvalidKnown_A	146533180	119952536	0	0
WreadyKnown_A	146533180	119952536	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	146533180	23363989	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	23363989	0	0
T7	31058	18	0	0
T8	10480	0	0	0
T9	8888	1816	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	2216	0	0
T13	93908	10394	0	0
T14	16979	16699	0	0
T26	1159	0	0	0
T27	3656	0	0	0
T30	0	17692	0	0
T32	0	20166	0	0
T45	0	10816	0	0
T51	0	4104	0	0
T52	0	22920	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	23363989	0	0
T7	31058	18	0	0
T8	10480	0	0	0
T9	8888	1816	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	2216	0	0
T13	93908	10394	0	0
T14	16979	16699	0	0
T26	1159	0	0	0
T27	3656	0	0	0
T30	0	17692	0	0
T32	0	20166	0	0
T45	0	10816	0	0
T51	0	4104	0	0
T52	0	22920	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T7 T8 T9 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T7 T8 T9 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
124        excluded               storage[fifo_wptr] <= wdata_i;
Exclude Annotation: VC_COV_UNR
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        0/1     ==>        assign rdata_int = storage_rdata;
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	11	5	45.45
Logical	11	5	45.45
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T8,T9
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Not Covered
1	1	0	Excluded		VC_COV_UNR
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	1	1	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		VC_COV_UNR
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	4	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	4	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	146533180	0	0	0
DataKnown_AKnownEnable	146533180	119952536	0	0
DepthKnown_A	146533180	119952536	0	0
RvalidKnown_A	146533180	119952536	0	0
WreadyKnown_A	146533180	119952536	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	146533180	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	0	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	119952536	0	0
T7	31058	31058	0	0
T8	10480	10480	0	0
T9	8888	8888	0	0
T10	109671	0	0	0
T11	14640	14640	0	0
T12	5392	5392	0	0
T13	93908	93738	0	0
T14	16979	16979	0	0
T17	0	2128	0	0
T18	0	96	0	0
T19	0	54621	0	0
T26	1159	0	0	0
T27	3656	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T4 T5 T6 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T4 T5 T6 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T5 T6 T27 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T5 T6 T27 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T6 T27 

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	20	17	85.00
Logical	20	17	85.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T5,T6,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T6,T27
1	0	1	Covered	T5,T6,T27
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T5,T6,T27

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T27

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T27

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T27
1	0	Covered	T5,T6,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	146533180	5100045	0	0
DataKnown_AKnownEnable	146533180	25344785	0	0
DepthKnown_A	146533180	25344785	0	0
RvalidKnown_A	146533180	25344785	0	0
WreadyKnown_A	146533180	25344785	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	146533180	5100045	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	5100045	0	0
T5	128	38	0	0
T6	65683	14106	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T14	16979	0	0	0
T27	0	1756	0	0
T28	0	25669	0	0
T30	0	36900	0	0
T32	0	31930	0	0
T34	0	1073	0	0
T63	0	33838	0	0
T64	0	131	0	0
T65	0	27032	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	5100045	0	0
T5	128	38	0	0
T6	65683	14106	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T14	16979	0	0	0
T27	0	1756	0	0
T28	0	25669	0	0
T30	0	36900	0	0
T32	0	31930	0	0
T34	0	1073	0	0
T63	0	33838	0	0
T64	0	131	0	0
T65	0	27032	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T4 T5 T6 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T4 T5 T6 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T6 T27 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T6 T27 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T5,T6,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Not Covered
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T5,T6,T27

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T27

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	146533180	163914	0	0
DataKnown_AKnownEnable	146533180	25344785	0	0
DepthKnown_A	146533180	25344785	0	0
RvalidKnown_A	146533180	25344785	0	0
WreadyKnown_A	146533180	25344785	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	146533180	163914	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	163914	0	0
T5	128	1	0	0
T6	65683	454	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T14	16979	0	0	0
T27	0	58	0	0
T28	0	821	0	0
T30	0	1181	0	0
T32	0	1030	0	0
T34	0	34	0	0
T63	0	1088	0	0
T64	0	5	0	0
T65	0	875	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	25344785	0	0
T4	72	72	0	0
T5	128	128	0	0
T6	65683	63616	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	105320	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T26	0	1008	0	0
T27	0	3656	0	0
T28	0	220328	0	0
T29	0	91744	0	0
T30	0	145112	0	0
T32	0	145392	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	146533180	163914	0	0
T5	128	1	0	0
T6	65683	454	0	0
T7	31058	0	0	0
T8	10480	0	0	0
T9	8888	0	0	0
T10	109671	0	0	0
T11	14640	0	0	0
T12	5392	0	0	0
T13	93908	0	0	0
T14	16979	0	0	0
T27	0	58	0	0
T28	0	821	0	0
T30	0	1181	0	0
T32	0	1030	0	0
T34	0	34	0	0
T63	0	1088	0	0
T64	0	5	0	0
T65	0	875	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T3 T7 T8 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T3 T7 T8 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T3 T7 T8 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T7,T9,T11
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T7,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417740699	3161543	0	0
DataKnown_AKnownEnable	417740699	417650903	0	0
DepthKnown_A	417740699	417650903	0	0
RvalidKnown_A	417740699	417650903	0	0
WreadyKnown_A	417740699	417650903	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	417740699	3161543	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	3161543	0	0
T3	1783	100	0	0
T4	1281	0	0	0
T5	1069	0	0	0
T6	69410	0	0	0
T7	96749	835	0	0
T8	13829	832	0	0
T9	53869	2588	0	0
T10	440049	0	0	0
T11	7176	838	0	0
T12	13983	1088	0	0
T13	0	832	0	0
T14	0	832	0	0
T25	0	100	0	0
T40	0	832	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	3161543	0	0
T3	1783	100	0	0
T4	1281	0	0	0
T5	1069	0	0	0
T6	69410	0	0	0
T7	96749	835	0	0
T8	13829	832	0	0
T9	53869	2588	0	0
T10	440049	0	0	0
T11	7176	838	0	0
T12	13983	1088	0	0
T13	0	832	0	0
T14	0	832	0	0
T25	0	100	0	0
T40	0	832	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        excluded               storage[0] <= wdata_i;
Exclude Annotation: VC_COV_UNR
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        0/1     ==>        assign rdata_int = storage_rdata;
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
TERNARY	138	1	1	100.00
IF	69	3	3	100.00
IF	123	2	1	50.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==> (Excluded)  

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	4	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	4	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417740699	0	0	0
DataKnown_AKnownEnable	417740699	417650903	0	0
DepthKnown_A	417740699	417650903	0	0
RvalidKnown_A	417740699	417650903	0	0
WreadyKnown_A	417740699	417650903	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	417740699	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	0	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	417650903	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	417740699	0	0	0