Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
3188 |
0 |
0 |
T108 |
16513 |
160 |
0 |
0 |
T109 |
2255 |
2 |
0 |
0 |
T110 |
7676 |
85 |
0 |
0 |
T111 |
4035 |
87 |
0 |
0 |
T112 |
65881 |
2 |
0 |
0 |
T113 |
54854 |
1 |
0 |
0 |
T114 |
27905 |
1 |
0 |
0 |
T116 |
7753 |
268 |
0 |
0 |
T123 |
10430 |
4 |
0 |
0 |
T124 |
5406 |
9 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1592 |
0 |
0 |
T112 |
65881 |
81 |
0 |
0 |
T122 |
15426 |
17 |
0 |
0 |
T123 |
10430 |
16 |
0 |
0 |
T127 |
6660 |
7 |
0 |
0 |
T149 |
6638 |
21 |
0 |
0 |
T150 |
19277 |
34 |
0 |
0 |
T155 |
20021 |
39 |
0 |
0 |
T156 |
102415 |
102 |
0 |
0 |
T157 |
7739 |
6 |
0 |
0 |
T158 |
9923 |
10 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1581 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T110 |
7676 |
1 |
0 |
0 |
T112 |
65881 |
62 |
0 |
0 |
T122 |
15426 |
28 |
0 |
0 |
T123 |
10430 |
15 |
0 |
0 |
T127 |
6660 |
2 |
0 |
0 |
T149 |
6638 |
20 |
0 |
0 |
T150 |
19277 |
36 |
0 |
0 |
T155 |
20021 |
71 |
0 |
0 |
T159 |
3320 |
10 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
2081 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T112 |
65881 |
137 |
0 |
0 |
T122 |
15426 |
31 |
0 |
0 |
T123 |
10430 |
16 |
0 |
0 |
T127 |
6660 |
4 |
0 |
0 |
T149 |
6638 |
16 |
0 |
0 |
T150 |
19277 |
76 |
0 |
0 |
T155 |
20021 |
36 |
0 |
0 |
T156 |
102415 |
227 |
0 |
0 |
T159 |
3320 |
8 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
9911 |
0 |
0 |
T93 |
3165 |
4 |
0 |
0 |
T112 |
65881 |
1130 |
0 |
0 |
T122 |
15426 |
24 |
0 |
0 |
T123 |
10430 |
91 |
0 |
0 |
T127 |
6660 |
11 |
0 |
0 |
T149 |
6638 |
10 |
0 |
0 |
T150 |
19277 |
25 |
0 |
0 |
T155 |
20021 |
94 |
0 |
0 |
T156 |
102415 |
1457 |
0 |
0 |
T159 |
3320 |
56 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
11322 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T112 |
65881 |
862 |
0 |
0 |
T122 |
15426 |
133 |
0 |
0 |
T123 |
10430 |
111 |
0 |
0 |
T127 |
6660 |
10 |
0 |
0 |
T149 |
6638 |
17 |
0 |
0 |
T150 |
19277 |
68 |
0 |
0 |
T155 |
20021 |
71 |
0 |
0 |
T156 |
102415 |
2140 |
0 |
0 |
T159 |
3320 |
75 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
10749 |
0 |
0 |
T93 |
3165 |
9 |
0 |
0 |
T112 |
65881 |
1188 |
0 |
0 |
T122 |
15426 |
235 |
0 |
0 |
T123 |
10430 |
82 |
0 |
0 |
T127 |
6660 |
129 |
0 |
0 |
T149 |
6638 |
31 |
0 |
0 |
T150 |
19277 |
77 |
0 |
0 |
T155 |
20021 |
59 |
0 |
0 |
T156 |
102415 |
2118 |
0 |
0 |
T157 |
7739 |
137 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
10705 |
0 |
0 |
T93 |
3165 |
9 |
0 |
0 |
T112 |
65881 |
1174 |
0 |
0 |
T122 |
15426 |
148 |
0 |
0 |
T123 |
10430 |
68 |
0 |
0 |
T127 |
6660 |
94 |
0 |
0 |
T149 |
6638 |
20 |
0 |
0 |
T150 |
19277 |
29 |
0 |
0 |
T155 |
20021 |
36 |
0 |
0 |
T156 |
102415 |
2019 |
0 |
0 |
T159 |
3320 |
73 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
9504 |
0 |
0 |
T93 |
3165 |
5 |
0 |
0 |
T112 |
65881 |
1280 |
0 |
0 |
T122 |
15426 |
123 |
0 |
0 |
T123 |
10430 |
84 |
0 |
0 |
T127 |
6660 |
7 |
0 |
0 |
T150 |
19277 |
91 |
0 |
0 |
T155 |
20021 |
36 |
0 |
0 |
T156 |
102415 |
1452 |
0 |
0 |
T157 |
7739 |
128 |
0 |
0 |
T158 |
9923 |
71 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
11534 |
0 |
0 |
T93 |
3165 |
7 |
0 |
0 |
T108 |
16513 |
2 |
0 |
0 |
T112 |
65881 |
1588 |
0 |
0 |
T122 |
15426 |
142 |
0 |
0 |
T123 |
10430 |
13 |
0 |
0 |
T127 |
6660 |
232 |
0 |
0 |
T149 |
6638 |
38 |
0 |
0 |
T150 |
19277 |
108 |
0 |
0 |
T155 |
20021 |
74 |
0 |
0 |
T159 |
3320 |
85 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
11072 |
0 |
0 |
T93 |
3165 |
7 |
0 |
0 |
T112 |
65881 |
1102 |
0 |
0 |
T122 |
15426 |
247 |
0 |
0 |
T123 |
10430 |
106 |
0 |
0 |
T127 |
6660 |
133 |
0 |
0 |
T150 |
19277 |
133 |
0 |
0 |
T155 |
20021 |
37 |
0 |
0 |
T156 |
102415 |
1645 |
0 |
0 |
T157 |
7739 |
147 |
0 |
0 |
T159 |
3320 |
7 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
11140 |
0 |
0 |
T93 |
3165 |
8 |
0 |
0 |
T112 |
65881 |
991 |
0 |
0 |
T122 |
15426 |
119 |
0 |
0 |
T123 |
10430 |
119 |
0 |
0 |
T127 |
6660 |
101 |
0 |
0 |
T149 |
6638 |
19 |
0 |
0 |
T150 |
19277 |
67 |
0 |
0 |
T155 |
20021 |
34 |
0 |
0 |
T156 |
102415 |
1992 |
0 |
0 |
T159 |
3320 |
61 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5290 |
0 |
0 |
T93 |
3165 |
8 |
0 |
0 |
T112 |
65881 |
740 |
0 |
0 |
T122 |
15426 |
143 |
0 |
0 |
T123 |
10430 |
53 |
0 |
0 |
T127 |
6660 |
14 |
0 |
0 |
T149 |
6638 |
1 |
0 |
0 |
T150 |
19277 |
62 |
0 |
0 |
T155 |
20021 |
95 |
0 |
0 |
T156 |
102415 |
826 |
0 |
0 |
T159 |
3320 |
15 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5533 |
0 |
0 |
T93 |
3165 |
10 |
0 |
0 |
T112 |
65881 |
519 |
0 |
0 |
T122 |
15426 |
51 |
0 |
0 |
T123 |
10430 |
36 |
0 |
0 |
T127 |
6660 |
5 |
0 |
0 |
T149 |
6638 |
9 |
0 |
0 |
T150 |
19277 |
68 |
0 |
0 |
T155 |
20021 |
37 |
0 |
0 |
T156 |
102415 |
973 |
0 |
0 |
T157 |
7739 |
3 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5385 |
0 |
0 |
T112 |
65881 |
594 |
0 |
0 |
T122 |
15426 |
127 |
0 |
0 |
T123 |
10430 |
14 |
0 |
0 |
T127 |
6660 |
11 |
0 |
0 |
T149 |
6638 |
10 |
0 |
0 |
T150 |
19277 |
82 |
0 |
0 |
T155 |
20021 |
45 |
0 |
0 |
T156 |
102415 |
765 |
0 |
0 |
T157 |
7739 |
68 |
0 |
0 |
T159 |
3320 |
1 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5545 |
0 |
0 |
T93 |
3165 |
4 |
0 |
0 |
T112 |
65881 |
469 |
0 |
0 |
T122 |
15426 |
108 |
0 |
0 |
T123 |
10430 |
22 |
0 |
0 |
T127 |
6660 |
49 |
0 |
0 |
T149 |
6638 |
8 |
0 |
0 |
T150 |
19277 |
103 |
0 |
0 |
T155 |
20021 |
45 |
0 |
0 |
T156 |
102415 |
1069 |
0 |
0 |
T157 |
7739 |
84 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5008 |
0 |
0 |
T93 |
3165 |
2 |
0 |
0 |
T112 |
65881 |
631 |
0 |
0 |
T122 |
15426 |
21 |
0 |
0 |
T123 |
10430 |
41 |
0 |
0 |
T127 |
6660 |
111 |
0 |
0 |
T149 |
6638 |
3 |
0 |
0 |
T150 |
19277 |
73 |
0 |
0 |
T155 |
20021 |
80 |
0 |
0 |
T156 |
102415 |
783 |
0 |
0 |
T159 |
3320 |
21 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5678 |
0 |
0 |
T93 |
3165 |
12 |
0 |
0 |
T112 |
65881 |
636 |
0 |
0 |
T122 |
15426 |
85 |
0 |
0 |
T123 |
10430 |
35 |
0 |
0 |
T127 |
6660 |
118 |
0 |
0 |
T150 |
19277 |
55 |
0 |
0 |
T155 |
20021 |
78 |
0 |
0 |
T156 |
102415 |
794 |
0 |
0 |
T157 |
7739 |
51 |
0 |
0 |
T158 |
9923 |
14 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5091 |
0 |
0 |
T93 |
3165 |
2 |
0 |
0 |
T112 |
65881 |
431 |
0 |
0 |
T122 |
15426 |
50 |
0 |
0 |
T123 |
10430 |
36 |
0 |
0 |
T127 |
6660 |
9 |
0 |
0 |
T149 |
6638 |
7 |
0 |
0 |
T150 |
19277 |
86 |
0 |
0 |
T155 |
20021 |
116 |
0 |
0 |
T156 |
102415 |
730 |
0 |
0 |
T159 |
3320 |
5 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5637 |
0 |
0 |
T112 |
65881 |
479 |
0 |
0 |
T122 |
15426 |
137 |
0 |
0 |
T123 |
10430 |
54 |
0 |
0 |
T127 |
6660 |
98 |
0 |
0 |
T149 |
6638 |
32 |
0 |
0 |
T150 |
19277 |
105 |
0 |
0 |
T155 |
20021 |
65 |
0 |
0 |
T156 |
102415 |
862 |
0 |
0 |
T157 |
7739 |
48 |
0 |
0 |
T159 |
3320 |
16 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5605 |
0 |
0 |
T112 |
65881 |
533 |
0 |
0 |
T122 |
15426 |
108 |
0 |
0 |
T123 |
10430 |
47 |
0 |
0 |
T127 |
6660 |
10 |
0 |
0 |
T149 |
6638 |
13 |
0 |
0 |
T150 |
19277 |
42 |
0 |
0 |
T155 |
20021 |
55 |
0 |
0 |
T156 |
102415 |
1026 |
0 |
0 |
T157 |
7739 |
49 |
0 |
0 |
T158 |
9923 |
29 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5158 |
0 |
0 |
T93 |
3165 |
2 |
0 |
0 |
T112 |
65881 |
657 |
0 |
0 |
T122 |
15426 |
104 |
0 |
0 |
T123 |
10430 |
73 |
0 |
0 |
T127 |
6660 |
1 |
0 |
0 |
T150 |
19277 |
60 |
0 |
0 |
T155 |
20021 |
32 |
0 |
0 |
T156 |
102415 |
949 |
0 |
0 |
T157 |
7739 |
70 |
0 |
0 |
T159 |
3320 |
6 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5286 |
0 |
0 |
T93 |
3165 |
5 |
0 |
0 |
T112 |
65881 |
631 |
0 |
0 |
T122 |
15426 |
100 |
0 |
0 |
T123 |
10430 |
7 |
0 |
0 |
T127 |
6660 |
4 |
0 |
0 |
T149 |
6638 |
20 |
0 |
0 |
T150 |
19277 |
91 |
0 |
0 |
T155 |
20021 |
43 |
0 |
0 |
T156 |
102415 |
589 |
0 |
0 |
T157 |
7739 |
68 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
4939 |
0 |
0 |
T93 |
3165 |
4 |
0 |
0 |
T112 |
65881 |
626 |
0 |
0 |
T122 |
15426 |
68 |
0 |
0 |
T123 |
10430 |
32 |
0 |
0 |
T127 |
6660 |
49 |
0 |
0 |
T149 |
6638 |
34 |
0 |
0 |
T150 |
19277 |
59 |
0 |
0 |
T155 |
20021 |
61 |
0 |
0 |
T156 |
102415 |
1015 |
0 |
0 |
T157 |
7739 |
62 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5394 |
0 |
0 |
T93 |
3165 |
8 |
0 |
0 |
T112 |
65881 |
584 |
0 |
0 |
T122 |
15426 |
126 |
0 |
0 |
T123 |
10430 |
31 |
0 |
0 |
T127 |
6660 |
47 |
0 |
0 |
T149 |
6638 |
10 |
0 |
0 |
T150 |
19277 |
101 |
0 |
0 |
T155 |
20021 |
70 |
0 |
0 |
T156 |
102415 |
709 |
0 |
0 |
T159 |
3320 |
7 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
4878 |
0 |
0 |
T112 |
65881 |
423 |
0 |
0 |
T122 |
15426 |
105 |
0 |
0 |
T123 |
10430 |
12 |
0 |
0 |
T127 |
6660 |
9 |
0 |
0 |
T149 |
6638 |
4 |
0 |
0 |
T150 |
19277 |
91 |
0 |
0 |
T155 |
20021 |
134 |
0 |
0 |
T156 |
102415 |
762 |
0 |
0 |
T157 |
7739 |
117 |
0 |
0 |
T159 |
3320 |
17 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
4913 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T112 |
65881 |
591 |
0 |
0 |
T122 |
15426 |
12 |
0 |
0 |
T123 |
10430 |
40 |
0 |
0 |
T127 |
6660 |
45 |
0 |
0 |
T149 |
6638 |
29 |
0 |
0 |
T150 |
19277 |
66 |
0 |
0 |
T155 |
20021 |
69 |
0 |
0 |
T156 |
102415 |
804 |
0 |
0 |
T157 |
7739 |
45 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5223 |
0 |
0 |
T93 |
3165 |
5 |
0 |
0 |
T112 |
65881 |
511 |
0 |
0 |
T122 |
15426 |
71 |
0 |
0 |
T123 |
10430 |
19 |
0 |
0 |
T127 |
6660 |
36 |
0 |
0 |
T149 |
6638 |
9 |
0 |
0 |
T150 |
19277 |
86 |
0 |
0 |
T155 |
20021 |
88 |
0 |
0 |
T156 |
102415 |
638 |
0 |
0 |
T157 |
7739 |
48 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
4972 |
0 |
0 |
T112 |
65881 |
544 |
0 |
0 |
T117 |
13276 |
12 |
0 |
0 |
T122 |
15426 |
135 |
0 |
0 |
T123 |
10430 |
7 |
0 |
0 |
T127 |
6660 |
3 |
0 |
0 |
T149 |
6638 |
26 |
0 |
0 |
T150 |
19277 |
34 |
0 |
0 |
T155 |
20021 |
43 |
0 |
0 |
T156 |
102415 |
983 |
0 |
0 |
T159 |
3320 |
26 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5246 |
0 |
0 |
T93 |
3165 |
2 |
0 |
0 |
T112 |
65881 |
409 |
0 |
0 |
T122 |
15426 |
44 |
0 |
0 |
T123 |
10430 |
71 |
0 |
0 |
T127 |
6660 |
45 |
0 |
0 |
T150 |
19277 |
60 |
0 |
0 |
T155 |
20021 |
102 |
0 |
0 |
T156 |
102415 |
885 |
0 |
0 |
T157 |
7739 |
53 |
0 |
0 |
T158 |
9923 |
53 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5059 |
0 |
0 |
T93 |
3165 |
4 |
0 |
0 |
T112 |
65881 |
712 |
0 |
0 |
T122 |
15426 |
63 |
0 |
0 |
T123 |
10430 |
13 |
0 |
0 |
T127 |
6660 |
56 |
0 |
0 |
T150 |
19277 |
104 |
0 |
0 |
T155 |
20021 |
113 |
0 |
0 |
T156 |
102415 |
665 |
0 |
0 |
T157 |
7739 |
5 |
0 |
0 |
T159 |
3320 |
16 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5465 |
0 |
0 |
T93 |
3165 |
3 |
0 |
0 |
T112 |
65881 |
485 |
0 |
0 |
T122 |
15426 |
64 |
0 |
0 |
T123 |
10430 |
5 |
0 |
0 |
T127 |
6660 |
35 |
0 |
0 |
T149 |
6638 |
18 |
0 |
0 |
T150 |
19277 |
60 |
0 |
0 |
T155 |
20021 |
90 |
0 |
0 |
T156 |
102415 |
846 |
0 |
0 |
T159 |
3320 |
2 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5597 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T112 |
65881 |
742 |
0 |
0 |
T122 |
15426 |
101 |
0 |
0 |
T123 |
10430 |
48 |
0 |
0 |
T127 |
6660 |
5 |
0 |
0 |
T149 |
6638 |
7 |
0 |
0 |
T150 |
19277 |
28 |
0 |
0 |
T155 |
20021 |
74 |
0 |
0 |
T156 |
102415 |
899 |
0 |
0 |
T157 |
7739 |
66 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
4581 |
0 |
0 |
T93 |
3165 |
10 |
0 |
0 |
T112 |
65881 |
433 |
0 |
0 |
T122 |
15426 |
193 |
0 |
0 |
T123 |
10430 |
4 |
0 |
0 |
T127 |
6660 |
56 |
0 |
0 |
T149 |
6638 |
9 |
0 |
0 |
T150 |
19277 |
96 |
0 |
0 |
T155 |
20021 |
102 |
0 |
0 |
T156 |
102415 |
753 |
0 |
0 |
T159 |
3320 |
8 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5155 |
0 |
0 |
T112 |
65881 |
377 |
0 |
0 |
T122 |
15426 |
115 |
0 |
0 |
T123 |
10430 |
63 |
0 |
0 |
T127 |
6660 |
102 |
0 |
0 |
T149 |
6638 |
3 |
0 |
0 |
T150 |
19277 |
54 |
0 |
0 |
T155 |
20021 |
82 |
0 |
0 |
T156 |
102415 |
679 |
0 |
0 |
T157 |
7739 |
47 |
0 |
0 |
T159 |
3320 |
23 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
5242 |
0 |
0 |
T112 |
65881 |
696 |
0 |
0 |
T122 |
15426 |
125 |
0 |
0 |
T123 |
10430 |
24 |
0 |
0 |
T127 |
6660 |
47 |
0 |
0 |
T149 |
6638 |
2 |
0 |
0 |
T150 |
19277 |
57 |
0 |
0 |
T155 |
20021 |
26 |
0 |
0 |
T156 |
102415 |
841 |
0 |
0 |
T157 |
7739 |
90 |
0 |
0 |
T159 |
3320 |
14 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1921 |
0 |
0 |
T112 |
65881 |
80 |
0 |
0 |
T122 |
15426 |
31 |
0 |
0 |
T123 |
10430 |
7 |
0 |
0 |
T127 |
6660 |
13 |
0 |
0 |
T149 |
6638 |
11 |
0 |
0 |
T150 |
19277 |
83 |
0 |
0 |
T155 |
20021 |
56 |
0 |
0 |
T156 |
102415 |
210 |
0 |
0 |
T157 |
7739 |
18 |
0 |
0 |
T158 |
9923 |
11 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1905 |
0 |
0 |
T112 |
65881 |
122 |
0 |
0 |
T122 |
15426 |
10 |
0 |
0 |
T123 |
10430 |
10 |
0 |
0 |
T127 |
6660 |
6 |
0 |
0 |
T149 |
6638 |
24 |
0 |
0 |
T150 |
19277 |
85 |
0 |
0 |
T155 |
20021 |
44 |
0 |
0 |
T156 |
102415 |
221 |
0 |
0 |
T157 |
7739 |
19 |
0 |
0 |
T158 |
9923 |
4 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1957 |
0 |
0 |
T93 |
3165 |
5 |
0 |
0 |
T112 |
65881 |
102 |
0 |
0 |
T117 |
13276 |
1 |
0 |
0 |
T122 |
15426 |
35 |
0 |
0 |
T123 |
10430 |
21 |
0 |
0 |
T127 |
6660 |
17 |
0 |
0 |
T149 |
6638 |
9 |
0 |
0 |
T150 |
19277 |
104 |
0 |
0 |
T155 |
20021 |
68 |
0 |
0 |
T156 |
102415 |
134 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1869 |
0 |
0 |
T93 |
3165 |
6 |
0 |
0 |
T112 |
65881 |
124 |
0 |
0 |
T122 |
15426 |
34 |
0 |
0 |
T123 |
10430 |
12 |
0 |
0 |
T127 |
6660 |
2 |
0 |
0 |
T149 |
6638 |
10 |
0 |
0 |
T150 |
19277 |
57 |
0 |
0 |
T155 |
20021 |
85 |
0 |
0 |
T156 |
102415 |
127 |
0 |
0 |
T159 |
3320 |
1 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
2611 |
0 |
0 |
T93 |
3165 |
2 |
0 |
0 |
T112 |
65881 |
212 |
0 |
0 |
T122 |
15426 |
44 |
0 |
0 |
T123 |
10430 |
12 |
0 |
0 |
T127 |
6660 |
9 |
0 |
0 |
T150 |
19277 |
62 |
0 |
0 |
T155 |
20021 |
61 |
0 |
0 |
T156 |
102415 |
264 |
0 |
0 |
T157 |
7739 |
29 |
0 |
0 |
T158 |
9923 |
23 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
4542 |
0 |
0 |
T36 |
100134 |
10 |
0 |
0 |
T39 |
0 |
21 |
0 |
0 |
T66 |
0 |
113 |
0 |
0 |
T97 |
50983 |
0 |
0 |
0 |
T145 |
113502 |
0 |
0 |
0 |
T146 |
0 |
12 |
0 |
0 |
T160 |
0 |
32 |
0 |
0 |
T161 |
0 |
74 |
0 |
0 |
T162 |
0 |
25 |
0 |
0 |
T163 |
0 |
47 |
0 |
0 |
T164 |
0 |
11 |
0 |
0 |
T165 |
0 |
37 |
0 |
0 |
T166 |
71973 |
0 |
0 |
0 |
T167 |
6167 |
0 |
0 |
0 |
T168 |
11249 |
0 |
0 |
0 |
T169 |
366528 |
0 |
0 |
0 |
T170 |
408312 |
0 |
0 |
0 |
T171 |
1031 |
0 |
0 |
0 |
T172 |
1549 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1957 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T112 |
65881 |
115 |
0 |
0 |
T122 |
15426 |
44 |
0 |
0 |
T123 |
10430 |
10 |
0 |
0 |
T127 |
6660 |
14 |
0 |
0 |
T149 |
6638 |
23 |
0 |
0 |
T150 |
19277 |
64 |
0 |
0 |
T155 |
20021 |
46 |
0 |
0 |
T156 |
102415 |
166 |
0 |
0 |
T157 |
7739 |
26 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1984 |
0 |
0 |
T93 |
3165 |
8 |
0 |
0 |
T112 |
65881 |
88 |
0 |
0 |
T122 |
15426 |
34 |
0 |
0 |
T123 |
10430 |
12 |
0 |
0 |
T127 |
6660 |
8 |
0 |
0 |
T150 |
19277 |
37 |
0 |
0 |
T155 |
20021 |
78 |
0 |
0 |
T156 |
102415 |
192 |
0 |
0 |
T157 |
7739 |
1 |
0 |
0 |
T159 |
3320 |
1 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1615 |
0 |
0 |
T93 |
3165 |
8 |
0 |
0 |
T112 |
65881 |
82 |
0 |
0 |
T122 |
15426 |
14 |
0 |
0 |
T123 |
10430 |
10 |
0 |
0 |
T127 |
6660 |
6 |
0 |
0 |
T150 |
19277 |
66 |
0 |
0 |
T155 |
20021 |
71 |
0 |
0 |
T156 |
102415 |
111 |
0 |
0 |
T157 |
7739 |
4 |
0 |
0 |
T158 |
9923 |
1 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1600 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T108 |
16513 |
1 |
0 |
0 |
T112 |
65881 |
88 |
0 |
0 |
T122 |
15426 |
8 |
0 |
0 |
T123 |
10430 |
11 |
0 |
0 |
T127 |
6660 |
13 |
0 |
0 |
T150 |
19277 |
61 |
0 |
0 |
T155 |
20021 |
48 |
0 |
0 |
T156 |
102415 |
115 |
0 |
0 |
T157 |
7739 |
9 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1688 |
0 |
0 |
T93 |
3165 |
9 |
0 |
0 |
T112 |
65881 |
87 |
0 |
0 |
T122 |
15426 |
14 |
0 |
0 |
T123 |
10430 |
4 |
0 |
0 |
T127 |
6660 |
5 |
0 |
0 |
T149 |
6638 |
9 |
0 |
0 |
T150 |
19277 |
80 |
0 |
0 |
T155 |
20021 |
60 |
0 |
0 |
T156 |
102415 |
142 |
0 |
0 |
T157 |
7739 |
14 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1724 |
0 |
0 |
T93 |
3165 |
7 |
0 |
0 |
T112 |
65881 |
97 |
0 |
0 |
T122 |
15426 |
33 |
0 |
0 |
T123 |
10430 |
12 |
0 |
0 |
T127 |
6660 |
12 |
0 |
0 |
T149 |
6638 |
2 |
0 |
0 |
T150 |
19277 |
34 |
0 |
0 |
T155 |
20021 |
69 |
0 |
0 |
T156 |
102415 |
124 |
0 |
0 |
T159 |
3320 |
7 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
2520 |
0 |
0 |
T112 |
65881 |
164 |
0 |
0 |
T122 |
15426 |
49 |
0 |
0 |
T123 |
10430 |
20 |
0 |
0 |
T127 |
6660 |
30 |
0 |
0 |
T149 |
6638 |
3 |
0 |
0 |
T150 |
19277 |
91 |
0 |
0 |
T155 |
20021 |
76 |
0 |
0 |
T156 |
102415 |
254 |
0 |
0 |
T157 |
7739 |
13 |
0 |
0 |
T158 |
9923 |
16 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1741 |
0 |
0 |
T112 |
65881 |
103 |
0 |
0 |
T122 |
15426 |
11 |
0 |
0 |
T123 |
10430 |
11 |
0 |
0 |
T127 |
6660 |
10 |
0 |
0 |
T149 |
6638 |
12 |
0 |
0 |
T150 |
19277 |
37 |
0 |
0 |
T155 |
20021 |
72 |
0 |
0 |
T156 |
102415 |
109 |
0 |
0 |
T157 |
7739 |
10 |
0 |
0 |
T158 |
9923 |
4 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
2805 |
0 |
0 |
T93 |
3165 |
5 |
0 |
0 |
T112 |
65881 |
206 |
0 |
0 |
T122 |
15426 |
79 |
0 |
0 |
T123 |
10430 |
17 |
0 |
0 |
T127 |
6660 |
17 |
0 |
0 |
T149 |
6638 |
5 |
0 |
0 |
T150 |
19277 |
46 |
0 |
0 |
T155 |
20021 |
68 |
0 |
0 |
T156 |
102415 |
339 |
0 |
0 |
T157 |
7739 |
28 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1976 |
0 |
0 |
T93 |
3165 |
8 |
0 |
0 |
T112 |
65881 |
113 |
0 |
0 |
T122 |
15426 |
14 |
0 |
0 |
T123 |
10430 |
17 |
0 |
0 |
T127 |
6660 |
16 |
0 |
0 |
T149 |
6638 |
25 |
0 |
0 |
T150 |
19277 |
37 |
0 |
0 |
T155 |
20021 |
56 |
0 |
0 |
T156 |
102415 |
180 |
0 |
0 |
T159 |
3320 |
3 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1610 |
0 |
0 |
T93 |
3165 |
17 |
0 |
0 |
T112 |
65881 |
60 |
0 |
0 |
T122 |
15426 |
12 |
0 |
0 |
T123 |
10430 |
6 |
0 |
0 |
T127 |
6660 |
13 |
0 |
0 |
T149 |
6638 |
2 |
0 |
0 |
T150 |
19277 |
66 |
0 |
0 |
T155 |
20021 |
38 |
0 |
0 |
T156 |
102415 |
114 |
0 |
0 |
T159 |
3320 |
6 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1750 |
0 |
0 |
T112 |
65881 |
58 |
0 |
0 |
T122 |
15426 |
17 |
0 |
0 |
T123 |
10430 |
3 |
0 |
0 |
T127 |
6660 |
10 |
0 |
0 |
T149 |
6638 |
3 |
0 |
0 |
T150 |
19277 |
81 |
0 |
0 |
T155 |
20021 |
99 |
0 |
0 |
T156 |
102415 |
156 |
0 |
0 |
T157 |
7739 |
11 |
0 |
0 |
T158 |
9923 |
9 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1756 |
0 |
0 |
T112 |
65881 |
99 |
0 |
0 |
T122 |
15426 |
29 |
0 |
0 |
T123 |
10430 |
17 |
0 |
0 |
T127 |
6660 |
11 |
0 |
0 |
T149 |
6638 |
3 |
0 |
0 |
T150 |
19277 |
53 |
0 |
0 |
T155 |
20021 |
43 |
0 |
0 |
T156 |
102415 |
132 |
0 |
0 |
T157 |
7739 |
10 |
0 |
0 |
T159 |
3320 |
6 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1708 |
0 |
0 |
T93 |
3165 |
1 |
0 |
0 |
T112 |
65881 |
81 |
0 |
0 |
T122 |
15426 |
17 |
0 |
0 |
T123 |
10430 |
12 |
0 |
0 |
T127 |
6660 |
4 |
0 |
0 |
T149 |
6638 |
13 |
0 |
0 |
T150 |
19277 |
73 |
0 |
0 |
T155 |
20021 |
70 |
0 |
0 |
T156 |
102415 |
132 |
0 |
0 |
T157 |
7739 |
8 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1658 |
0 |
0 |
T93 |
3165 |
12 |
0 |
0 |
T112 |
65881 |
84 |
0 |
0 |
T122 |
15426 |
30 |
0 |
0 |
T123 |
10430 |
10 |
0 |
0 |
T127 |
6660 |
14 |
0 |
0 |
T149 |
6638 |
16 |
0 |
0 |
T150 |
19277 |
62 |
0 |
0 |
T155 |
20021 |
37 |
0 |
0 |
T156 |
102415 |
125 |
0 |
0 |
T157 |
7739 |
8 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419996797 |
1790 |
0 |
0 |
T93 |
3165 |
9 |
0 |
0 |
T112 |
65881 |
80 |
0 |
0 |
T122 |
15426 |
30 |
0 |
0 |
T127 |
6660 |
7 |
0 |
0 |
T149 |
6638 |
18 |
0 |
0 |
T150 |
19277 |
87 |
0 |
0 |
T155 |
20021 |
66 |
0 |
0 |
T156 |
102415 |
99 |
0 |
0 |
T157 |
7739 |
5 |
0 |
0 |
T159 |
3320 |
5 |
0 |
0 |