3df77bec1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.600m | 13.113ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 16.520us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 38.220us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 167.042us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 18.682us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 45.522us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 38.220us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 18.682us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 17.422us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 28.912us | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | performance | spi_host_performance | 5.000s | 29.609us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.683m | 5.030ms | 49 | 50 | 98.00 |
| spi_host_error_cmd | 4.000s | 15.353us | 50 | 50 | 100.00 | ||
| spi_host_event | 19.733m | 244.949ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.117m | 59.924ms | 49 | 50 | 98.00 |
| V2 | speed | spi_host_speed | 5.117m | 59.924ms | 49 | 50 | 98.00 |
| V2 | chip_select_timing | spi_host_speed | 5.117m | 59.924ms | 49 | 50 | 98.00 |
| V2 | sw_reset | spi_host_sw_reset | 7.833m | 10.986ms | 44 | 50 | 88.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 1.707ms | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.117m | 59.924ms | 49 | 50 | 98.00 |
| V2 | full_cycle | spi_host_speed | 5.117m | 59.924ms | 49 | 50 | 98.00 |
| V2 | duplex | spi_host_smoke | 9.600m | 13.113ms | 48 | 50 | 96.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.600m | 13.113ms | 48 | 50 | 96.00 |
| V2 | stress_all | spi_host_stress_all | 7.500m | 10.140ms | 45 | 50 | 90.00 |
| V2 | spien | spi_host_spien | 6.683m | 8.665ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 10.933m | 31.254ms | 49 | 50 | 98.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 1.050m | 5.754ms | 49 | 50 | 98.00 |
| V2 | alert_test | spi_host_alert_test | 4.000s | 41.349us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 4.000s | 49.989us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 441.169us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 441.169us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 16.520us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 38.220us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 18.682us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 31.780us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 16.520us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 38.220us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 18.682us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 31.780us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 675 | 690 | 97.83 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 75.671us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 219.358us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 75.671us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 813 | 830 | 97.95 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.09 | 98.19 | 95.98 | 99.74 | 96.34 | 95.70 | 100.00 | 98.60 | 91.29 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 8 failures:
Test spi_host_smoke has 2 failures.
1.spi_host_smoke.1101768896
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 118219329189 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbf896394) == 0x0
UVM_INFO @ 118219329189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_smoke.4028928987
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_smoke/latest/run.log
UVM_FATAL @ 191869160341 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd47d7714) == 0x0
UVM_INFO @ 191869160341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 4 failures.
5.spi_host_stress_all.17159203
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10313193886 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc353b514) == 0x0
UVM_INFO @ 10313193886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_stress_all.184818184
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 13454927864 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9c71c714) == 0x0
UVM_INFO @ 13454927864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_idlecsbactive has 1 failures.
7.spi_host_idlecsbactive.1057459732
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10055920936 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xda110654) == 0x0
UVM_INFO @ 10055920936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_overflow_underflow has 1 failures.
16.spi_host_overflow_underflow.3142774212
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 34914816787 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6b86f854) == 0x0
UVM_INFO @ 34914816787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 4 failures:
Test spi_host_stress_all has 1 failures.
14.spi_host_stress_all.2124023290
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10140419473 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa4ddbed4) == 0x0
UVM_INFO @ 10140419473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 3 failures.
21.spi_host_sw_reset.3114659678
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10000858711 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbb7f26d4) == 0x0
UVM_INFO @ 10000858711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_sw_reset.2836160424
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 13131200457 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4cd8f914) == 0x0
UVM_INFO @ 13131200457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 3 failures:
6.spi_host_sw_reset.2906269712
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10119480180 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe4d740d4) == 0x0
UVM_INFO @ 10119480180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_sw_reset.2103695937
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10505774380 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xac28c654) == 0x0
UVM_INFO @ 10505774380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
17.spi_host_status_stall.1983960191
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
36.spi_host_speed.3643874652
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_speed/latest/run.log
UVM_FATAL @ 83387089068 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa8f6b0d4) == 0x0
UVM_INFO @ 83387089068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---