SPI_HOST Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.900m	12.378ms	45	50	90.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	48.461us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	46.605us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	318.518us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	160.424us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	272.528us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	46.605us	20	20	100.00
		spi_host_csr_aliasing	4.000s	160.424us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	18.729us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	20.603us	5	5	100.00
V1		TOTAL			110	115	95.65
V2	performance	spi_host_performance	4.000s	32.372us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.600m	41.822ms	48	50	96.00
		spi_host_error_cmd	3.000s	17.249us	50	50	100.00
		spi_host_event	23.517m	34.862ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.567m	109.569ms	49	50	98.00
V2	speed	spi_host_speed	5.567m	109.569ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	5.567m	109.569ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	6.017m	19.526ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	1.244ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.567m	109.569ms	49	50	98.00
V2	full_cycle	spi_host_speed	5.567m	109.569ms	49	50	98.00
V2	duplex	spi_host_smoke	9.900m	12.378ms	45	50	90.00
V2	tx_rx_only	spi_host_smoke	9.900m	12.378ms	45	50	90.00
V2	stress_all	spi_host_stress_all	4.883m	9.586ms	50	50	100.00
V2	spien	spi_host_spien	5.467m	7.175ms	50	50	100.00
V2	stall	spi_host_status_stall	8.633m	24.839ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	48.000s	4.780ms	49	50	98.00
V2	alert_test	spi_host_alert_test	3.000s	17.326us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	43.573us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	37.659us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	37.659us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	48.461us	5	5	100.00
		spi_host_csr_rw	3.000s	46.605us	20	20	100.00
		spi_host_csr_aliasing	4.000s	160.424us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	54.049us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	48.461us	5	5	100.00
		spi_host_csr_rw	3.000s	46.605us	20	20	100.00
		spi_host_csr_aliasing	4.000s	160.424us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	54.049us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	53.883us	20	20	100.00
		spi_host_sec_cm	2.000s	283.449us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	53.883us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			821	830	98.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.09	98.13	95.98	99.73	96.70	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
- Test spi_host_overflow_underflow has 2 failures.
  - 5.spi_host_overflow_underflow.66375832953530570887674846023876267210279437295208766615006031480251702168679
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 41821806416 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb5d56854) == 0x0
  UVM_INFO @ 41821806416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.spi_host_overflow_underflow.14405676851881339336697029398059776824768663049081131994229441028055202664182
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 48940978089 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfe147f94) == 0x0
  UVM_INFO @ 48940978089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 3 failures.
  - 9.spi_host_smoke.8567107361713014177155089583780145764064231316105996265493737587243009783046
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 89229049205 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4dbd6e14) == 0x0
  UVM_INFO @ 89229049205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.spi_host_smoke.31589774087529201797573587887650353920866569825132462567184927605552740982614
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 105806849017 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6d790f94) == 0x0
  UVM_INFO @ 105806849017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_speed has 1 failures.
  - 16.spi_host_speed.1449164841189550891126675850862197970776510456563455751240446588887328214177
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 109569066816 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1c08d54) == 0x0
  UVM_INFO @ 109569066816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_idlecsbactive has 1 failures.
  - 23.spi_host_idlecsbactive.30780557648875561126772156980646898016548050229229531867665407890151275997024
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10084087769 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x35eed054) == 0x0
  UVM_INFO @ 10084087769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 4.spi_host_smoke.12161294589223424326784046181246984190656781006296969428900163413462617300196
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 13.spi_host_smoke.37235869863397470151028569163960057637676257209788773703727746290018900663920
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 98660781974 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x793e2614) == 0x0
  UVM_INFO @ 98660781974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0dd29ab736`