Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2618250	1			T1	1591		T3	1591		T10	4115
auto[1]	10324400	1			T1	351		T3	351		T8	4275
auto[2]	1955900	1			T1	1183		T3	1183		T10	2861
auto[3]	9765450	1			T1	185		T3	185		T8	4513

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15360350	1			T1	2632		T3	2632		T8	8788
auto[1]	2327700	1			T1	361		T3	361		T9	5716
auto[2]	2167050	1			T1	276		T3	276		T9	5560
auto[3]	4808900	1			T1	41		T3	41		T9	608

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6444800

1

T1

3310

T3

3310

T8

8788

auto[1]

18219200

1

T9

2

T10

2

T12

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	520150	1			T1	1321		T3	1321		T11	2089
auto[0]	auto[0]	auto[1]	54600	1			T1	134		T3	134		T10	30
auto[0]	auto[0]	auto[2]	57300	1			T1	124		T3	124		T10	31
auto[0]	auto[0]	auto[3]	220950	1			T1	12		T3	12		T10	4052
auto[0]	auto[1]	auto[0]	1878500	1			T1	201		T3	201		T8	4275
auto[0]	auto[1]	auto[1]	222200	1			T1	130		T3	130		T9	2717
auto[0]	auto[1]	auto[2]	185800	1			T1	12		T3	12		T9	2845
auto[0]	auto[1]	auto[3]	230350	1			T1	8		T3	8		T9	317
auto[0]	auto[2]	auto[0]	443950	1			T1	1016		T3	1016		T11	1453
auto[0]	auto[2]	auto[1]	62900	1			T1	92		T3	92		T10	328
auto[0]	auto[2]	auto[2]	32050	1			T1	66		T3	66		T10	16
auto[0]	auto[2]	auto[3]	137000	1			T1	9		T3	9		T10	2517
auto[0]	auto[3]	auto[0]	1842700	1			T1	94		T3	94		T8	4513
auto[0]	auto[3]	auto[1]	188650	1			T1	5		T3	5		T9	2998
auto[0]	auto[3]	auto[2]	214950	1			T1	74		T3	74		T9	2715
auto[0]	auto[3]	auto[3]	152750	1			T1	12		T3	12		T9	291
auto[1]	auto[0]	auto[0]	59450	1			T88	1189		T93	1189		T94	1189
auto[1]	auto[0]	auto[1]	264650	1			T88	5293		T93	5293		T94	5293
auto[1]	auto[0]	auto[2]	264350	1			T88	5287		T93	5287		T94	5287
auto[1]	auto[0]	auto[3]	1176800	1			T10	2		T16	1		T88	23533
auto[1]	auto[1]	auto[0]	5270850	1			T18	105219		T88	198		T90	105219
auto[1]	auto[1]	auto[1]	731300	1			T18	9337		T88	5289		T90	9337
auto[1]	auto[1]	auto[2]	570450	1			T18	10544		T88	865		T90	10544
auto[1]	auto[1]	auto[3]	1234950	1			T18	900		T88	23799		T90	900
auto[1]	auto[2]	auto[0]	55750	1			T12	1		T88	1114		T105	1
auto[1]	auto[2]	auto[1]	246700	1			T88	4934		T93	4934		T94	4934
auto[1]	auto[2]	auto[2]	180150	1			T12	1		T88	3602		T105	1
auto[1]	auto[2]	auto[3]	797400	1			T88	15948		T93	15948		T94	15948
auto[1]	auto[3]	auto[0]	5289000	1			T9	1		T18	105662		T88	117
auto[1]	auto[3]	auto[1]	556700	1			T9	1		T18	10615		T88	518
auto[1]	auto[3]	auto[2]	662000	1			T18	9645		T88	3595		T90	9645
auto[1]	auto[3]	auto[3]	858700	1			T18	919		T88	16255		T90	919