Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	100.00	95.12	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1386028885	66430	0	0
ctrl_regwen_rd_A	1386028885	7810	0	0
exec_rd_A	1386028885	6810	0	0
exec_regwen_rd_A	1386028885	7675	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1386028885	66430	0	0
T2	34962	1169	0	0
T3	111517	0	0	0
T7	34962	1169	0	0
T8	75205	0	0	0
T9	754166	0	0	0
T10	266045	0	0	0
T11	177593	0	0	0
T12	160895	0	0	0
T13	103295	0	0	0
T14	55344	0	0	0
T29	0	1169	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	7	0	0
T51	0	7	0	0
T52	0	7	0	0
T53	0	2	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1386028885	7810	0	0
T2	34962	103	0	0
T3	111517	0	0	0
T7	34962	103	0	0
T8	75205	0	0	0
T9	754166	0	0	0
T10	266045	0	0	0
T11	177593	0	0	0
T12	160895	0	0	0
T13	103295	0	0	0
T14	55344	0	0	0
T29	0	103	0	0
T30	0	21	0	0
T31	0	20	0	0
T32	0	15	0	0
T47	0	11	0	0
T50	0	5	0	0
T51	0	5	0	0
T64	0	21	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1386028885	6810	0	0
T2	34962	82	0	0
T3	111517	0	0	0
T7	34962	82	0	0
T8	75205	0	0	0
T9	754166	0	0	0
T10	266045	0	0	0
T11	177593	0	0	0
T12	160895	0	0	0
T13	103295	0	0	0
T14	55344	0	0	0
T29	0	82	0	0
T30	0	2	0	0
T31	0	13	0	0
T32	0	2	0	0
T47	0	34	0	0
T50	0	6	0	0
T51	0	6	0	0
T64	0	2	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1386028885	7675	0	0
T2	34962	104	0	0
T3	111517	0	0	0
T7	34962	104	0	0
T8	75205	0	0	0
T9	754166	0	0	0
T10	266045	0	0	0
T11	177593	0	0	0
T12	160895	0	0	0
T13	103295	0	0	0
T14	55344	0	0	0
T29	0	104	0	0
T30	0	13	0	0
T31	0	14	0	0
T32	0	4	0	0
T47	0	46	0	0
T50	0	7	0	0
T51	0	7	0	0
T64	0	13	0	0