T277 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1015360963 |
|
|
Dec 20 01:06:55 PM PST 23 |
Dec 20 01:09:27 PM PST 23 |
2638437138 ps |
T278 |
/workspace/coverage/default/30.sram_ctrl_regwen.3035138778 |
|
|
Dec 20 01:05:59 PM PST 23 |
Dec 20 01:13:31 PM PST 23 |
14553826002 ps |
T279 |
/workspace/coverage/default/23.sram_ctrl_stress_all.3238657206 |
|
|
Dec 20 01:05:50 PM PST 23 |
Dec 20 02:34:18 PM PST 23 |
306059115434 ps |
T280 |
/workspace/coverage/default/3.sram_ctrl_bijection.3620634407 |
|
|
Dec 20 01:05:11 PM PST 23 |
Dec 20 01:22:18 PM PST 23 |
15223180563 ps |
T281 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3254105164 |
|
|
Dec 20 01:06:04 PM PST 23 |
Dec 20 01:08:46 PM PST 23 |
822700362 ps |
T128 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1018689589 |
|
|
Dec 20 01:05:47 PM PST 23 |
Dec 20 01:13:12 PM PST 23 |
69736436156 ps |
T282 |
/workspace/coverage/default/31.sram_ctrl_executable.1395029973 |
|
|
Dec 20 01:06:07 PM PST 23 |
Dec 20 01:21:22 PM PST 23 |
20321687440 ps |
T283 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3522918912 |
|
|
Dec 20 01:06:09 PM PST 23 |
Dec 20 01:06:24 PM PST 23 |
343996071 ps |
T116 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1882979349 |
|
|
Dec 20 01:06:43 PM PST 23 |
Dec 20 01:07:44 PM PST 23 |
2607961349 ps |
T284 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.578965633 |
|
|
Dec 20 01:05:39 PM PST 23 |
Dec 20 01:12:39 PM PST 23 |
21360518648 ps |
T117 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.921665849 |
|
|
Dec 20 01:05:00 PM PST 23 |
Dec 20 01:05:54 PM PST 23 |
5322935094 ps |
T285 |
/workspace/coverage/default/18.sram_ctrl_smoke.3257709788 |
|
|
Dec 20 01:05:48 PM PST 23 |
Dec 20 01:08:03 PM PST 23 |
2115770495 ps |
T30 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2442351130 |
|
|
Dec 20 01:06:57 PM PST 23 |
Dec 20 01:09:45 PM PST 23 |
50627797595 ps |
T286 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2094994615 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:14:30 PM PST 23 |
55725567841 ps |
T287 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.51460135 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:15:18 PM PST 23 |
25272978087 ps |
T288 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.511852295 |
|
|
Dec 20 01:05:38 PM PST 23 |
Dec 20 01:09:48 PM PST 23 |
9384802972 ps |
T289 |
/workspace/coverage/default/25.sram_ctrl_smoke.3583378687 |
|
|
Dec 20 01:05:44 PM PST 23 |
Dec 20 01:06:24 PM PST 23 |
5292946287 ps |
T290 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2457434178 |
|
|
Dec 20 01:06:09 PM PST 23 |
Dec 20 01:06:50 PM PST 23 |
2805415143 ps |
T291 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3572147017 |
|
|
Dec 20 01:05:13 PM PST 23 |
Dec 20 01:16:47 PM PST 23 |
23774732978 ps |
T292 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2417274145 |
|
|
Dec 20 01:05:23 PM PST 23 |
Dec 20 01:14:12 PM PST 23 |
41175447717 ps |
T293 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2052829614 |
|
|
Dec 20 01:05:32 PM PST 23 |
Dec 20 01:08:24 PM PST 23 |
1209871682 ps |
T294 |
/workspace/coverage/default/9.sram_ctrl_regwen.898526337 |
|
|
Dec 20 01:05:00 PM PST 23 |
Dec 20 01:15:55 PM PST 23 |
3852213260 ps |
T295 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2790112078 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:12:34 PM PST 23 |
7041170460 ps |
T31 |
/workspace/coverage/default/34.sram_ctrl_stress_all.704766243 |
|
|
Dec 20 01:06:19 PM PST 23 |
Dec 20 02:56:35 PM PST 23 |
998941245902 ps |
T296 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2303850958 |
|
|
Dec 20 01:04:59 PM PST 23 |
Dec 20 01:07:35 PM PST 23 |
1596087488 ps |
T297 |
/workspace/coverage/default/33.sram_ctrl_partial_access.4239513859 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:06:27 PM PST 23 |
552417416 ps |
T298 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2133080957 |
|
|
Dec 20 01:05:36 PM PST 23 |
Dec 20 01:05:58 PM PST 23 |
88572610 ps |
T299 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.1269842255 |
|
|
Dec 20 01:05:05 PM PST 23 |
Dec 20 01:08:01 PM PST 23 |
10341010978 ps |
T300 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.772507090 |
|
|
Dec 20 01:04:49 PM PST 23 |
Dec 20 01:12:57 PM PST 23 |
27201718427 ps |
T301 |
/workspace/coverage/default/11.sram_ctrl_executable.2167521240 |
|
|
Dec 20 01:05:34 PM PST 23 |
Dec 20 01:09:40 PM PST 23 |
20738045849 ps |
T129 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3985356664 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:12:04 PM PST 23 |
69328119882 ps |
T302 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1039532684 |
|
|
Dec 20 01:06:52 PM PST 23 |
Dec 20 01:08:31 PM PST 23 |
1834661304 ps |
T303 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.341137051 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:14:28 PM PST 23 |
32793448854 ps |
T304 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2264614691 |
|
|
Dec 20 01:05:00 PM PST 23 |
Dec 20 01:06:19 PM PST 23 |
742750884 ps |
T305 |
/workspace/coverage/default/19.sram_ctrl_smoke.862986571 |
|
|
Dec 20 01:05:43 PM PST 23 |
Dec 20 01:06:13 PM PST 23 |
1546666936 ps |
T306 |
/workspace/coverage/default/36.sram_ctrl_smoke.1387132822 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:06:41 PM PST 23 |
1150846934 ps |
T307 |
/workspace/coverage/default/44.sram_ctrl_smoke.96949372 |
|
|
Dec 20 01:07:00 PM PST 23 |
Dec 20 01:07:56 PM PST 23 |
2864764525 ps |
T308 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3619385357 |
|
|
Dec 20 01:06:57 PM PST 23 |
Dec 20 01:07:27 PM PST 23 |
1409264653 ps |
T309 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.206768031 |
|
|
Dec 20 01:05:10 PM PST 23 |
Dec 20 01:21:52 PM PST 23 |
52150388531 ps |
T310 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3451151836 |
|
|
Dec 20 01:04:59 PM PST 23 |
Dec 20 02:23:32 PM PST 23 |
1166436837 ps |
T311 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.1059651453 |
|
|
Dec 20 01:06:06 PM PST 23 |
Dec 20 01:10:26 PM PST 23 |
4110401160 ps |
T312 |
/workspace/coverage/default/4.sram_ctrl_smoke.3949188229 |
|
|
Dec 20 01:05:18 PM PST 23 |
Dec 20 01:06:07 PM PST 23 |
1782692087 ps |
T313 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2295993982 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:11:27 PM PST 23 |
17393501317 ps |
T314 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2244864637 |
|
|
Dec 20 01:05:47 PM PST 23 |
Dec 20 01:07:25 PM PST 23 |
11082087520 ps |
T315 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2255990145 |
|
|
Dec 20 01:05:32 PM PST 23 |
Dec 20 01:28:00 PM PST 23 |
1783862401 ps |
T316 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2439401743 |
|
|
Dec 20 01:07:19 PM PST 23 |
Dec 20 02:09:52 PM PST 23 |
156699395319 ps |
T317 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.668192256 |
|
|
Dec 20 01:05:00 PM PST 23 |
Dec 20 01:06:48 PM PST 23 |
15031617931 ps |
T118 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3135370883 |
|
|
Dec 20 01:06:44 PM PST 23 |
Dec 20 02:29:05 PM PST 23 |
938623605048 ps |
T318 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1092451436 |
|
|
Dec 20 01:05:51 PM PST 23 |
Dec 20 01:13:51 PM PST 23 |
19710657046 ps |
T319 |
/workspace/coverage/default/28.sram_ctrl_regwen.3292435767 |
|
|
Dec 20 01:06:12 PM PST 23 |
Dec 20 01:16:26 PM PST 23 |
29754346226 ps |
T320 |
/workspace/coverage/default/0.sram_ctrl_bijection.1110814814 |
|
|
Dec 20 01:04:58 PM PST 23 |
Dec 20 01:24:17 PM PST 23 |
122341137404 ps |
T321 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.619405209 |
|
|
Dec 20 01:06:34 PM PST 23 |
Dec 20 01:09:40 PM PST 23 |
4166993700 ps |
T322 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.4194132797 |
|
|
Dec 20 01:05:38 PM PST 23 |
Dec 20 01:06:19 PM PST 23 |
694529024 ps |
T323 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.196413026 |
|
|
Dec 20 01:06:07 PM PST 23 |
Dec 20 01:10:58 PM PST 23 |
4091804625 ps |
T324 |
/workspace/coverage/default/23.sram_ctrl_regwen.1397119191 |
|
|
Dec 20 01:05:46 PM PST 23 |
Dec 20 01:14:06 PM PST 23 |
7428068613 ps |
T325 |
/workspace/coverage/default/4.sram_ctrl_regwen.1311614761 |
|
|
Dec 20 01:05:14 PM PST 23 |
Dec 20 01:13:21 PM PST 23 |
48839474224 ps |
T326 |
/workspace/coverage/default/47.sram_ctrl_smoke.2097942024 |
|
|
Dec 20 01:06:57 PM PST 23 |
Dec 20 01:07:52 PM PST 23 |
4864984559 ps |
T327 |
/workspace/coverage/default/36.sram_ctrl_partial_access.958581524 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:08:47 PM PST 23 |
532668301 ps |
T328 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2181681364 |
|
|
Dec 20 01:05:28 PM PST 23 |
Dec 20 01:07:07 PM PST 23 |
10095851648 ps |
T329 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2586797243 |
|
|
Dec 20 01:05:29 PM PST 23 |
Dec 20 01:06:38 PM PST 23 |
788965498 ps |
T330 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.102162345 |
|
|
Dec 20 01:05:22 PM PST 23 |
Dec 20 01:07:53 PM PST 23 |
790203519 ps |
T331 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1266059623 |
|
|
Dec 20 01:06:45 PM PST 23 |
Dec 20 01:07:25 PM PST 23 |
1600754470 ps |
T332 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1003035389 |
|
|
Dec 20 01:06:04 PM PST 23 |
Dec 20 01:06:43 PM PST 23 |
713857067 ps |
T333 |
/workspace/coverage/default/29.sram_ctrl_alert_test.2427390556 |
|
|
Dec 20 01:05:59 PM PST 23 |
Dec 20 01:06:11 PM PST 23 |
59972756 ps |
T334 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2099608407 |
|
|
Dec 20 01:06:21 PM PST 23 |
Dec 20 01:10:34 PM PST 23 |
7206826561 ps |
T335 |
/workspace/coverage/default/31.sram_ctrl_bijection.2202095513 |
|
|
Dec 20 01:06:02 PM PST 23 |
Dec 20 01:35:05 PM PST 23 |
265881337643 ps |
T336 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3106785999 |
|
|
Dec 20 01:05:11 PM PST 23 |
Dec 20 01:05:36 PM PST 23 |
42835026 ps |
T337 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3233490910 |
|
|
Dec 20 01:07:03 PM PST 23 |
Dec 20 01:12:16 PM PST 23 |
34073122614 ps |
T338 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.650254470 |
|
|
Dec 20 01:05:57 PM PST 23 |
Dec 20 01:23:46 PM PST 23 |
138525408173 ps |
T339 |
/workspace/coverage/default/34.sram_ctrl_partial_access.4205009600 |
|
|
Dec 20 01:06:18 PM PST 23 |
Dec 20 01:07:01 PM PST 23 |
1608076194 ps |
T340 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1746106616 |
|
|
Dec 20 01:05:48 PM PST 23 |
Dec 20 01:08:24 PM PST 23 |
52723957063 ps |
T341 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.825409410 |
|
|
Dec 20 01:07:04 PM PST 23 |
Dec 20 01:37:17 PM PST 23 |
393040831 ps |
T342 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1378162294 |
|
|
Dec 20 01:06:46 PM PST 23 |
Dec 20 01:08:16 PM PST 23 |
1470025416 ps |
T343 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2335918533 |
|
|
Dec 20 01:05:46 PM PST 23 |
Dec 20 02:06:00 PM PST 23 |
1726371520 ps |
T344 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1076984144 |
|
|
Dec 20 01:06:51 PM PST 23 |
Dec 20 01:11:36 PM PST 23 |
48590230207 ps |
T345 |
/workspace/coverage/default/14.sram_ctrl_alert_test.2337737895 |
|
|
Dec 20 01:05:32 PM PST 23 |
Dec 20 01:05:49 PM PST 23 |
20773751 ps |
T346 |
/workspace/coverage/default/25.sram_ctrl_partial_access.782728527 |
|
|
Dec 20 01:05:59 PM PST 23 |
Dec 20 01:06:38 PM PST 23 |
5353335391 ps |
T347 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1907364775 |
|
|
Dec 20 01:06:40 PM PST 23 |
Dec 20 01:50:26 PM PST 23 |
6191613291 ps |
T130 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2743322263 |
|
|
Dec 20 01:06:56 PM PST 23 |
Dec 20 01:12:11 PM PST 23 |
41215521145 ps |
T348 |
/workspace/coverage/default/31.sram_ctrl_regwen.3933250625 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:23:59 PM PST 23 |
35938731471 ps |
T349 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.130291948 |
|
|
Dec 20 01:05:51 PM PST 23 |
Dec 20 01:14:04 PM PST 23 |
240591543013 ps |
T132 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.454085906 |
|
|
Dec 20 01:06:01 PM PST 23 |
Dec 20 01:10:14 PM PST 23 |
62144804269 ps |
T350 |
/workspace/coverage/default/46.sram_ctrl_alert_test.237777277 |
|
|
Dec 20 01:06:55 PM PST 23 |
Dec 20 01:07:21 PM PST 23 |
13545799 ps |
T351 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3249975656 |
|
|
Dec 20 01:05:31 PM PST 23 |
Dec 20 01:06:01 PM PST 23 |
349918775 ps |
T352 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.980998490 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:08:34 PM PST 23 |
1653254169 ps |
T353 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3615506322 |
|
|
Dec 20 01:06:18 PM PST 23 |
Dec 20 01:07:32 PM PST 23 |
752652180 ps |
T354 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.736081228 |
|
|
Dec 20 01:05:36 PM PST 23 |
Dec 20 01:10:51 PM PST 23 |
11516896425 ps |
T355 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3275028074 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:08:04 PM PST 23 |
3133577609 ps |
T356 |
/workspace/coverage/default/39.sram_ctrl_smoke.308101508 |
|
|
Dec 20 01:06:12 PM PST 23 |
Dec 20 01:06:34 PM PST 23 |
2078660799 ps |
T357 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2999644636 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:15:21 PM PST 23 |
10182479908 ps |
T358 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2147663675 |
|
|
Dec 20 01:06:58 PM PST 23 |
Dec 20 01:23:43 PM PST 23 |
2439024102 ps |
T359 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.672312367 |
|
|
Dec 20 01:05:09 PM PST 23 |
Dec 20 01:09:34 PM PST 23 |
3943916805 ps |
T360 |
/workspace/coverage/default/25.sram_ctrl_executable.1885222778 |
|
|
Dec 20 01:05:42 PM PST 23 |
Dec 20 01:20:15 PM PST 23 |
55067008349 ps |
T361 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.792208600 |
|
|
Dec 20 01:06:13 PM PST 23 |
Dec 20 01:13:27 PM PST 23 |
5525242794 ps |
T362 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.174801676 |
|
|
Dec 20 01:06:45 PM PST 23 |
Dec 20 01:09:17 PM PST 23 |
41576677426 ps |
T363 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1760585681 |
|
|
Dec 20 01:06:12 PM PST 23 |
Dec 20 01:07:45 PM PST 23 |
2408602450 ps |
T364 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.1910253446 |
|
|
Dec 20 01:05:15 PM PST 23 |
Dec 20 01:07:12 PM PST 23 |
4613245867 ps |
T365 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1057064240 |
|
|
Dec 20 01:05:02 PM PST 23 |
Dec 20 01:07:52 PM PST 23 |
6908980649 ps |
T366 |
/workspace/coverage/default/47.sram_ctrl_executable.856185251 |
|
|
Dec 20 01:07:03 PM PST 23 |
Dec 20 01:20:32 PM PST 23 |
29835170492 ps |
T367 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.4173375548 |
|
|
Dec 20 01:06:14 PM PST 23 |
Dec 20 01:21:34 PM PST 23 |
4899078023 ps |
T368 |
/workspace/coverage/default/40.sram_ctrl_smoke.2711029577 |
|
|
Dec 20 01:06:23 PM PST 23 |
Dec 20 01:08:47 PM PST 23 |
803003735 ps |
T369 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2641393233 |
|
|
Dec 20 01:05:59 PM PST 23 |
Dec 20 01:07:30 PM PST 23 |
26649806056 ps |
T370 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3761068080 |
|
|
Dec 20 01:05:20 PM PST 23 |
Dec 20 01:08:15 PM PST 23 |
5118671047 ps |
T371 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1791697583 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:06:18 PM PST 23 |
22522032 ps |
T372 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1954079034 |
|
|
Dec 20 01:06:51 PM PST 23 |
Dec 20 01:07:22 PM PST 23 |
1403098395 ps |
T373 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1723328088 |
|
|
Dec 20 01:06:44 PM PST 23 |
Dec 20 01:11:26 PM PST 23 |
3017395535 ps |
T374 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.4080572435 |
|
|
Dec 20 01:05:27 PM PST 23 |
Dec 20 01:10:49 PM PST 23 |
5801282857 ps |
T375 |
/workspace/coverage/default/31.sram_ctrl_stress_all.291418927 |
|
|
Dec 20 01:05:58 PM PST 23 |
Dec 20 02:08:34 PM PST 23 |
657905807086 ps |
T376 |
/workspace/coverage/default/23.sram_ctrl_bijection.2884751150 |
|
|
Dec 20 01:05:32 PM PST 23 |
Dec 20 01:15:56 PM PST 23 |
34223561084 ps |
T377 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3045617276 |
|
|
Dec 20 01:05:23 PM PST 23 |
Dec 20 01:47:08 PM PST 23 |
55935859101 ps |
T378 |
/workspace/coverage/default/28.sram_ctrl_smoke.3965890155 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:06:32 PM PST 23 |
858192100 ps |
T379 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.88131214 |
|
|
Dec 20 01:06:45 PM PST 23 |
Dec 20 01:07:15 PM PST 23 |
363194212 ps |
T380 |
/workspace/coverage/default/27.sram_ctrl_regwen.30883078 |
|
|
Dec 20 01:05:54 PM PST 23 |
Dec 20 01:31:32 PM PST 23 |
27487467201 ps |
T381 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1925785546 |
|
|
Dec 20 01:06:07 PM PST 23 |
Dec 20 01:20:16 PM PST 23 |
11085260132 ps |
T382 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1451309228 |
|
|
Dec 20 01:05:32 PM PST 23 |
Dec 20 01:34:29 PM PST 23 |
1413605654 ps |
T383 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.784846384 |
|
|
Dec 20 01:06:42 PM PST 23 |
Dec 20 01:22:52 PM PST 23 |
8426219684 ps |
T384 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1069569102 |
|
|
Dec 20 01:05:54 PM PST 23 |
Dec 20 01:10:28 PM PST 23 |
68369767053 ps |
T385 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4251006607 |
|
|
Dec 20 01:06:34 PM PST 23 |
Dec 20 01:25:48 PM PST 23 |
8866528909 ps |
T386 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.3869905312 |
|
|
Dec 20 01:05:01 PM PST 23 |
Dec 20 01:07:36 PM PST 23 |
4295468049 ps |
T387 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.382742757 |
|
|
Dec 20 01:05:39 PM PST 23 |
Dec 20 01:13:39 PM PST 23 |
18564309765 ps |
T388 |
/workspace/coverage/default/31.sram_ctrl_smoke.434865237 |
|
|
Dec 20 01:06:09 PM PST 23 |
Dec 20 01:06:34 PM PST 23 |
993425265 ps |
T389 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2969760525 |
|
|
Dec 20 01:06:42 PM PST 23 |
Dec 20 01:07:28 PM PST 23 |
4297835790 ps |
T390 |
/workspace/coverage/default/25.sram_ctrl_bijection.3605553074 |
|
|
Dec 20 01:05:52 PM PST 23 |
Dec 20 01:31:16 PM PST 23 |
88787464086 ps |
T391 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2168259424 |
|
|
Dec 20 01:05:39 PM PST 23 |
Dec 20 01:07:16 PM PST 23 |
17973522921 ps |
T392 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1396839908 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:06:41 PM PST 23 |
1702219610 ps |
T393 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2057940593 |
|
|
Dec 20 01:06:32 PM PST 23 |
Dec 20 01:06:52 PM PST 23 |
962281918 ps |
T394 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2925949019 |
|
|
Dec 20 01:06:33 PM PST 23 |
Dec 20 01:07:50 PM PST 23 |
9141853954 ps |
T395 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.54464971 |
|
|
Dec 20 01:05:13 PM PST 23 |
Dec 20 01:12:13 PM PST 23 |
72978553697 ps |
T396 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3560380216 |
|
|
Dec 20 01:06:39 PM PST 23 |
Dec 20 01:09:35 PM PST 23 |
2003093782 ps |
T397 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2870782324 |
|
|
Dec 20 01:05:37 PM PST 23 |
Dec 20 01:11:03 PM PST 23 |
23241795230 ps |
T398 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2905805779 |
|
|
Dec 20 01:06:13 PM PST 23 |
Dec 20 01:12:59 PM PST 23 |
16225338685 ps |
T399 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.4156688270 |
|
|
Dec 20 01:07:20 PM PST 23 |
Dec 20 01:09:28 PM PST 23 |
18953545472 ps |
T400 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2931216474 |
|
|
Dec 20 01:05:39 PM PST 23 |
Dec 20 01:24:15 PM PST 23 |
7451748441 ps |
T401 |
/workspace/coverage/default/2.sram_ctrl_bijection.3467726599 |
|
|
Dec 20 01:05:16 PM PST 23 |
Dec 20 01:36:32 PM PST 23 |
189971138552 ps |
T402 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2059434858 |
|
|
Dec 20 01:06:09 PM PST 23 |
Dec 20 01:11:58 PM PST 23 |
4808034075 ps |
T403 |
/workspace/coverage/default/37.sram_ctrl_executable.1859660399 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:19:59 PM PST 23 |
26691499113 ps |
T404 |
/workspace/coverage/default/5.sram_ctrl_smoke.2108380837 |
|
|
Dec 20 01:05:16 PM PST 23 |
Dec 20 01:05:49 PM PST 23 |
2976346417 ps |
T405 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.459916021 |
|
|
Dec 20 01:05:17 PM PST 23 |
Dec 20 01:09:13 PM PST 23 |
43112592278 ps |
T406 |
/workspace/coverage/default/38.sram_ctrl_bijection.3570451499 |
|
|
Dec 20 01:06:18 PM PST 23 |
Dec 20 01:29:35 PM PST 23 |
83337885901 ps |
T407 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2316703344 |
|
|
Dec 20 01:04:55 PM PST 23 |
Dec 20 01:19:44 PM PST 23 |
13015190851 ps |
T408 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.65521810 |
|
|
Dec 20 01:05:58 PM PST 23 |
Dec 20 01:08:29 PM PST 23 |
791301567 ps |
T409 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.247316540 |
|
|
Dec 20 01:05:36 PM PST 23 |
Dec 20 01:06:05 PM PST 23 |
1475518710 ps |
T410 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1618779386 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:23:24 PM PST 23 |
11025608770 ps |
T411 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.358160288 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:07:11 PM PST 23 |
18330993030 ps |
T412 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3688947718 |
|
|
Dec 20 01:05:15 PM PST 23 |
Dec 20 01:08:11 PM PST 23 |
35569139348 ps |
T413 |
/workspace/coverage/default/0.sram_ctrl_regwen.178539577 |
|
|
Dec 20 01:04:53 PM PST 23 |
Dec 20 01:09:12 PM PST 23 |
3996640719 ps |
T414 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.135903371 |
|
|
Dec 20 01:05:42 PM PST 23 |
Dec 20 01:08:33 PM PST 23 |
10440717602 ps |
T415 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.672199121 |
|
|
Dec 20 01:06:10 PM PST 23 |
Dec 20 01:06:54 PM PST 23 |
4246204325 ps |
T416 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2581265720 |
|
|
Dec 20 01:06:07 PM PST 23 |
Dec 20 01:30:37 PM PST 23 |
966951124 ps |
T417 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3009073378 |
|
|
Dec 20 01:07:03 PM PST 23 |
Dec 20 01:23:52 PM PST 23 |
21355296782 ps |
T418 |
/workspace/coverage/default/45.sram_ctrl_regwen.4164103749 |
|
|
Dec 20 01:06:52 PM PST 23 |
Dec 20 01:25:09 PM PST 23 |
10113703441 ps |
T419 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1560495713 |
|
|
Dec 20 01:05:34 PM PST 23 |
Dec 20 01:05:50 PM PST 23 |
64629034 ps |
T420 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3867257771 |
|
|
Dec 20 01:06:12 PM PST 23 |
Dec 20 01:08:56 PM PST 23 |
19891887544 ps |
T421 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2358998045 |
|
|
Dec 20 01:06:18 PM PST 23 |
Dec 20 01:07:10 PM PST 23 |
2857378438 ps |
T422 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2486561164 |
|
|
Dec 20 01:06:13 PM PST 23 |
Dec 20 01:28:13 PM PST 23 |
11280200828 ps |
T423 |
/workspace/coverage/default/41.sram_ctrl_partial_access.4153860783 |
|
|
Dec 20 01:06:43 PM PST 23 |
Dec 20 01:07:20 PM PST 23 |
2666614883 ps |
T424 |
/workspace/coverage/default/30.sram_ctrl_smoke.2028034192 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:06:20 PM PST 23 |
1885249673 ps |
T425 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2738412754 |
|
|
Dec 20 01:06:12 PM PST 23 |
Dec 20 01:38:20 PM PST 23 |
181433271496 ps |
T426 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2338277582 |
|
|
Dec 20 01:06:16 PM PST 23 |
Dec 20 01:10:15 PM PST 23 |
2765304983 ps |
T427 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1361132048 |
|
|
Dec 20 01:05:35 PM PST 23 |
Dec 20 01:07:23 PM PST 23 |
18429888141 ps |
T428 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3014174150 |
|
|
Dec 20 01:05:10 PM PST 23 |
Dec 20 01:06:05 PM PST 23 |
3258548431 ps |
T429 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2867765943 |
|
|
Dec 20 01:05:32 PM PST 23 |
Dec 20 01:06:56 PM PST 23 |
747656029 ps |
T430 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1090514143 |
|
|
Dec 20 01:05:25 PM PST 23 |
Dec 20 01:18:07 PM PST 23 |
117137425827 ps |
T431 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.787081629 |
|
|
Dec 20 01:06:06 PM PST 23 |
Dec 20 01:07:30 PM PST 23 |
2940778498 ps |
T432 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.479683409 |
|
|
Dec 20 01:05:31 PM PST 23 |
Dec 20 01:07:05 PM PST 23 |
47258098950 ps |
T433 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2648029511 |
|
|
Dec 20 01:06:53 PM PST 23 |
Dec 20 01:10:13 PM PST 23 |
19685345897 ps |
T434 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1219339114 |
|
|
Dec 20 01:04:56 PM PST 23 |
Dec 20 01:09:12 PM PST 23 |
3103550351 ps |
T435 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.274764548 |
|
|
Dec 20 01:06:35 PM PST 23 |
Dec 20 01:09:14 PM PST 23 |
48538241742 ps |
T436 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3278169180 |
|
|
Dec 20 01:05:55 PM PST 23 |
Dec 20 01:06:16 PM PST 23 |
2786499928 ps |
T437 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2778313925 |
|
|
Dec 20 01:05:19 PM PST 23 |
Dec 20 01:10:58 PM PST 23 |
16257601673 ps |
T438 |
/workspace/coverage/default/22.sram_ctrl_partial_access.2898344700 |
|
|
Dec 20 01:05:30 PM PST 23 |
Dec 20 01:06:01 PM PST 23 |
2730970665 ps |
T439 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1943043575 |
|
|
Dec 20 01:05:36 PM PST 23 |
Dec 20 01:07:07 PM PST 23 |
9462587320 ps |
T440 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.244559295 |
|
|
Dec 20 01:05:27 PM PST 23 |
Dec 20 01:50:32 PM PST 23 |
1088729572 ps |
T441 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3153039453 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:20:41 PM PST 23 |
14797954565 ps |
T442 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2565675840 |
|
|
Dec 20 01:05:26 PM PST 23 |
Dec 20 01:11:52 PM PST 23 |
54808153588 ps |
T443 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3204353006 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:09:03 PM PST 23 |
3247801517 ps |
T444 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.4240362874 |
|
|
Dec 20 01:05:19 PM PST 23 |
Dec 20 01:21:34 PM PST 23 |
17934188986 ps |
T445 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1821135677 |
|
|
Dec 20 01:06:53 PM PST 23 |
Dec 20 01:07:38 PM PST 23 |
895334478 ps |
T446 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3879460121 |
|
|
Dec 20 01:06:51 PM PST 23 |
Dec 20 01:14:38 PM PST 23 |
19170277879 ps |
T447 |
/workspace/coverage/default/35.sram_ctrl_executable.1994240242 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:13:26 PM PST 23 |
8601203580 ps |
T448 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3119152723 |
|
|
Dec 20 01:05:54 PM PST 23 |
Dec 20 01:11:50 PM PST 23 |
15775178267 ps |
T449 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3026916198 |
|
|
Dec 20 01:06:50 PM PST 23 |
Dec 20 01:12:41 PM PST 23 |
85959161649 ps |
T450 |
/workspace/coverage/default/9.sram_ctrl_bijection.3158462543 |
|
|
Dec 20 01:05:25 PM PST 23 |
Dec 20 01:34:22 PM PST 23 |
168291279915 ps |
T451 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1687475761 |
|
|
Dec 20 01:06:12 PM PST 23 |
Dec 20 01:07:36 PM PST 23 |
8077397407 ps |
T452 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2050566829 |
|
|
Dec 20 01:05:55 PM PST 23 |
Dec 20 01:36:31 PM PST 23 |
460203463 ps |
T453 |
/workspace/coverage/default/1.sram_ctrl_bijection.1265570340 |
|
|
Dec 20 01:05:23 PM PST 23 |
Dec 20 01:24:02 PM PST 23 |
239979968793 ps |
T454 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2798852292 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:07:50 PM PST 23 |
1228902567 ps |
T455 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.577559479 |
|
|
Dec 20 01:04:56 PM PST 23 |
Dec 20 01:07:32 PM PST 23 |
3155832084 ps |
T456 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1547342751 |
|
|
Dec 20 01:06:19 PM PST 23 |
Dec 20 01:08:55 PM PST 23 |
7024344904 ps |
T457 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2380948339 |
|
|
Dec 20 01:05:36 PM PST 23 |
Dec 20 01:09:38 PM PST 23 |
18334047183 ps |
T458 |
/workspace/coverage/default/8.sram_ctrl_regwen.1492937148 |
|
|
Dec 20 01:05:20 PM PST 23 |
Dec 20 01:20:26 PM PST 23 |
5054812876 ps |
T459 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.274371533 |
|
|
Dec 20 01:06:49 PM PST 23 |
Dec 20 01:15:11 PM PST 23 |
12967194376 ps |
T460 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3589746409 |
|
|
Dec 20 01:06:24 PM PST 23 |
Dec 20 01:21:06 PM PST 23 |
220593558 ps |
T461 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2809832436 |
|
|
Dec 20 01:05:50 PM PST 23 |
Dec 20 01:06:12 PM PST 23 |
2792868747 ps |
T462 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.1613026055 |
|
|
Dec 20 01:06:09 PM PST 23 |
Dec 20 01:08:48 PM PST 23 |
10767504469 ps |
T463 |
/workspace/coverage/default/6.sram_ctrl_executable.4207157787 |
|
|
Dec 20 01:05:06 PM PST 23 |
Dec 20 01:15:34 PM PST 23 |
13594356055 ps |
T464 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1860733288 |
|
|
Dec 20 01:07:17 PM PST 23 |
Dec 20 01:10:06 PM PST 23 |
17250867472 ps |
T465 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2298052396 |
|
|
Dec 20 01:05:08 PM PST 23 |
Dec 20 01:35:49 PM PST 23 |
2263975730 ps |
T466 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.453289265 |
|
|
Dec 20 01:04:44 PM PST 23 |
Dec 20 01:09:48 PM PST 23 |
4219603251 ps |
T467 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3114260630 |
|
|
Dec 20 01:06:10 PM PST 23 |
Dec 20 01:15:41 PM PST 23 |
23570563698 ps |
T468 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4008940419 |
|
|
Dec 20 01:05:55 PM PST 23 |
Dec 20 01:06:43 PM PST 23 |
3297754874 ps |
T469 |
/workspace/coverage/default/39.sram_ctrl_alert_test.344774071 |
|
|
Dec 20 01:06:23 PM PST 23 |
Dec 20 01:06:31 PM PST 23 |
21997412 ps |
T470 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2937185423 |
|
|
Dec 20 01:06:07 PM PST 23 |
Dec 20 01:09:56 PM PST 23 |
13744517028 ps |
T471 |
/workspace/coverage/default/26.sram_ctrl_executable.3485762205 |
|
|
Dec 20 01:05:52 PM PST 23 |
Dec 20 01:21:38 PM PST 23 |
99423091251 ps |
T472 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2696354752 |
|
|
Dec 20 01:05:42 PM PST 23 |
Dec 20 01:07:01 PM PST 23 |
1461057510 ps |
T473 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2595961934 |
|
|
Dec 20 01:05:30 PM PST 23 |
Dec 20 01:05:53 PM PST 23 |
1404823486 ps |
T474 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2424630770 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:08:48 PM PST 23 |
801499852 ps |
T475 |
/workspace/coverage/default/44.sram_ctrl_alert_test.4258803810 |
|
|
Dec 20 01:06:32 PM PST 23 |
Dec 20 01:06:34 PM PST 23 |
23096589 ps |
T84 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1283131047 |
|
|
Dec 20 01:04:59 PM PST 23 |
Dec 20 01:06:45 PM PST 23 |
12134591048 ps |
T476 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1236030172 |
|
|
Dec 20 01:06:19 PM PST 23 |
Dec 20 01:14:22 PM PST 23 |
28745196858 ps |
T477 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1538660789 |
|
|
Dec 20 01:04:57 PM PST 23 |
Dec 20 01:06:49 PM PST 23 |
7930531786 ps |
T478 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.4032888457 |
|
|
Dec 20 01:06:04 PM PST 23 |
Dec 20 01:08:25 PM PST 23 |
3132706068 ps |
T23 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2859515421 |
|
|
Dec 20 01:05:12 PM PST 23 |
Dec 20 01:05:38 PM PST 23 |
311023862 ps |
T40 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.39044653 |
|
|
Dec 20 01:06:45 PM PST 23 |
Dec 20 01:24:13 PM PST 23 |
34106449702 ps |
T41 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2748479541 |
|
|
Dec 20 01:06:56 PM PST 23 |
Dec 20 01:07:47 PM PST 23 |
5141337799 ps |
T42 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2191753466 |
|
|
Dec 20 01:05:34 PM PST 23 |
Dec 20 01:06:03 PM PST 23 |
1305193636 ps |
T43 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3434564794 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:06:51 PM PST 23 |
1203654677 ps |
T44 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.4238711723 |
|
|
Dec 20 01:05:08 PM PST 23 |
Dec 20 01:05:43 PM PST 23 |
1806986059 ps |
T45 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2917857713 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:06:56 PM PST 23 |
2956673618 ps |
T46 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3165809393 |
|
|
Dec 20 01:05:19 PM PST 23 |
Dec 20 01:06:20 PM PST 23 |
752301996 ps |
T47 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2085221685 |
|
|
Dec 20 01:06:20 PM PST 23 |
Dec 20 01:06:30 PM PST 23 |
16996824 ps |
T48 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3967803687 |
|
|
Dec 20 01:05:26 PM PST 23 |
Dec 20 01:11:17 PM PST 23 |
82667923936 ps |
T479 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1180010393 |
|
|
Dec 20 01:05:25 PM PST 23 |
Dec 20 01:07:03 PM PST 23 |
2479212094 ps |
T480 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.4006496015 |
|
|
Dec 20 01:05:23 PM PST 23 |
Dec 20 01:10:38 PM PST 23 |
17228683793 ps |
T481 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.769885209 |
|
|
Dec 20 01:04:58 PM PST 23 |
Dec 20 01:11:28 PM PST 23 |
61194193681 ps |
T482 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2579280441 |
|
|
Dec 20 01:05:30 PM PST 23 |
Dec 20 01:06:17 PM PST 23 |
696647811 ps |
T483 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.820548703 |
|
|
Dec 20 01:05:49 PM PST 23 |
Dec 20 01:07:36 PM PST 23 |
761217824 ps |
T484 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1729592766 |
|
|
Dec 20 01:05:36 PM PST 23 |
Dec 20 01:06:01 PM PST 23 |
2410962117 ps |
T485 |
/workspace/coverage/default/13.sram_ctrl_smoke.2030163103 |
|
|
Dec 20 01:05:14 PM PST 23 |
Dec 20 01:06:26 PM PST 23 |
1109421754 ps |
T486 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.532657222 |
|
|
Dec 20 01:05:30 PM PST 23 |
Dec 20 01:13:56 PM PST 23 |
29628858468 ps |
T487 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.767853114 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:07:32 PM PST 23 |
2446822546 ps |
T488 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4201893870 |
|
|
Dec 20 01:06:55 PM PST 23 |
Dec 20 01:08:32 PM PST 23 |
5562936929 ps |
T489 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.150425950 |
|
|
Dec 20 01:06:42 PM PST 23 |
Dec 20 01:08:25 PM PST 23 |
959292020 ps |
T490 |
/workspace/coverage/default/10.sram_ctrl_stress_all.3560918103 |
|
|
Dec 20 01:05:30 PM PST 23 |
Dec 20 01:54:22 PM PST 23 |
140654026701 ps |
T491 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2546265743 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:06:15 PM PST 23 |
20904128 ps |
T492 |
/workspace/coverage/default/27.sram_ctrl_smoke.3336815755 |
|
|
Dec 20 01:05:52 PM PST 23 |
Dec 20 01:06:56 PM PST 23 |
731555099 ps |
T493 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1667992256 |
|
|
Dec 20 01:06:42 PM PST 23 |
Dec 20 01:07:39 PM PST 23 |
1468540675 ps |
T494 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1198727824 |
|
|
Dec 20 01:05:10 PM PST 23 |
Dec 20 01:05:55 PM PST 23 |
2135572632 ps |
T495 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2277070553 |
|
|
Dec 20 01:05:26 PM PST 23 |
Dec 20 01:08:13 PM PST 23 |
5151316956 ps |
T496 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2075229221 |
|
|
Dec 20 01:05:23 PM PST 23 |
Dec 20 01:10:27 PM PST 23 |
3759245516 ps |
T497 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.271290758 |
|
|
Dec 20 01:05:39 PM PST 23 |
Dec 20 01:07:13 PM PST 23 |
9642507925 ps |
T498 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.4156631815 |
|
|
Dec 20 01:05:44 PM PST 23 |
Dec 20 01:12:45 PM PST 23 |
22174965221 ps |
T499 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.4138280277 |
|
|
Dec 20 01:05:25 PM PST 23 |
Dec 20 01:10:00 PM PST 23 |
35820954402 ps |
T500 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1813267363 |
|
|
Dec 20 01:06:06 PM PST 23 |
Dec 20 01:56:12 PM PST 23 |
347835231570 ps |
T501 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1836490697 |
|
|
Dec 20 01:06:13 PM PST 23 |
Dec 20 02:49:25 PM PST 23 |
264343517802 ps |
T502 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.660067381 |
|
|
Dec 20 01:05:22 PM PST 23 |
Dec 20 01:10:22 PM PST 23 |
7798974019 ps |
T503 |
/workspace/coverage/default/22.sram_ctrl_stress_all.9862498 |
|
|
Dec 20 01:05:29 PM PST 23 |
Dec 20 01:32:53 PM PST 23 |
188399937656 ps |
T504 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.3537284722 |
|
|
Dec 20 01:05:33 PM PST 23 |
Dec 20 01:06:32 PM PST 23 |
2604317300 ps |
T505 |
/workspace/coverage/default/15.sram_ctrl_smoke.3621138192 |
|
|
Dec 20 01:05:22 PM PST 23 |
Dec 20 01:06:29 PM PST 23 |
1031678822 ps |
T506 |
/workspace/coverage/default/22.sram_ctrl_bijection.764827923 |
|
|
Dec 20 01:05:37 PM PST 23 |
Dec 20 01:45:54 PM PST 23 |
736304449363 ps |