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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total test records in report: 993
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T753 /workspace/coverage/default/13.sram_ctrl_alert_test.813563620 Dec 20 01:05:35 PM PST 23 Dec 20 01:05:51 PM PST 23 31240657 ps
T754 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.405762226 Dec 20 01:05:57 PM PST 23 Dec 20 01:13:05 PM PST 23 5474081367 ps
T755 /workspace/coverage/default/16.sram_ctrl_alert_test.2194418133 Dec 20 01:05:15 PM PST 23 Dec 20 01:05:38 PM PST 23 16794835 ps
T756 /workspace/coverage/default/26.sram_ctrl_multiple_keys.1184615565 Dec 20 01:05:45 PM PST 23 Dec 20 01:22:13 PM PST 23 39033005925 ps
T757 /workspace/coverage/default/5.sram_ctrl_stress_all.67156539 Dec 20 01:05:03 PM PST 23 Dec 20 01:36:39 PM PST 23 20123622843 ps
T758 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2803623106 Dec 20 01:07:07 PM PST 23 Dec 20 01:18:50 PM PST 23 15532057390 ps
T759 /workspace/coverage/default/8.sram_ctrl_mem_walk.3342378363 Dec 20 01:05:13 PM PST 23 Dec 20 01:10:17 PM PST 23 14504127420 ps
T760 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1169922725 Dec 20 01:06:01 PM PST 23 Dec 20 01:12:04 PM PST 23 4645102737 ps
T761 /workspace/coverage/default/6.sram_ctrl_multiple_keys.4126986038 Dec 20 01:05:04 PM PST 23 Dec 20 01:28:39 PM PST 23 118714221208 ps
T762 /workspace/coverage/default/32.sram_ctrl_bijection.845853362 Dec 20 01:06:07 PM PST 23 Dec 20 01:52:53 PM PST 23 181436689254 ps
T763 /workspace/coverage/default/4.sram_ctrl_ram_cfg.2628030809 Dec 20 01:05:21 PM PST 23 Dec 20 01:05:54 PM PST 23 1342080936 ps
T764 /workspace/coverage/default/2.sram_ctrl_regwen.2329151431 Dec 20 01:04:47 PM PST 23 Dec 20 01:19:52 PM PST 23 12440166467 ps
T765 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1551211743 Dec 20 01:05:32 PM PST 23 Dec 20 01:51:36 PM PST 23 8667099337 ps
T766 /workspace/coverage/default/40.sram_ctrl_executable.964648315 Dec 20 01:06:19 PM PST 23 Dec 20 01:13:30 PM PST 23 35849263741 ps
T767 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.174663931 Dec 20 01:05:49 PM PST 23 Dec 20 01:28:32 PM PST 23 18295024975 ps
T768 /workspace/coverage/default/32.sram_ctrl_regwen.2575109688 Dec 20 01:06:07 PM PST 23 Dec 20 01:08:39 PM PST 23 1226205021 ps
T769 /workspace/coverage/default/7.sram_ctrl_regwen.2970380881 Dec 20 01:05:25 PM PST 23 Dec 20 01:25:23 PM PST 23 16250652909 ps
T770 /workspace/coverage/default/23.sram_ctrl_executable.1954560102 Dec 20 01:05:31 PM PST 23 Dec 20 01:19:11 PM PST 23 86919594825 ps
T771 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1677576707 Dec 20 01:06:15 PM PST 23 Dec 20 01:08:59 PM PST 23 4806900046 ps
T772 /workspace/coverage/default/48.sram_ctrl_bijection.4289760846 Dec 20 01:06:51 PM PST 23 Dec 20 01:42:45 PM PST 23 33147190708 ps
T773 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3506924782 Dec 20 01:06:21 PM PST 23 Dec 20 01:06:36 PM PST 23 1400685922 ps
T774 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2573891288 Dec 20 01:06:43 PM PST 23 Dec 20 01:17:26 PM PST 23 9529153670 ps
T775 /workspace/coverage/default/18.sram_ctrl_ram_cfg.2264145226 Dec 20 01:05:28 PM PST 23 Dec 20 01:05:59 PM PST 23 383801921 ps
T776 /workspace/coverage/default/42.sram_ctrl_bijection.889691496 Dec 20 01:06:55 PM PST 23 Dec 20 01:24:06 PM PST 23 61502644107 ps
T777 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1885142450 Dec 20 01:05:38 PM PST 23 Dec 20 01:13:46 PM PST 23 70178494119 ps
T778 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1594149508 Dec 20 01:06:10 PM PST 23 Dec 20 01:07:05 PM PST 23 5954618083 ps
T779 /workspace/coverage/default/35.sram_ctrl_partial_access.1759979784 Dec 20 01:06:10 PM PST 23 Dec 20 01:06:46 PM PST 23 1964442088 ps
T780 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1643234205 Dec 20 01:06:02 PM PST 23 Dec 20 01:32:25 PM PST 23 20468660632 ps
T781 /workspace/coverage/default/11.sram_ctrl_stress_all.3487016416 Dec 20 01:05:32 PM PST 23 Dec 20 02:49:31 PM PST 23 543127610833 ps
T782 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.744162383 Dec 20 01:05:15 PM PST 23 Dec 20 01:06:18 PM PST 23 4170784664 ps
T783 /workspace/coverage/default/4.sram_ctrl_executable.3338059166 Dec 20 01:05:32 PM PST 23 Dec 20 01:14:10 PM PST 23 23524737538 ps
T784 /workspace/coverage/default/47.sram_ctrl_ram_cfg.3883557336 Dec 20 01:06:51 PM PST 23 Dec 20 01:07:29 PM PST 23 355435488 ps
T785 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2432247364 Dec 20 01:06:19 PM PST 23 Dec 20 01:11:42 PM PST 23 3140731971 ps
T786 /workspace/coverage/default/28.sram_ctrl_ram_cfg.423924480 Dec 20 01:05:59 PM PST 23 Dec 20 01:06:17 PM PST 23 345875527 ps
T787 /workspace/coverage/default/14.sram_ctrl_max_throughput.586143069 Dec 20 01:05:28 PM PST 23 Dec 20 01:07:01 PM PST 23 3686782223 ps
T788 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1698627019 Dec 20 01:06:15 PM PST 23 Dec 20 01:26:31 PM PST 23 15559573110 ps
T789 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3301473265 Dec 20 01:05:39 PM PST 23 Dec 20 01:06:41 PM PST 23 14302151320 ps
T790 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.798331926 Dec 20 01:06:13 PM PST 23 Dec 20 01:56:57 PM PST 23 18850094673 ps
T791 /workspace/coverage/default/2.sram_ctrl_max_throughput.2640065018 Dec 20 01:04:47 PM PST 23 Dec 20 01:05:51 PM PST 23 2836006822 ps
T792 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.610020875 Dec 20 01:05:51 PM PST 23 Dec 20 01:22:50 PM PST 23 33431676211 ps
T793 /workspace/coverage/default/24.sram_ctrl_mem_walk.184155505 Dec 20 01:05:50 PM PST 23 Dec 20 01:08:32 PM PST 23 57465135371 ps
T794 /workspace/coverage/default/46.sram_ctrl_executable.4088806009 Dec 20 01:06:54 PM PST 23 Dec 20 01:25:39 PM PST 23 24458178635 ps
T795 /workspace/coverage/default/32.sram_ctrl_partial_access.2536341463 Dec 20 01:05:59 PM PST 23 Dec 20 01:06:48 PM PST 23 2866832110 ps
T796 /workspace/coverage/default/20.sram_ctrl_max_throughput.1385898796 Dec 20 01:05:41 PM PST 23 Dec 20 01:08:18 PM PST 23 888661993 ps
T797 /workspace/coverage/default/18.sram_ctrl_regwen.2492242733 Dec 20 01:05:40 PM PST 23 Dec 20 01:15:41 PM PST 23 40038948027 ps
T798 /workspace/coverage/default/20.sram_ctrl_stress_all.1679568310 Dec 20 01:05:41 PM PST 23 Dec 20 01:51:43 PM PST 23 369584140210 ps
T799 /workspace/coverage/default/40.sram_ctrl_regwen.2441327038 Dec 20 01:06:20 PM PST 23 Dec 20 01:26:07 PM PST 23 14602703518 ps
T800 /workspace/coverage/default/20.sram_ctrl_regwen.2993704037 Dec 20 01:05:52 PM PST 23 Dec 20 01:19:51 PM PST 23 51934423175 ps
T801 /workspace/coverage/default/13.sram_ctrl_lc_escalation.4176816216 Dec 20 01:05:27 PM PST 23 Dec 20 01:09:29 PM PST 23 48703567005 ps
T802 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.542850740 Dec 20 01:05:19 PM PST 23 Dec 20 01:06:55 PM PST 23 954304713 ps
T803 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1587104806 Dec 20 01:06:43 PM PST 23 Dec 20 01:31:29 PM PST 23 507149663 ps
T804 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.959133198 Dec 20 01:05:45 PM PST 23 Dec 20 01:09:06 PM PST 23 2797125668 ps
T805 /workspace/coverage/default/12.sram_ctrl_mem_walk.2317748476 Dec 20 01:05:19 PM PST 23 Dec 20 01:10:51 PM PST 23 41254133114 ps
T806 /workspace/coverage/default/16.sram_ctrl_smoke.560722534 Dec 20 01:05:25 PM PST 23 Dec 20 01:08:05 PM PST 23 1925341196 ps
T807 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1930916296 Dec 20 01:05:16 PM PST 23 Dec 20 01:08:01 PM PST 23 4368508741 ps
T808 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3244603614 Dec 20 01:05:46 PM PST 23 Dec 20 01:31:52 PM PST 23 399579710 ps
T809 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2933607368 Dec 20 01:06:53 PM PST 23 Dec 20 01:47:31 PM PST 23 179098929 ps
T38 /workspace/coverage/default/2.sram_ctrl_sec_cm.1097765498 Dec 20 01:04:51 PM PST 23 Dec 20 01:05:15 PM PST 23 450405296 ps
T810 /workspace/coverage/default/29.sram_ctrl_max_throughput.3902151276 Dec 20 01:05:59 PM PST 23 Dec 20 01:08:49 PM PST 23 3189921757 ps
T811 /workspace/coverage/default/40.sram_ctrl_mem_walk.4200748481 Dec 20 01:06:48 PM PST 23 Dec 20 01:09:37 PM PST 23 7115688748 ps
T812 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.585112671 Dec 20 01:06:44 PM PST 23 Dec 20 01:12:43 PM PST 23 13913423079 ps
T813 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3107335162 Dec 20 01:05:38 PM PST 23 Dec 20 01:51:29 PM PST 23 5533064008 ps
T814 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2901696663 Dec 20 01:06:07 PM PST 23 Dec 20 01:08:54 PM PST 23 3402291492 ps
T815 /workspace/coverage/default/28.sram_ctrl_alert_test.2523355726 Dec 20 01:06:12 PM PST 23 Dec 20 01:06:24 PM PST 23 13666991 ps
T816 /workspace/coverage/default/44.sram_ctrl_bijection.1647228385 Dec 20 01:06:32 PM PST 23 Dec 20 01:25:48 PM PST 23 540436925450 ps
T817 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2637245058 Dec 20 01:05:02 PM PST 23 Dec 20 01:06:46 PM PST 23 5118352240 ps
T818 /workspace/coverage/default/38.sram_ctrl_regwen.3305667701 Dec 20 01:06:17 PM PST 23 Dec 20 01:16:36 PM PST 23 15281495361 ps
T819 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2664358779 Dec 20 01:06:07 PM PST 23 Dec 20 01:11:59 PM PST 23 22911039798 ps
T820 /workspace/coverage/default/16.sram_ctrl_partial_access.567920246 Dec 20 01:05:25 PM PST 23 Dec 20 01:07:34 PM PST 23 5522867719 ps
T821 /workspace/coverage/default/41.sram_ctrl_bijection.4093828592 Dec 20 01:06:43 PM PST 23 Dec 20 01:43:12 PM PST 23 34516278009 ps
T822 /workspace/coverage/default/22.sram_ctrl_regwen.724407371 Dec 20 01:05:39 PM PST 23 Dec 20 01:25:22 PM PST 23 58945480151 ps
T823 /workspace/coverage/default/17.sram_ctrl_regwen.3816427912 Dec 20 01:05:37 PM PST 23 Dec 20 01:16:42 PM PST 23 26307847033 ps
T824 /workspace/coverage/default/28.sram_ctrl_mem_walk.1699599027 Dec 20 01:05:58 PM PST 23 Dec 20 01:08:29 PM PST 23 7105655151 ps
T825 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4071541461 Dec 20 01:06:57 PM PST 23 Dec 20 01:10:35 PM PST 23 2784565708 ps
T826 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2186067536 Dec 20 01:06:00 PM PST 23 Dec 20 01:29:02 PM PST 23 3345953927 ps
T827 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.322714021 Dec 20 01:06:11 PM PST 23 Dec 20 01:12:27 PM PST 23 19628152013 ps
T828 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2923628241 Dec 20 01:05:36 PM PST 23 Dec 20 01:17:26 PM PST 23 6194521241 ps
T829 /workspace/coverage/default/27.sram_ctrl_multiple_keys.4173769302 Dec 20 01:05:56 PM PST 23 Dec 20 01:23:19 PM PST 23 7196869805 ps
T830 /workspace/coverage/default/38.sram_ctrl_mem_walk.1726524257 Dec 20 01:06:17 PM PST 23 Dec 20 01:10:59 PM PST 23 14330728384 ps
T831 /workspace/coverage/default/42.sram_ctrl_regwen.2133949399 Dec 20 01:06:55 PM PST 23 Dec 20 01:07:27 PM PST 23 1716657369 ps
T832 /workspace/coverage/default/48.sram_ctrl_regwen.3627720183 Dec 20 01:06:55 PM PST 23 Dec 20 01:25:51 PM PST 23 16856560691 ps
T833 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.452737168 Dec 20 01:06:10 PM PST 23 Dec 20 01:53:21 PM PST 23 4519691815 ps
T834 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3410925245 Dec 20 01:05:13 PM PST 23 Dec 20 01:12:32 PM PST 23 11170086775 ps
T835 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1172604115 Dec 20 01:06:17 PM PST 23 Dec 20 01:07:40 PM PST 23 2470747133 ps
T836 /workspace/coverage/default/43.sram_ctrl_max_throughput.710355837 Dec 20 01:06:33 PM PST 23 Dec 20 01:07:38 PM PST 23 2991475985 ps
T837 /workspace/coverage/default/45.sram_ctrl_executable.649749795 Dec 20 01:06:51 PM PST 23 Dec 20 01:22:13 PM PST 23 85278764040 ps
T838 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2189577608 Dec 20 01:06:05 PM PST 23 Dec 20 01:07:26 PM PST 23 760614189 ps
T839 /workspace/coverage/default/21.sram_ctrl_smoke.3204653911 Dec 20 01:05:37 PM PST 23 Dec 20 01:08:05 PM PST 23 3209897893 ps
T840 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3955074412 Dec 20 01:05:41 PM PST 23 Dec 20 01:07:09 PM PST 23 950501755 ps
T841 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.162672505 Dec 20 01:05:25 PM PST 23 Dec 20 01:08:06 PM PST 23 3783968059 ps
T842 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.443733978 Dec 20 01:06:21 PM PST 23 Dec 20 01:09:09 PM PST 23 62213280485 ps
T843 /workspace/coverage/default/13.sram_ctrl_multiple_keys.2061010903 Dec 20 01:05:21 PM PST 23 Dec 20 01:31:13 PM PST 23 131993654659 ps
T844 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3236653222 Dec 20 01:05:12 PM PST 23 Dec 20 01:06:28 PM PST 23 724857753 ps
T845 /workspace/coverage/default/8.sram_ctrl_partial_access.4057797949 Dec 20 01:05:29 PM PST 23 Dec 20 01:08:57 PM PST 23 861639390 ps
T846 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2396149581 Dec 20 01:05:33 PM PST 23 Dec 20 01:08:10 PM PST 23 795551928 ps
T847 /workspace/coverage/default/33.sram_ctrl_mem_walk.1732917141 Dec 20 01:06:05 PM PST 23 Dec 20 01:10:21 PM PST 23 3943497653 ps
T848 /workspace/coverage/default/11.sram_ctrl_lc_escalation.2958130309 Dec 20 01:05:10 PM PST 23 Dec 20 01:06:46 PM PST 23 13437535343 ps
T849 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.482381533 Dec 20 01:06:13 PM PST 23 Dec 20 01:12:16 PM PST 23 7908306041 ps
T850 /workspace/coverage/default/47.sram_ctrl_alert_test.2048092261 Dec 20 01:06:55 PM PST 23 Dec 20 01:07:20 PM PST 23 20957518 ps
T851 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1702417136 Dec 20 01:06:13 PM PST 23 Dec 20 01:12:59 PM PST 23 23857467232 ps
T852 /workspace/coverage/default/42.sram_ctrl_max_throughput.1353132361 Dec 20 01:06:47 PM PST 23 Dec 20 01:09:14 PM PST 23 3259984376 ps
T853 /workspace/coverage/default/15.sram_ctrl_stress_all.4263329184 Dec 20 01:05:16 PM PST 23 Dec 20 01:41:45 PM PST 23 141346117502 ps
T854 /workspace/coverage/default/15.sram_ctrl_multiple_keys.906556064 Dec 20 01:05:27 PM PST 23 Dec 20 01:12:14 PM PST 23 18528821180 ps
T855 /workspace/coverage/default/33.sram_ctrl_alert_test.604444271 Dec 20 01:06:12 PM PST 23 Dec 20 01:06:23 PM PST 23 164808188 ps
T856 /workspace/coverage/default/20.sram_ctrl_lc_escalation.639566070 Dec 20 01:05:39 PM PST 23 Dec 20 01:10:02 PM PST 23 136035034862 ps
T857 /workspace/coverage/default/48.sram_ctrl_smoke.4082836316 Dec 20 01:06:58 PM PST 23 Dec 20 01:07:43 PM PST 23 1131607979 ps
T858 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3626382184 Dec 20 01:06:56 PM PST 23 Dec 20 01:12:36 PM PST 23 17696198914 ps
T859 /workspace/coverage/default/3.sram_ctrl_lc_escalation.926558594 Dec 20 01:05:12 PM PST 23 Dec 20 01:08:15 PM PST 23 16753105672 ps
T860 /workspace/coverage/default/14.sram_ctrl_regwen.3092534133 Dec 20 01:05:23 PM PST 23 Dec 20 01:13:40 PM PST 23 9667638699 ps
T39 /workspace/coverage/default/4.sram_ctrl_sec_cm.1448813951 Dec 20 01:04:56 PM PST 23 Dec 20 01:05:24 PM PST 23 491289575 ps
T861 /workspace/coverage/default/15.sram_ctrl_regwen.178202571 Dec 20 01:05:26 PM PST 23 Dec 20 01:23:43 PM PST 23 37472089115 ps
T862 /workspace/coverage/default/10.sram_ctrl_mem_walk.1518206674 Dec 20 01:05:30 PM PST 23 Dec 20 01:07:51 PM PST 23 7903444436 ps
T863 /workspace/coverage/default/44.sram_ctrl_mem_walk.1108688051 Dec 20 01:06:33 PM PST 23 Dec 20 01:08:48 PM PST 23 1979698439 ps
T864 /workspace/coverage/default/45.sram_ctrl_max_throughput.251838964 Dec 20 01:06:56 PM PST 23 Dec 20 01:08:32 PM PST 23 3306679068 ps
T865 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.985568730 Dec 20 01:05:53 PM PST 23 Dec 20 01:27:32 PM PST 23 15601932517 ps
T866 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2477365368 Dec 20 01:06:11 PM PST 23 Dec 20 01:17:44 PM PST 23 37737166748 ps
T867 /workspace/coverage/default/37.sram_ctrl_lc_escalation.871087441 Dec 20 01:06:16 PM PST 23 Dec 20 01:07:54 PM PST 23 34732623622 ps
T868 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2223481239 Dec 20 01:05:18 PM PST 23 Dec 20 01:21:17 PM PST 23 33716575580 ps
T869 /workspace/coverage/default/27.sram_ctrl_alert_test.710493047 Dec 20 01:05:48 PM PST 23 Dec 20 01:06:04 PM PST 23 24805043 ps
T870 /workspace/coverage/default/17.sram_ctrl_partial_access.4209597242 Dec 20 01:05:15 PM PST 23 Dec 20 01:06:05 PM PST 23 1209123643 ps
T871 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3797437213 Dec 20 01:06:04 PM PST 23 Dec 20 01:25:54 PM PST 23 44703570550 ps
T872 /workspace/coverage/default/33.sram_ctrl_regwen.2953526429 Dec 20 01:06:04 PM PST 23 Dec 20 01:09:21 PM PST 23 7807188399 ps
T873 /workspace/coverage/default/14.sram_ctrl_mem_walk.1376539729 Dec 20 01:05:22 PM PST 23 Dec 20 01:07:47 PM PST 23 7904217468 ps
T874 /workspace/coverage/default/42.sram_ctrl_stress_all.1109507913 Dec 20 01:06:39 PM PST 23 Dec 20 01:54:30 PM PST 23 134250520771 ps
T875 /workspace/coverage/default/19.sram_ctrl_max_throughput.4110955251 Dec 20 01:05:33 PM PST 23 Dec 20 01:08:46 PM PST 23 3175678010 ps
T876 /workspace/coverage/default/20.sram_ctrl_executable.2708533788 Dec 20 01:05:41 PM PST 23 Dec 20 01:24:54 PM PST 23 38992588426 ps
T877 /workspace/coverage/default/43.sram_ctrl_partial_access.948701113 Dec 20 01:06:40 PM PST 23 Dec 20 01:07:23 PM PST 23 8883590885 ps
T878 /workspace/coverage/default/31.sram_ctrl_ram_cfg.3527810642 Dec 20 01:06:07 PM PST 23 Dec 20 01:06:23 PM PST 23 363376563 ps
T879 /workspace/coverage/default/8.sram_ctrl_max_throughput.2493330908 Dec 20 01:05:27 PM PST 23 Dec 20 01:06:29 PM PST 23 2707903923 ps
T880 /workspace/coverage/default/1.sram_ctrl_executable.1056976141 Dec 20 01:05:11 PM PST 23 Dec 20 01:19:32 PM PST 23 20268529917 ps
T881 /workspace/coverage/default/47.sram_ctrl_partial_access.2795714531 Dec 20 01:07:04 PM PST 23 Dec 20 01:07:46 PM PST 23 398556589 ps
T882 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.798195960 Dec 20 01:06:08 PM PST 23 Dec 20 01:07:35 PM PST 23 2494828964 ps
T883 /workspace/coverage/default/46.sram_ctrl_lc_escalation.643353752 Dec 20 01:06:58 PM PST 23 Dec 20 01:08:22 PM PST 23 22994176573 ps
T884 /workspace/coverage/default/4.sram_ctrl_partial_access.2605256078 Dec 20 01:05:05 PM PST 23 Dec 20 01:07:17 PM PST 23 504196916 ps
T885 /workspace/coverage/default/21.sram_ctrl_mem_walk.1962170229 Dec 20 01:05:37 PM PST 23 Dec 20 01:11:04 PM PST 23 196615184170 ps
T886 /workspace/coverage/default/11.sram_ctrl_regwen.1886773444 Dec 20 01:05:25 PM PST 23 Dec 20 01:09:52 PM PST 23 1171049496 ps
T887 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3164818 Dec 20 01:05:37 PM PST 23 Dec 20 01:18:49 PM PST 23 12583546781 ps
T888 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3308858177 Dec 20 01:06:19 PM PST 23 Dec 20 01:11:30 PM PST 23 12224492656 ps
T889 /workspace/coverage/default/12.sram_ctrl_partial_access.1569342780 Dec 20 01:05:32 PM PST 23 Dec 20 01:06:02 PM PST 23 853652137 ps
T890 /workspace/coverage/default/12.sram_ctrl_alert_test.1559977786 Dec 20 01:05:25 PM PST 23 Dec 20 01:05:45 PM PST 23 33651168 ps
T891 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.933498490 Dec 20 01:06:03 PM PST 23 Dec 20 01:41:25 PM PST 23 684987915 ps
T892 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2693367189 Dec 20 01:06:09 PM PST 23 Dec 20 01:28:15 PM PST 23 4125996941 ps
T893 /workspace/coverage/default/47.sram_ctrl_regwen.3136124240 Dec 20 01:06:54 PM PST 23 Dec 20 01:21:47 PM PST 23 32733603641 ps
T894 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.230173509 Dec 20 01:05:36 PM PST 23 Dec 20 01:08:56 PM PST 23 9966396714 ps
T895 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.453339136 Dec 20 01:07:20 PM PST 23 Dec 20 01:28:03 PM PST 23 27868035319 ps
T896 /workspace/coverage/default/11.sram_ctrl_bijection.1640183812 Dec 20 01:05:22 PM PST 23 Dec 20 01:19:02 PM PST 23 38008462921 ps
T897 /workspace/coverage/default/36.sram_ctrl_ram_cfg.2637367271 Dec 20 01:06:11 PM PST 23 Dec 20 01:06:29 PM PST 23 365544278 ps
T898 /workspace/coverage/default/37.sram_ctrl_partial_access.691324514 Dec 20 01:06:16 PM PST 23 Dec 20 01:06:38 PM PST 23 494279073 ps
T899 /workspace/coverage/default/29.sram_ctrl_ram_cfg.775198214 Dec 20 01:05:57 PM PST 23 Dec 20 01:06:22 PM PST 23 2244854906 ps
T900 /workspace/coverage/default/39.sram_ctrl_ram_cfg.42794881 Dec 20 01:06:19 PM PST 23 Dec 20 01:06:35 PM PST 23 1397043098 ps
T901 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.622520369 Dec 20 01:05:47 PM PST 23 Dec 20 01:07:35 PM PST 23 1511462594 ps
T902 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2169983513 Dec 20 01:06:09 PM PST 23 Dec 20 01:08:27 PM PST 23 6794098317 ps
T903 /workspace/coverage/default/11.sram_ctrl_mem_walk.1566094942 Dec 20 01:05:34 PM PST 23 Dec 20 01:11:34 PM PST 23 129130198977 ps
T904 /workspace/coverage/default/2.sram_ctrl_mem_walk.152489167 Dec 20 01:04:55 PM PST 23 Dec 20 01:07:27 PM PST 23 8228248181 ps
T905 /workspace/coverage/default/11.sram_ctrl_multiple_keys.1982777693 Dec 20 01:05:27 PM PST 23 Dec 20 01:25:55 PM PST 23 22438145687 ps
T906 /workspace/coverage/default/23.sram_ctrl_mem_walk.2690993186 Dec 20 01:05:37 PM PST 23 Dec 20 01:08:20 PM PST 23 7185442286 ps
T907 /workspace/coverage/default/25.sram_ctrl_lc_escalation.761305511 Dec 20 01:06:09 PM PST 23 Dec 20 01:08:06 PM PST 23 39142938943 ps
T908 /workspace/coverage/default/33.sram_ctrl_ram_cfg.826993762 Dec 20 01:06:13 PM PST 23 Dec 20 01:06:30 PM PST 23 347769443 ps
T909 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1482490980 Dec 20 01:07:02 PM PST 23 Dec 20 01:13:31 PM PST 23 15030413328 ps
T910 /workspace/coverage/default/21.sram_ctrl_partial_access.2449283438 Dec 20 01:05:59 PM PST 23 Dec 20 01:06:39 PM PST 23 1245035186 ps
T911 /workspace/coverage/default/30.sram_ctrl_bijection.3267471939 Dec 20 01:06:20 PM PST 23 Dec 20 01:30:57 PM PST 23 92658103268 ps
T912 /workspace/coverage/default/24.sram_ctrl_lc_escalation.2114904098 Dec 20 01:05:54 PM PST 23 Dec 20 01:07:09 PM PST 23 13467288476 ps
T913 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3598318438 Dec 20 01:05:19 PM PST 23 Dec 20 01:11:12 PM PST 23 95944897951 ps
T914 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2585219346 Dec 20 01:05:46 PM PST 23 Dec 20 01:08:42 PM PST 23 6949977417 ps
T915 /workspace/coverage/default/24.sram_ctrl_partial_access.3211970206 Dec 20 01:05:55 PM PST 23 Dec 20 01:06:42 PM PST 23 14956392923 ps
T916 /workspace/coverage/default/45.sram_ctrl_smoke.951667527 Dec 20 01:06:42 PM PST 23 Dec 20 01:08:39 PM PST 23 2335595715 ps
T917 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1543128875 Dec 20 01:06:51 PM PST 23 Dec 20 01:08:33 PM PST 23 5328585727 ps
T918 /workspace/coverage/default/13.sram_ctrl_stress_all.3944110470 Dec 20 01:05:30 PM PST 23 Dec 20 02:00:06 PM PST 23 277415625342 ps
T919 /workspace/coverage/default/7.sram_ctrl_smoke.3449501208 Dec 20 01:05:25 PM PST 23 Dec 20 01:06:08 PM PST 23 6093029400 ps
T920 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.73999012 Dec 20 01:06:16 PM PST 23 Dec 20 01:11:05 PM PST 23 18202883684 ps
T921 /workspace/coverage/default/43.sram_ctrl_regwen.3210101981 Dec 20 01:06:41 PM PST 23 Dec 20 01:13:30 PM PST 23 8996265449 ps
T922 /workspace/coverage/default/26.sram_ctrl_mem_walk.1212781732 Dec 20 01:05:51 PM PST 23 Dec 20 01:08:19 PM PST 23 8227958731 ps
T923 /workspace/coverage/default/46.sram_ctrl_regwen.3741822224 Dec 20 01:06:54 PM PST 23 Dec 20 01:19:50 PM PST 23 22698316312 ps
T924 /workspace/coverage/default/49.sram_ctrl_max_throughput.984480032 Dec 20 01:07:17 PM PST 23 Dec 20 01:08:15 PM PST 23 743149491 ps
T925 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3027500309 Dec 20 01:06:54 PM PST 23 Dec 20 01:26:55 PM PST 23 37003689831 ps
T926 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.23134584 Dec 20 01:05:03 PM PST 23 Dec 20 01:11:40 PM PST 23 5882389207 ps
T927 /workspace/coverage/default/11.sram_ctrl_alert_test.1533000008 Dec 20 01:05:20 PM PST 23 Dec 20 01:05:40 PM PST 23 20868482 ps
T928 /workspace/coverage/default/27.sram_ctrl_stress_all.2531698610 Dec 20 01:05:59 PM PST 23 Dec 20 01:40:23 PM PST 23 33824373282 ps
T929 /workspace/coverage/default/5.sram_ctrl_executable.2036601290 Dec 20 01:05:02 PM PST 23 Dec 20 01:12:43 PM PST 23 40391041560 ps
T930 /workspace/coverage/default/21.sram_ctrl_max_throughput.2461003153 Dec 20 01:05:34 PM PST 23 Dec 20 01:08:08 PM PST 23 1646337847 ps
T931 /workspace/coverage/default/45.sram_ctrl_bijection.435165906 Dec 20 01:06:42 PM PST 23 Dec 20 01:16:34 PM PST 23 144749247167 ps
T932 /workspace/coverage/default/3.sram_ctrl_ram_cfg.1684516846 Dec 20 01:05:24 PM PST 23 Dec 20 01:05:51 PM PST 23 358091129 ps
T933 /workspace/coverage/default/47.sram_ctrl_max_throughput.1833201809 Dec 20 01:07:07 PM PST 23 Dec 20 01:08:32 PM PST 23 1472236029 ps
T934 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1220202064 Dec 20 01:05:51 PM PST 23 Dec 20 01:08:46 PM PST 23 10475633705 ps
T935 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3200748659 Dec 20 01:07:00 PM PST 23 Dec 20 01:08:44 PM PST 23 1557026754 ps
T936 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2116601561 Dec 20 01:05:02 PM PST 23 Dec 20 01:29:06 PM PST 23 178937418 ps
T937 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.100827970 Dec 20 01:06:34 PM PST 23 Dec 20 01:10:16 PM PST 23 19256281840 ps
T938 /workspace/coverage/default/46.sram_ctrl_bijection.367776078 Dec 20 01:06:52 PM PST 23 Dec 20 01:25:20 PM PST 23 46190753206 ps
T939 /workspace/coverage/default/38.sram_ctrl_smoke.1712926069 Dec 20 01:06:17 PM PST 23 Dec 20 01:06:48 PM PST 23 1335565101 ps
T940 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.285925862 Dec 20 01:06:38 PM PST 23 Dec 20 01:14:51 PM PST 23 31739222848 ps
T941 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2975603988 Dec 20 01:05:30 PM PST 23 Dec 20 02:00:25 PM PST 23 516711145 ps
T942 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3968409930 Dec 20 01:05:15 PM PST 23 Dec 20 01:43:04 PM PST 23 5088390057 ps
T943 /workspace/coverage/default/17.sram_ctrl_multiple_keys.102444582 Dec 20 01:05:28 PM PST 23 Dec 20 01:14:51 PM PST 23 11692784330 ps
T944 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3300418849 Dec 20 01:05:52 PM PST 23 Dec 20 01:06:37 PM PST 23 2725110859 ps
T945 /workspace/coverage/default/25.sram_ctrl_multiple_keys.61389574 Dec 20 01:05:44 PM PST 23 Dec 20 01:23:29 PM PST 23 70755003311 ps
T946 /workspace/coverage/default/27.sram_ctrl_ram_cfg.3832902886 Dec 20 01:06:07 PM PST 23 Dec 20 01:06:31 PM PST 23 360434733 ps
T947 /workspace/coverage/default/42.sram_ctrl_smoke.408577038 Dec 20 01:06:55 PM PST 23 Dec 20 01:07:33 PM PST 23 736852761 ps
T948 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.494099809 Dec 20 01:06:23 PM PST 23 Dec 20 01:07:56 PM PST 23 3572440675 ps
T949 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.804231436 Dec 20 01:06:11 PM PST 23 Dec 20 01:24:50 PM PST 23 10812265081 ps
T950 /workspace/coverage/default/5.sram_ctrl_multiple_keys.3349623224 Dec 20 01:05:08 PM PST 23 Dec 20 01:06:28 PM PST 23 774810906 ps
T951 /workspace/coverage/default/6.sram_ctrl_smoke.581025704 Dec 20 01:04:54 PM PST 23 Dec 20 01:05:56 PM PST 23 819162899 ps
T952 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3012580150 Dec 20 01:04:54 PM PST 23 Dec 20 01:10:11 PM PST 23 49115191153 ps
T953 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2530884981 Dec 20 01:06:54 PM PST 23 Dec 20 01:07:45 PM PST 23 2785420025 ps
T954 /workspace/coverage/default/10.sram_ctrl_executable.1202396984 Dec 20 01:05:04 PM PST 23 Dec 20 01:30:43 PM PST 23 99839212799 ps
T955 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.974461641 Dec 20 01:06:35 PM PST 23 Dec 20 01:07:25 PM PST 23 1505282174 ps
T956 /workspace/coverage/default/27.sram_ctrl_max_throughput.4170094236 Dec 20 01:05:50 PM PST 23 Dec 20 01:06:36 PM PST 23 1742856720 ps
T957 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2269499906 Dec 20 01:05:23 PM PST 23 Dec 20 01:11:41 PM PST 23 4862951887 ps
T958 /workspace/coverage/default/49.sram_ctrl_bijection.3645251431 Dec 20 01:07:03 PM PST 23 Dec 20 01:47:28 PM PST 23 116253822870 ps
T959 /workspace/coverage/default/1.sram_ctrl_stress_all.1485768015 Dec 20 01:05:18 PM PST 23 Dec 20 02:01:51 PM PST 23 147066218537 ps
T960 /workspace/coverage/default/37.sram_ctrl_smoke.2859440767 Dec 20 01:06:09 PM PST 23 Dec 20 01:08:42 PM PST 23 1629034940 ps
T961 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3418288301 Dec 20 01:05:14 PM PST 23 Dec 20 01:05:43 PM PST 23 364132839 ps
T962 /workspace/coverage/default/1.sram_ctrl_alert_test.1140682508 Dec 20 01:05:23 PM PST 23 Dec 20 01:05:43 PM PST 23 162524265 ps
T963 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2656280804 Dec 20 01:06:05 PM PST 23 Dec 20 01:20:38 PM PST 23 19028366314 ps
T964 /workspace/coverage/default/36.sram_ctrl_max_throughput.3044090683 Dec 20 01:06:11 PM PST 23 Dec 20 01:08:09 PM PST 23 1515356941 ps
T965 /workspace/coverage/default/36.sram_ctrl_multiple_keys.3967305248 Dec 20 01:06:06 PM PST 23 Dec 20 01:20:17 PM PST 23 14656072685 ps
T966 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2643032554 Dec 20 01:05:18 PM PST 23 Dec 20 01:10:14 PM PST 23 22028282957 ps
T967 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3841501011 Dec 20 01:05:39 PM PST 23 Dec 20 01:23:25 PM PST 23 15619116202 ps
T968 /workspace/coverage/default/2.sram_ctrl_ram_cfg.1286436324 Dec 20 01:04:47 PM PST 23 Dec 20 01:05:11 PM PST 23 1690187480 ps
T969 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2357989121 Dec 20 01:06:15 PM PST 23 Dec 20 01:17:47 PM PST 23 30703991291 ps
T970 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1085841027 Dec 20 01:06:08 PM PST 23 Dec 20 01:11:27 PM PST 23 4231990411 ps
T971 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.886310231 Dec 20 01:05:17 PM PST 23 Dec 20 02:10:37 PM PST 23 6450038242 ps
T972 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.462067284 Dec 20 01:06:18 PM PST 23 Dec 20 01:19:05 PM PST 23 7345447502 ps
T973 /workspace/coverage/default/14.sram_ctrl_stress_all.4174005804 Dec 20 01:05:27 PM PST 23 Dec 20 01:36:15 PM PST 23 226815218565 ps
T974 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.253831276 Dec 20 01:04:59 PM PST 23 Dec 20 01:06:44 PM PST 23 2794185228 ps
T975 /workspace/coverage/default/49.sram_ctrl_regwen.1571295388 Dec 20 01:07:20 PM PST 23 Dec 20 01:21:05 PM PST 23 28740137875 ps
T976 /workspace/coverage/default/29.sram_ctrl_smoke.150701059 Dec 20 01:06:07 PM PST 23 Dec 20 01:06:44 PM PST 23 655719807 ps
T977 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3874361089 Dec 20 01:05:40 PM PST 23 Dec 20 01:25:28 PM PST 23 33744070442 ps
T978 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1976685290 Dec 20 01:05:04 PM PST 23 Dec 20 01:05:40 PM PST 23 379973411 ps
T979 /workspace/coverage/default/37.sram_ctrl_alert_test.2215257831 Dec 20 01:06:17 PM PST 23 Dec 20 01:06:28 PM PST 23 40472862 ps
T980 /workspace/coverage/default/3.sram_ctrl_regwen.1253248149 Dec 20 01:05:01 PM PST 23 Dec 20 01:17:39 PM PST 23 8829775077 ps
T981 /workspace/coverage/default/32.sram_ctrl_mem_walk.2283439490 Dec 20 01:06:11 PM PST 23 Dec 20 01:11:34 PM PST 23 18658854237 ps
T982 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.525276102 Dec 20 01:06:51 PM PST 23 Dec 20 01:10:36 PM PST 23 10821355784 ps
T983 /workspace/coverage/default/6.sram_ctrl_alert_test.226158713 Dec 20 01:05:27 PM PST 23 Dec 20 01:05:46 PM PST 23 175764023 ps
T984 /workspace/coverage/default/48.sram_ctrl_executable.1320104450 Dec 20 01:07:00 PM PST 23 Dec 20 01:25:16 PM PST 23 30157633082 ps
T985 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3509810672 Dec 20 01:05:47 PM PST 23 Dec 20 01:24:15 PM PST 23 34660127912 ps
T986 /workspace/coverage/default/43.sram_ctrl_lc_escalation.3050894948 Dec 20 01:06:45 PM PST 23 Dec 20 01:09:42 PM PST 23 13295213260 ps
T987 /workspace/coverage/default/24.sram_ctrl_ram_cfg.3661959709 Dec 20 01:05:47 PM PST 23 Dec 20 01:06:10 PM PST 23 1400484618 ps
T988 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3299982017 Dec 20 01:04:49 PM PST 23 Dec 20 01:10:26 PM PST 23 7593388806 ps
T989 /workspace/coverage/default/8.sram_ctrl_lc_escalation.3952339177 Dec 20 01:05:23 PM PST 23 Dec 20 01:07:35 PM PST 23 58468317397 ps
T990 /workspace/coverage/default/19.sram_ctrl_alert_test.1335599199 Dec 20 01:05:37 PM PST 23 Dec 20 01:05:52 PM PST 23 34523958 ps
T991 /workspace/coverage/default/2.sram_ctrl_partial_access.3027724587 Dec 20 01:05:06 PM PST 23 Dec 20 01:06:02 PM PST 23 1703957529 ps
T992 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1619768988 Dec 20 01:05:14 PM PST 23 Dec 20 01:14:57 PM PST 23 25082061947 ps
T993 /workspace/coverage/default/46.sram_ctrl_mem_walk.1321530558 Dec 20 01:06:54 PM PST 23 Dec 20 01:11:23 PM PST 23 14070495633 ps

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3384165477
Short name T1
Test name
Test status
Simulation time 30036146448 ps
CPU time 807.19 seconds
Started Dec 20 01:06:41 PM PST 23
Finished Dec 20 01:20:36 PM PST 23
Peak memory 373996 kb
Host smart-0bbfa30c-8452-4662-b122-17df32ec7f5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384165477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.3384165477
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3441534564
Short name T10
Test name
Test status
Simulation time 2312529829 ps
CPU time 2564.95 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:48:22 PM PST 23
Peak memory 539396 kb
Host smart-449b4896-ef90-45b7-846b-f7825902313a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3441534564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3441534564
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.660729827
Short name T8
Test name
Test status
Simulation time 64250547525 ps
CPU time 1497.7 seconds
Started Dec 20 01:06:34 PM PST 23
Finished Dec 20 01:31:39 PM PST 23
Peak memory 383244 kb
Host smart-35a8f170-eb27-4eec-973d-8a8d2e31e7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660729827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_stress_all.660729827
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.1559530797
Short name T29
Test name
Test status
Simulation time 38030782985 ps
CPU time 1139.86 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:25:21 PM PST 23
Peak memory 380176 kb
Host smart-56298cbf-1c8e-47e0-abb4-c153e9d5f3d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559530797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1559530797
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3028608864
Short name T33
Test name
Test status
Simulation time 185316973 ps
CPU time 2.22 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:09 PM PST 23
Peak memory 202492 kb
Host smart-daa797a4-f675-48b4-a20a-bb2840d3bbff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028608864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.3028608864
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.4237532176
Short name T24
Test name
Test status
Simulation time 907109573 ps
CPU time 3.27 seconds
Started Dec 20 01:05:06 PM PST 23
Finished Dec 20 01:05:33 PM PST 23
Peak memory 223952 kb
Host smart-e32c29b6-7ee7-452a-b29a-a29b32886034
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237532176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.4237532176
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1018689589
Short name T128
Test name
Test status
Simulation time 69736436156 ps
CPU time 428.37 seconds
Started Dec 20 01:05:47 PM PST 23
Finished Dec 20 01:13:12 PM PST 23
Peak memory 202088 kb
Host smart-4a15e7a2-5720-4ccf-afea-d81f61f6805f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018689589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.1018689589
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.3135370883
Short name T118
Test name
Test status
Simulation time 938623605048 ps
CPU time 4914.9 seconds
Started Dec 20 01:06:44 PM PST 23
Finished Dec 20 02:29:05 PM PST 23
Peak memory 379144 kb
Host smart-9c90f68e-a6dd-4179-8df9-a7f55165b798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135370883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.3135370883
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3737740503
Short name T69
Test name
Test status
Simulation time 7539707348 ps
CPU time 57.17 seconds
Started Dec 20 12:24:05 PM PST 23
Finished Dec 20 12:25:40 PM PST 23
Peak memory 202816 kb
Host smart-58dcd33f-f18d-4d76-a80a-38c5e7905a75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737740503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3737740503
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.784901869
Short name T49
Test name
Test status
Simulation time 25523202212 ps
CPU time 417.32 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:12:40 PM PST 23
Peak memory 202248 kb
Host smart-f5ad0296-da31-415e-9ee9-9d837dabcd9a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784901869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.784901869
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.1347214237
Short name T36
Test name
Test status
Simulation time 353580797 ps
CPU time 6.69 seconds
Started Dec 20 01:05:28 PM PST 23
Finished Dec 20 01:05:53 PM PST 23
Peak memory 202308 kb
Host smart-1add1584-1882-4757-8159-94c46afb47cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347214237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1347214237
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1756378352
Short name T121
Test name
Test status
Simulation time 365991707 ps
CPU time 2.63 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 202244 kb
Host smart-b7fbab06-81fc-4197-a587-556338cc8d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756378352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.1756378352
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.400229594
Short name T239
Test name
Test status
Simulation time 41095510 ps
CPU time 0.63 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:06:23 PM PST 23
Peak memory 201404 kb
Host smart-37131980-738e-4c5b-913e-376f86a27be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400229594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.400229594
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.704766243
Short name T31
Test name
Test status
Simulation time 998941245902 ps
CPU time 6605.46 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 02:56:35 PM PST 23
Peak memory 381096 kb
Host smart-9ecf946e-6daa-44a3-ba38-eb5cb685e25f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704766243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_stress_all.704766243
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4147210052
Short name T58
Test name
Test status
Simulation time 224249204 ps
CPU time 2.02 seconds
Started Dec 20 12:23:47 PM PST 23
Finished Dec 20 12:24:30 PM PST 23
Peak memory 202520 kb
Host smart-1e5adc07-0755-46b2-81da-2210b67c99ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147210052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.4147210052
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1588010477
Short name T123
Test name
Test status
Simulation time 140537546 ps
CPU time 1.48 seconds
Started Dec 20 12:24:06 PM PST 23
Finished Dec 20 12:24:45 PM PST 23
Peak memory 202488 kb
Host smart-a195fd62-b5a1-48aa-8363-a8f8180094d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588010477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.1588010477
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.1943043575
Short name T439
Test name
Test status
Simulation time 9462587320 ps
CPU time 75.87 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:07:07 PM PST 23
Peak memory 202188 kb
Host smart-cb7812f4-2996-43f2-b9f7-4302ad482a20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943043575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.1943043575
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1370239610
Short name T94
Test name
Test status
Simulation time 15990934 ps
CPU time 0.71 seconds
Started Dec 20 12:23:57 PM PST 23
Finished Dec 20 12:24:38 PM PST 23
Peak memory 202208 kb
Host smart-e150afce-f16d-4465-8c30-35d21e5d31dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370239610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.1370239610
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.753228475
Short name T230
Test name
Test status
Simulation time 152397761 ps
CPU time 1.94 seconds
Started Dec 20 12:24:57 PM PST 23
Finished Dec 20 12:25:24 PM PST 23
Peak memory 202460 kb
Host smart-c67373f7-1511-4e29-bb1e-a0362eb4bae0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753228475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_bit_bash.753228475
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1160647988
Short name T178
Test name
Test status
Simulation time 121764519 ps
CPU time 0.65 seconds
Started Dec 20 12:23:46 PM PST 23
Finished Dec 20 12:24:27 PM PST 23
Peak memory 201536 kb
Host smart-2ab68126-f8bb-4a8b-b4aa-06a5d92cd351
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160647988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.1160647988
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1347998181
Short name T208
Test name
Test status
Simulation time 755767266 ps
CPU time 5.71 seconds
Started Dec 20 12:23:20 PM PST 23
Finished Dec 20 12:23:55 PM PST 23
Peak memory 210772 kb
Host smart-b972fa13-7a45-4e40-b1c1-e886256211f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347998181 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1347998181
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3811351651
Short name T75
Test name
Test status
Simulation time 24953104 ps
CPU time 0.66 seconds
Started Dec 20 12:23:25 PM PST 23
Finished Dec 20 12:24:00 PM PST 23
Peak memory 201664 kb
Host smart-79cb0907-45db-4331-abf1-ba1265cc9d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811351651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.3811351651
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3826078944
Short name T214
Test name
Test status
Simulation time 28469043230 ps
CPU time 119.33 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:26:18 PM PST 23
Peak memory 202624 kb
Host smart-24e10299-87a6-4919-9f49-c21fd1faa839
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826078944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3826078944
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1587576315
Short name T183
Test name
Test status
Simulation time 121591470 ps
CPU time 0.72 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:16 PM PST 23
Peak memory 202244 kb
Host smart-e08a19cd-e58e-44c0-a759-5cb1a38f7aa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587576315 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1587576315
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1584441325
Short name T168
Test name
Test status
Simulation time 491308992 ps
CPU time 4.26 seconds
Started Dec 20 12:23:31 PM PST 23
Finished Dec 20 12:24:12 PM PST 23
Peak memory 202460 kb
Host smart-8a9d6579-9cd8-4333-8375-ca6866f08b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584441325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.1584441325
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3359570538
Short name T190
Test name
Test status
Simulation time 220289072 ps
CPU time 1.4 seconds
Started Dec 20 12:23:42 PM PST 23
Finished Dec 20 12:24:22 PM PST 23
Peak memory 202364 kb
Host smart-115ab514-16b6-4436-b231-428343e8032f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359570538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.3359570538
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4171881112
Short name T78
Test name
Test status
Simulation time 41907664 ps
CPU time 0.67 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 202344 kb
Host smart-a955bf01-7d4d-4f46-a13d-cbeaa448840a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171881112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.4171881112
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2187086778
Short name T232
Test name
Test status
Simulation time 69038726 ps
CPU time 1.57 seconds
Started Dec 20 12:23:28 PM PST 23
Finished Dec 20 12:24:06 PM PST 23
Peak memory 202388 kb
Host smart-cb219c5d-de46-4bf9-ae57-56677848526e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187086778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2187086778
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2896859608
Short name T91
Test name
Test status
Simulation time 63831169 ps
CPU time 0.68 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:24:19 PM PST 23
Peak memory 201600 kb
Host smart-94aa3880-a1ca-4fc1-878c-901d3d955ad6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896859608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.2896859608
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1296084072
Short name T212
Test name
Test status
Simulation time 354200034 ps
CPU time 4.51 seconds
Started Dec 20 12:23:23 PM PST 23
Finished Dec 20 12:24:01 PM PST 23
Peak memory 202440 kb
Host smart-640e3fe6-59ea-4dfd-9fa5-0c634dbaa5d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296084072 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1296084072
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3738747535
Short name T216
Test name
Test status
Simulation time 40101098 ps
CPU time 0.62 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 201720 kb
Host smart-69a24bf6-76f9-4ebd-8567-f289e39c0fc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738747535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3738747535
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.363018421
Short name T226
Test name
Test status
Simulation time 35239504272 ps
CPU time 258.8 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:30:59 PM PST 23
Peak memory 208908 kb
Host smart-560fa942-c6c6-4d56-854e-3b3804469ee1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363018421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.363018421
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.302300064
Short name T73
Test name
Test status
Simulation time 17120210 ps
CPU time 0.68 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:07 PM PST 23
Peak memory 202040 kb
Host smart-106378ba-46a1-4182-bb99-d03a2ed9e9e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302300064 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.302300064
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2189749395
Short name T198
Test name
Test status
Simulation time 523787930 ps
CPU time 4.57 seconds
Started Dec 20 12:23:26 PM PST 23
Finished Dec 20 12:24:06 PM PST 23
Peak memory 202452 kb
Host smart-966624a7-5ce1-451d-bbfd-ea3208fce7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189749395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2189749395
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.891677733
Short name T205
Test name
Test status
Simulation time 791009314 ps
CPU time 1.85 seconds
Started Dec 20 12:23:22 PM PST 23
Finished Dec 20 12:23:56 PM PST 23
Peak memory 202476 kb
Host smart-706beaf3-3d84-49f2-8eef-0db15be5e825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891677733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.sram_ctrl_tl_intg_err.891677733
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3515495830
Short name T56
Test name
Test status
Simulation time 1400126104 ps
CPU time 5.63 seconds
Started Dec 20 12:23:47 PM PST 23
Finished Dec 20 12:24:33 PM PST 23
Peak memory 202516 kb
Host smart-9561436d-07da-4fef-904b-a744e08d2de9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515495830 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3515495830
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3664959984
Short name T96
Test name
Test status
Simulation time 17389136 ps
CPU time 0.71 seconds
Started Dec 20 12:25:18 PM PST 23
Finished Dec 20 12:25:40 PM PST 23
Peak memory 200288 kb
Host smart-d525e039-4635-47bd-8088-b3b7dc967c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664959984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.3664959984
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4285565025
Short name T97
Test name
Test status
Simulation time 25267841351 ps
CPU time 112.74 seconds
Started Dec 20 12:26:08 PM PST 23
Finished Dec 20 12:28:35 PM PST 23
Peak memory 210584 kb
Host smart-c7bbea21-3652-49c6-a123-20cf6068531e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285565025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.4285565025
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.935400677
Short name T71
Test name
Test status
Simulation time 22249845 ps
CPU time 0.71 seconds
Started Dec 20 12:25:06 PM PST 23
Finished Dec 20 12:25:27 PM PST 23
Peak memory 202148 kb
Host smart-beaf5b9b-1868-4091-a98f-52cb4a7a7aef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935400677 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.935400677
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2973167360
Short name T60
Test name
Test status
Simulation time 212836590 ps
CPU time 2.15 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:24:20 PM PST 23
Peak memory 202584 kb
Host smart-9c023f72-4d83-4cb1-a926-38522357db46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973167360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.2973167360
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3194545032
Short name T224
Test name
Test status
Simulation time 602680005 ps
CPU time 2.55 seconds
Started Dec 20 12:24:07 PM PST 23
Finished Dec 20 12:24:47 PM PST 23
Peak memory 202440 kb
Host smart-0de96077-3584-4622-a3c9-1223eb8f5652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194545032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.3194545032
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2488675577
Short name T215
Test name
Test status
Simulation time 1580795473 ps
CPU time 5.16 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:24:24 PM PST 23
Peak memory 210720 kb
Host smart-ba6b60f4-81b2-4159-a87f-18a86cc5bbf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488675577 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2488675577
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2009134698
Short name T161
Test name
Test status
Simulation time 12945601 ps
CPU time 0.62 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:49 PM PST 23
Peak memory 201720 kb
Host smart-54921e8c-12b4-437c-88df-48777cdc8ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009134698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2009134698
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2328247626
Short name T74
Test name
Test status
Simulation time 3720645541 ps
CPU time 60.34 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:27:32 PM PST 23
Peak memory 202388 kb
Host smart-e1e4845f-9926-48cf-b174-39e22cefa292
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328247626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2328247626
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2605129758
Short name T70
Test name
Test status
Simulation time 46940079 ps
CPU time 0.63 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:24:20 PM PST 23
Peak memory 201808 kb
Host smart-1b3a2b0e-da43-456a-bdaa-dedb89f84f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605129758 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2605129758
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.685565563
Short name T170
Test name
Test status
Simulation time 178402671 ps
CPU time 1.62 seconds
Started Dec 20 12:25:54 PM PST 23
Finished Dec 20 12:26:20 PM PST 23
Peak memory 202120 kb
Host smart-d9b0a888-224f-480a-a601-510729cd5773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685565563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.685565563
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1424855948
Short name T122
Test name
Test status
Simulation time 181156460 ps
CPU time 1.52 seconds
Started Dec 20 12:23:54 PM PST 23
Finished Dec 20 12:24:36 PM PST 23
Peak memory 202460 kb
Host smart-a9810447-cbc7-49f6-a6c6-12c33587b404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424855948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.1424855948
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3223537053
Short name T235
Test name
Test status
Simulation time 6850488985 ps
CPU time 4.81 seconds
Started Dec 20 12:24:03 PM PST 23
Finished Dec 20 12:24:48 PM PST 23
Peak memory 210828 kb
Host smart-37c8eb61-976e-4631-b439-4a1dd9657f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223537053 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3223537053
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3900978694
Short name T65
Test name
Test status
Simulation time 42348775 ps
CPU time 0.65 seconds
Started Dec 20 12:23:51 PM PST 23
Finished Dec 20 12:24:33 PM PST 23
Peak memory 201880 kb
Host smart-ceb2c217-c2b1-4684-9d79-831dcecb3d59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900978694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.3900978694
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1198893183
Short name T89
Test name
Test status
Simulation time 32011877687 ps
CPU time 106.03 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:27:25 PM PST 23
Peak memory 201652 kb
Host smart-62209d98-ccd4-4f06-aa6b-2a4fce30ecc2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198893183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1198893183
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2503603751
Short name T162
Test name
Test status
Simulation time 76457468 ps
CPU time 0.75 seconds
Started Dec 20 12:24:01 PM PST 23
Finished Dec 20 12:24:41 PM PST 23
Peak memory 202316 kb
Host smart-4caa2b92-118b-4fc5-8a54-90f96e0f550a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503603751 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2503603751
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.853350892
Short name T34
Test name
Test status
Simulation time 53771225 ps
CPU time 1.91 seconds
Started Dec 20 12:24:03 PM PST 23
Finished Dec 20 12:24:44 PM PST 23
Peak memory 202488 kb
Host smart-2422aeec-1219-4ac3-99fb-3187bea4f9dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853350892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_tl_errors.853350892
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.733119996
Short name T180
Test name
Test status
Simulation time 106315845 ps
CPU time 1.53 seconds
Started Dec 20 12:23:45 PM PST 23
Finished Dec 20 12:24:27 PM PST 23
Peak memory 202520 kb
Host smart-93fe5eef-150e-431b-8962-f75c4a878fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733119996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.sram_ctrl_tl_intg_err.733119996
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.473052804
Short name T55
Test name
Test status
Simulation time 351942929 ps
CPU time 12.3 seconds
Started Dec 20 12:23:41 PM PST 23
Finished Dec 20 12:24:32 PM PST 23
Peak memory 210664 kb
Host smart-7b368255-c79c-43b0-99ed-62d4fbe78f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473052804 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.473052804
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2106277428
Short name T223
Test name
Test status
Simulation time 20038838 ps
CPU time 0.65 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:24:18 PM PST 23
Peak memory 201616 kb
Host smart-13c66f52-a9a9-426b-8b1d-60da9eaa6bd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106277428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.2106277428
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3273529222
Short name T189
Test name
Test status
Simulation time 14799991264 ps
CPU time 63.41 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:25:22 PM PST 23
Peak memory 210748 kb
Host smart-7a5c99c9-d7e8-4c97-aff9-32e1acfb4de4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273529222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3273529222
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2098227429
Short name T229
Test name
Test status
Simulation time 27766469 ps
CPU time 0.64 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 202028 kb
Host smart-afd8beb4-0a51-443c-aa9e-90c3bc09b196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098227429 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2098227429
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.730271750
Short name T200
Test name
Test status
Simulation time 72319518 ps
CPU time 2.37 seconds
Started Dec 20 12:24:11 PM PST 23
Finished Dec 20 12:24:50 PM PST 23
Peak memory 202424 kb
Host smart-aad130db-08aa-4304-806e-ffa54bc2586c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730271750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_tl_errors.730271750
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1826284747
Short name T203
Test name
Test status
Simulation time 699086378 ps
CPU time 4.89 seconds
Started Dec 20 12:26:15 PM PST 23
Finished Dec 20 12:26:50 PM PST 23
Peak memory 202036 kb
Host smart-a89ea704-02e9-4d25-85e7-f18547a9c39d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826284747 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1826284747
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2551611589
Short name T77
Test name
Test status
Simulation time 14232030 ps
CPU time 0.61 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 202016 kb
Host smart-30e1cdab-5c15-4fbb-82e3-147ffc211b00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551611589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.2551611589
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2309700703
Short name T201
Test name
Test status
Simulation time 3837826207 ps
CPU time 139.13 seconds
Started Dec 20 12:24:09 PM PST 23
Finished Dec 20 12:27:05 PM PST 23
Peak memory 202608 kb
Host smart-a87b41d5-df03-4dc5-b614-ebde6fe06180
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309700703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2309700703
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1900520943
Short name T172
Test name
Test status
Simulation time 58018314 ps
CPU time 0.66 seconds
Started Dec 20 12:23:38 PM PST 23
Finished Dec 20 12:24:29 PM PST 23
Peak memory 201940 kb
Host smart-c216fee7-6a50-4837-b4a8-c4fb83ea6c9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900520943 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1900520943
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.227213772
Short name T210
Test name
Test status
Simulation time 177141388 ps
CPU time 2.8 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:26:43 PM PST 23
Peak memory 200632 kb
Host smart-95aeb16d-c36d-4a58-b41f-5365b9923810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227213772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_tl_errors.227213772
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.247312846
Short name T155
Test name
Test status
Simulation time 648081298 ps
CPU time 5.76 seconds
Started Dec 20 12:23:48 PM PST 23
Finished Dec 20 12:24:35 PM PST 23
Peak memory 202472 kb
Host smart-c55cf832-0c8e-44f1-9ff5-1b67dc6c2818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247312846 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.247312846
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3204436442
Short name T197
Test name
Test status
Simulation time 47958939 ps
CPU time 0.62 seconds
Started Dec 20 12:24:29 PM PST 23
Finished Dec 20 12:25:02 PM PST 23
Peak memory 202184 kb
Host smart-c494ddd9-124a-4f00-98d3-0943bb9b067b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204436442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3204436442
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1263175673
Short name T218
Test name
Test status
Simulation time 63898273306 ps
CPU time 272.18 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:28:46 PM PST 23
Peak memory 202580 kb
Host smart-2a672e27-6adf-4f87-990b-fe08be935ecd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263175673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1263175673
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.470387198
Short name T175
Test name
Test status
Simulation time 34859801 ps
CPU time 0.71 seconds
Started Dec 20 12:23:46 PM PST 23
Finished Dec 20 12:24:27 PM PST 23
Peak memory 202220 kb
Host smart-a73e9552-d5cc-4677-b875-dc9d57563c0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470387198 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.470387198
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.792267912
Short name T157
Test name
Test status
Simulation time 451717666 ps
CPU time 3.62 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:26:44 PM PST 23
Peak memory 200264 kb
Host smart-124fa46c-d944-4365-bf3f-593f5ec42bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792267912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_tl_errors.792267912
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4264142722
Short name T151
Test name
Test status
Simulation time 364307632 ps
CPU time 12.75 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:28 PM PST 23
Peak memory 210720 kb
Host smart-c494e5e4-da02-4bdc-aa7f-266d41d01c06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264142722 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.4264142722
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.103166580
Short name T227
Test name
Test status
Simulation time 42881470 ps
CPU time 0.63 seconds
Started Dec 20 12:24:04 PM PST 23
Finished Dec 20 12:24:43 PM PST 23
Peak memory 201292 kb
Host smart-a494473f-04e4-428c-a633-6022ed2d4a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103166580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_csr_rw.103166580
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1024980113
Short name T66
Test name
Test status
Simulation time 7343108459 ps
CPU time 271.56 seconds
Started Dec 20 12:24:58 PM PST 23
Finished Dec 20 12:29:54 PM PST 23
Peak memory 202676 kb
Host smart-edae8bf6-3c12-484c-8d09-70d678effbdd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024980113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1024980113
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.757600602
Short name T207
Test name
Test status
Simulation time 18886488 ps
CPU time 0.72 seconds
Started Dec 20 12:24:05 PM PST 23
Finished Dec 20 12:24:43 PM PST 23
Peak memory 202216 kb
Host smart-d7d4eb9c-2b6e-4843-8f16-17ca913934eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757600602 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.757600602
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3131601499
Short name T225
Test name
Test status
Simulation time 60738665 ps
CPU time 2.07 seconds
Started Dec 20 12:24:00 PM PST 23
Finished Dec 20 12:24:42 PM PST 23
Peak memory 202404 kb
Host smart-f10fff4e-6363-4be7-b2de-c1da2bf06cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131601499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.3131601499
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1047888017
Short name T115
Test name
Test status
Simulation time 169521136 ps
CPU time 2.07 seconds
Started Dec 20 12:23:39 PM PST 23
Finished Dec 20 12:24:19 PM PST 23
Peak memory 202420 kb
Host smart-7171eff8-b74a-4037-a448-cfec352c7c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047888017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1047888017
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.845509542
Short name T234
Test name
Test status
Simulation time 1584860478 ps
CPU time 14.08 seconds
Started Dec 20 12:24:16 PM PST 23
Finished Dec 20 12:25:06 PM PST 23
Peak memory 211684 kb
Host smart-768b20c2-5294-4d72-87d0-2dcbca7717ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845509542 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.845509542
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2633561802
Short name T173
Test name
Test status
Simulation time 13930752 ps
CPU time 0.63 seconds
Started Dec 20 12:26:17 PM PST 23
Finished Dec 20 12:26:49 PM PST 23
Peak memory 201424 kb
Host smart-a7f93e9d-1070-4fcc-b733-af8a11604620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633561802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.2633561802
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.133319477
Short name T169
Test name
Test status
Simulation time 3857020632 ps
CPU time 49.66 seconds
Started Dec 20 12:26:27 PM PST 23
Finished Dec 20 12:27:51 PM PST 23
Peak memory 210584 kb
Host smart-9c0204d5-8aed-4375-a25e-edc79ce3fede
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133319477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.133319477
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3248805434
Short name T195
Test name
Test status
Simulation time 39307470 ps
CPU time 0.62 seconds
Started Dec 20 12:23:45 PM PST 23
Finished Dec 20 12:24:26 PM PST 23
Peak memory 202256 kb
Host smart-2bc5c270-9fe6-4189-b0c0-fd7e7643ca99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248805434 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3248805434
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3741366182
Short name T217
Test name
Test status
Simulation time 76351141 ps
CPU time 2 seconds
Started Dec 20 12:23:41 PM PST 23
Finished Dec 20 12:24:24 PM PST 23
Peak memory 202692 kb
Host smart-f4db3dd3-1719-4821-a88a-396bd6c22138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741366182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.3741366182
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2027405465
Short name T120
Test name
Test status
Simulation time 3450088374 ps
CPU time 2.39 seconds
Started Dec 20 12:23:55 PM PST 23
Finished Dec 20 12:24:37 PM PST 23
Peak memory 202504 kb
Host smart-6c8121ef-8cef-4408-8899-c0eded85144c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027405465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.2027405465
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3298876059
Short name T57
Test name
Test status
Simulation time 711517627 ps
CPU time 5.3 seconds
Started Dec 20 12:23:49 PM PST 23
Finished Dec 20 12:24:36 PM PST 23
Peak memory 202588 kb
Host smart-76cfff61-085b-4e99-9dbb-0edb4138fb8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298876059 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3298876059
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1832281847
Short name T67
Test name
Test status
Simulation time 66142447 ps
CPU time 0.61 seconds
Started Dec 20 12:23:41 PM PST 23
Finished Dec 20 12:24:20 PM PST 23
Peak memory 202280 kb
Host smart-a1d467fc-8631-43de-9696-b95f78b3b3f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832281847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.1832281847
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3430121587
Short name T174
Test name
Test status
Simulation time 30702741208 ps
CPU time 63.78 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:27:35 PM PST 23
Peak memory 210584 kb
Host smart-13066b0d-1b6f-46f1-8906-23ada9d84531
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430121587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3430121587
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1523796201
Short name T165
Test name
Test status
Simulation time 34028794 ps
CPU time 0.7 seconds
Started Dec 20 12:23:49 PM PST 23
Finished Dec 20 12:24:32 PM PST 23
Peak memory 202280 kb
Host smart-0534b83c-5107-4bb5-b4f0-93aa409b1ba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523796201 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1523796201
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.389056302
Short name T184
Test name
Test status
Simulation time 39515388 ps
CPU time 3.61 seconds
Started Dec 20 12:23:39 PM PST 23
Finished Dec 20 12:24:23 PM PST 23
Peak memory 210696 kb
Host smart-f5aca25d-a499-4c41-bd13-77335755e136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389056302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.389056302
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3696282182
Short name T187
Test name
Test status
Simulation time 104437989 ps
CPU time 1.4 seconds
Started Dec 20 12:25:18 PM PST 23
Finished Dec 20 12:25:41 PM PST 23
Peak memory 201480 kb
Host smart-82d0dd4c-cd64-4c3e-b4b0-f38098acf5fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696282182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.3696282182
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3544444641
Short name T181
Test name
Test status
Simulation time 1353798568 ps
CPU time 4.62 seconds
Started Dec 20 12:25:31 PM PST 23
Finished Dec 20 12:26:04 PM PST 23
Peak memory 202384 kb
Host smart-b2933f17-82fa-4b96-a382-144700442e4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544444641 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3544444641
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4181950088
Short name T176
Test name
Test status
Simulation time 56564609 ps
CPU time 0.65 seconds
Started Dec 20 12:23:58 PM PST 23
Finished Dec 20 12:24:39 PM PST 23
Peak memory 202252 kb
Host smart-08ad65ac-f786-4b89-bf39-99b1ede6dd7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181950088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.4181950088
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1884520779
Short name T209
Test name
Test status
Simulation time 61486537123 ps
CPU time 68.58 seconds
Started Dec 20 12:26:04 PM PST 23
Finished Dec 20 12:27:35 PM PST 23
Peak memory 210584 kb
Host smart-533307a8-35b2-4eea-9868-8047ed9939b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884520779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1884520779
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3370200089
Short name T177
Test name
Test status
Simulation time 30174563 ps
CPU time 0.73 seconds
Started Dec 20 12:25:09 PM PST 23
Finished Dec 20 12:25:29 PM PST 23
Peak memory 202180 kb
Host smart-7d074442-0500-4455-b9a7-084606951df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370200089 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3370200089
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4125876218
Short name T61
Test name
Test status
Simulation time 43695479 ps
CPU time 2.03 seconds
Started Dec 20 12:24:06 PM PST 23
Finished Dec 20 12:24:46 PM PST 23
Peak memory 202576 kb
Host smart-50028f7a-913d-47e4-8dc7-80b32e56ece1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125876218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.4125876218
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3674433424
Short name T54
Test name
Test status
Simulation time 262643111 ps
CPU time 1.29 seconds
Started Dec 20 12:24:13 PM PST 23
Finished Dec 20 12:24:51 PM PST 23
Peak memory 202448 kb
Host smart-59f183ad-8d83-43c8-8508-99da3fa0443f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674433424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3674433424
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1020091536
Short name T213
Test name
Test status
Simulation time 12164023 ps
CPU time 0.64 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 201324 kb
Host smart-01daae29-5e6b-4fd8-b09e-d60658202b19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020091536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.1020091536
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.555751222
Short name T164
Test name
Test status
Simulation time 74797933 ps
CPU time 1.65 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:09 PM PST 23
Peak memory 202472 kb
Host smart-7a3941c6-c95a-4d76-8d1f-043f5afdb990
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555751222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_bit_bash.555751222
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.29924268
Short name T221
Test name
Test status
Simulation time 106619466 ps
CPU time 0.64 seconds
Started Dec 20 12:23:42 PM PST 23
Finished Dec 20 12:24:28 PM PST 23
Peak memory 202272 kb
Host smart-679fbe91-2c0a-41b1-a07c-19b9f7cb87bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29924268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_hw_reset.29924268
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3112277601
Short name T59
Test name
Test status
Simulation time 2143885041 ps
CPU time 6.41 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 210620 kb
Host smart-e8c5213f-4638-456d-8346-46b5b0bc78be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112277601 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3112277601
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3631606127
Short name T90
Test name
Test status
Simulation time 14473410 ps
CPU time 0.63 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 202224 kb
Host smart-158ae235-ad36-4b63-a998-b47a9f5ac9de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631606127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3631606127
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1491870921
Short name T154
Test name
Test status
Simulation time 7998113736 ps
CPU time 116.31 seconds
Started Dec 20 12:23:19 PM PST 23
Finished Dec 20 12:25:45 PM PST 23
Peak memory 210884 kb
Host smart-f9dfbc4f-3c0f-4a1b-818f-6c03dde8aad1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491870921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1491870921
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3099527303
Short name T167
Test name
Test status
Simulation time 125151325 ps
CPU time 0.67 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:24:19 PM PST 23
Peak memory 201848 kb
Host smart-bd4c4a0a-c14d-4235-aeb5-3b7c6364718a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099527303 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3099527303
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2026987688
Short name T64
Test name
Test status
Simulation time 218160801 ps
CPU time 1.7 seconds
Started Dec 20 12:23:34 PM PST 23
Finished Dec 20 12:24:12 PM PST 23
Peak memory 202612 kb
Host smart-f3719df9-14cc-4061-a03c-8527973fd61c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026987688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.2026987688
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3919089041
Short name T125
Test name
Test status
Simulation time 202174018 ps
CPU time 1.51 seconds
Started Dec 20 12:23:16 PM PST 23
Finished Dec 20 12:23:44 PM PST 23
Peak memory 202452 kb
Host smart-6f0c9dee-7a3f-4586-8a13-ee1b64342eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919089041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.3919089041
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.301771876
Short name T88
Test name
Test status
Simulation time 17474545 ps
CPU time 0.64 seconds
Started Dec 20 12:23:25 PM PST 23
Finished Dec 20 12:24:00 PM PST 23
Peak memory 202176 kb
Host smart-5fdf2a79-c7c8-4c7c-bfe6-77b89d3c1320
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301771876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_aliasing.301771876
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3225194377
Short name T219
Test name
Test status
Simulation time 148410424 ps
CPU time 1.89 seconds
Started Dec 20 12:24:13 PM PST 23
Finished Dec 20 12:24:52 PM PST 23
Peak memory 202404 kb
Host smart-2ec0ab5e-ef95-46ef-8ccc-58eac258a310
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225194377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.3225194377
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1062733829
Short name T79
Test name
Test status
Simulation time 25727327 ps
CPU time 0.65 seconds
Started Dec 20 12:23:25 PM PST 23
Finished Dec 20 12:24:00 PM PST 23
Peak memory 201544 kb
Host smart-ca38a273-90c7-4bc0-832a-042b348d58d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062733829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.1062733829
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1527148559
Short name T152
Test name
Test status
Simulation time 721720869 ps
CPU time 12.15 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:23 PM PST 23
Peak memory 202436 kb
Host smart-6191c6f8-5c54-4c63-850d-a2a12636a66d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527148559 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1527148559
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2635219064
Short name T112
Test name
Test status
Simulation time 14104238 ps
CPU time 0.61 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:16 PM PST 23
Peak memory 201508 kb
Host smart-f01b945f-1975-45fd-9f42-1a7fca987114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635219064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2635219064
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2470637032
Short name T87
Test name
Test status
Simulation time 24614517679 ps
CPU time 143.99 seconds
Started Dec 20 12:23:32 PM PST 23
Finished Dec 20 12:26:33 PM PST 23
Peak memory 202628 kb
Host smart-17af2859-4bdf-44ff-b05d-668a93a3f8d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470637032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2470637032
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3357458393
Short name T160
Test name
Test status
Simulation time 115396282 ps
CPU time 0.72 seconds
Started Dec 20 12:23:39 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 202332 kb
Host smart-9d5f964f-48de-4464-b0e6-cbbc0dbf5327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357458393 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3357458393
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.339026883
Short name T204
Test name
Test status
Simulation time 72356552 ps
CPU time 1.85 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 202544 kb
Host smart-192afebd-e0d8-4b64-a8dd-5ea1ed70c358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339026883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_tl_errors.339026883
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1397455104
Short name T171
Test name
Test status
Simulation time 44558940 ps
CPU time 0.65 seconds
Started Dec 20 12:24:00 PM PST 23
Finished Dec 20 12:24:41 PM PST 23
Peak memory 202176 kb
Host smart-c6bda80f-a049-4daf-8f3e-b58f96a81183
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397455104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.1397455104
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3094628880
Short name T191
Test name
Test status
Simulation time 98176680 ps
CPU time 1.13 seconds
Started Dec 20 12:23:41 PM PST 23
Finished Dec 20 12:24:21 PM PST 23
Peak memory 202416 kb
Host smart-dc25bdb3-881c-4b27-ba26-bf2c8262cb3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094628880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3094628880
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.598728584
Short name T156
Test name
Test status
Simulation time 16431653 ps
CPU time 0.63 seconds
Started Dec 20 12:23:38 PM PST 23
Finished Dec 20 12:24:16 PM PST 23
Peak memory 201316 kb
Host smart-75c639af-8570-4e65-aa3c-761fd7af0c99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598728584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_hw_reset.598728584
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2933276014
Short name T206
Test name
Test status
Simulation time 356391760 ps
CPU time 4.88 seconds
Started Dec 20 12:24:10 PM PST 23
Finished Dec 20 12:24:52 PM PST 23
Peak memory 210848 kb
Host smart-58f63df7-31a5-43f4-a21d-3d74656c1fd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933276014 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2933276014
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1964085705
Short name T92
Test name
Test status
Simulation time 15686714 ps
CPU time 0.67 seconds
Started Dec 20 12:24:12 PM PST 23
Finished Dec 20 12:24:50 PM PST 23
Peak memory 202208 kb
Host smart-f25d72fb-073a-4c0b-9ca9-d7c6cf0cd307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964085705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.1964085705
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4227311034
Short name T95
Test name
Test status
Simulation time 7740701305 ps
CPU time 136.11 seconds
Started Dec 20 12:23:21 PM PST 23
Finished Dec 20 12:26:07 PM PST 23
Peak memory 210820 kb
Host smart-09a78a25-45b4-45ac-8a84-72d6ea31d8d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227311034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.4227311034
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3620156682
Short name T196
Test name
Test status
Simulation time 17500441 ps
CPU time 0.66 seconds
Started Dec 20 12:23:22 PM PST 23
Finished Dec 20 12:23:55 PM PST 23
Peak memory 201896 kb
Host smart-7eb7ea85-1149-4045-a93a-593769fd863f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620156682 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3620156682
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1760877031
Short name T158
Test name
Test status
Simulation time 82154633 ps
CPU time 1.86 seconds
Started Dec 20 12:23:38 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 202484 kb
Host smart-c832cca9-48aa-400e-83f0-01a4169a47af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760877031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.1760877031
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.936128858
Short name T119
Test name
Test status
Simulation time 74846572 ps
CPU time 1.39 seconds
Started Dec 20 12:23:27 PM PST 23
Finished Dec 20 12:24:04 PM PST 23
Peak memory 202560 kb
Host smart-27fa1c43-6afb-470b-8aa5-84f22cc235dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936128858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.sram_ctrl_tl_intg_err.936128858
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.22268399
Short name T163
Test name
Test status
Simulation time 363514010 ps
CPU time 13.04 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:24:31 PM PST 23
Peak memory 210732 kb
Host smart-77815ab0-8e13-48df-bfd2-dc9fb213a078
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22268399 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.22268399
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.687966635
Short name T202
Test name
Test status
Simulation time 38021969 ps
CPU time 0.66 seconds
Started Dec 20 12:23:47 PM PST 23
Finished Dec 20 12:24:28 PM PST 23
Peak memory 202224 kb
Host smart-6ca5b6ed-abed-4043-bc90-9deda555c341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687966635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 5.sram_ctrl_csr_rw.687966635
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.705193943
Short name T153
Test name
Test status
Simulation time 37200054 ps
CPU time 0.65 seconds
Started Dec 20 12:24:10 PM PST 23
Finished Dec 20 12:24:49 PM PST 23
Peak memory 202272 kb
Host smart-e47ac65d-985c-4224-b95b-6c1b04775f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705193943 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.705193943
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2979496442
Short name T159
Test name
Test status
Simulation time 31496337 ps
CPU time 2.84 seconds
Started Dec 20 12:24:50 PM PST 23
Finished Dec 20 12:25:22 PM PST 23
Peak memory 202408 kb
Host smart-bc6c2c06-1715-47d6-bc79-aa1b2b0a19bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979496442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.2979496442
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.115314909
Short name T124
Test name
Test status
Simulation time 808848835 ps
CPU time 3.4 seconds
Started Dec 20 12:24:11 PM PST 23
Finished Dec 20 12:24:52 PM PST 23
Peak memory 202592 kb
Host smart-d82d0fae-ed70-4f68-ac83-7b2ab3d16849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115314909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.sram_ctrl_tl_intg_err.115314909
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3052548302
Short name T114
Test name
Test status
Simulation time 1424385596 ps
CPU time 5.11 seconds
Started Dec 20 12:23:48 PM PST 23
Finished Dec 20 12:24:34 PM PST 23
Peak memory 202388 kb
Host smart-9c05b273-e5ce-48ac-b491-62998442b99a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052548302 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3052548302
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.450676478
Short name T228
Test name
Test status
Simulation time 17356134 ps
CPU time 0.64 seconds
Started Dec 20 12:23:42 PM PST 23
Finished Dec 20 12:24:21 PM PST 23
Peak memory 201448 kb
Host smart-790513c1-d523-43f6-b72f-2d7b6ce80243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450676478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.450676478
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2255262488
Short name T179
Test name
Test status
Simulation time 3890338030 ps
CPU time 62.74 seconds
Started Dec 20 12:24:32 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 202496 kb
Host smart-7cc768f9-dab6-44dd-8eb3-f7f135d3358a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255262488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2255262488
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3922029585
Short name T220
Test name
Test status
Simulation time 44860720 ps
CPU time 0.7 seconds
Started Dec 20 12:25:09 PM PST 23
Finished Dec 20 12:25:29 PM PST 23
Peak memory 202260 kb
Host smart-d6a81ec4-bf44-4cc4-bde5-8986093861be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922029585 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3922029585
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2006255416
Short name T231
Test name
Test status
Simulation time 428204859 ps
CPU time 3.52 seconds
Started Dec 20 12:23:28 PM PST 23
Finished Dec 20 12:24:09 PM PST 23
Peak memory 210816 kb
Host smart-fcad053e-a8ec-40c7-a669-e047ff04d3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006255416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2006255416
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3836010186
Short name T53
Test name
Test status
Simulation time 264130108 ps
CPU time 1.31 seconds
Started Dec 20 12:25:03 PM PST 23
Finished Dec 20 12:25:26 PM PST 23
Peak memory 202532 kb
Host smart-38d74251-eee1-4de5-b8f7-96e23b763f0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836010186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.3836010186
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2626606796
Short name T166
Test name
Test status
Simulation time 1293440498 ps
CPU time 14.43 seconds
Started Dec 20 12:23:56 PM PST 23
Finished Dec 20 12:24:51 PM PST 23
Peak memory 210704 kb
Host smart-a2e9e3a3-358f-4f22-b989-40a05be40580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626606796 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2626606796
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1573530981
Short name T194
Test name
Test status
Simulation time 42386282 ps
CPU time 0.67 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:16 PM PST 23
Peak memory 201604 kb
Host smart-efd4ec2d-172a-45ba-8fd4-6bbb20f27e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573530981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1573530981
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1255989838
Short name T93
Test name
Test status
Simulation time 7379609193 ps
CPU time 146.87 seconds
Started Dec 20 12:24:33 PM PST 23
Finished Dec 20 12:27:31 PM PST 23
Peak memory 202668 kb
Host smart-228c866c-75fd-484b-bf49-1f01c1447ab5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255989838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.1255989838
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.562875955
Short name T188
Test name
Test status
Simulation time 81295930 ps
CPU time 0.78 seconds
Started Dec 20 12:25:13 PM PST 23
Finished Dec 20 12:25:32 PM PST 23
Peak memory 202276 kb
Host smart-392666cc-6368-464c-afe1-41765dfe0bf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562875955 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.562875955
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2718516225
Short name T186
Test name
Test status
Simulation time 276814978 ps
CPU time 4.94 seconds
Started Dec 20 12:25:16 PM PST 23
Finished Dec 20 12:25:40 PM PST 23
Peak memory 202572 kb
Host smart-139efd9b-2ca1-41dd-af76-307c6cfb0dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718516225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.2718516225
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4019091241
Short name T222
Test name
Test status
Simulation time 97969043 ps
CPU time 1.43 seconds
Started Dec 20 12:23:41 PM PST 23
Finished Dec 20 12:24:21 PM PST 23
Peak memory 202444 kb
Host smart-5c001488-a8cb-4a4a-82a8-8a7e386d529d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019091241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.4019091241
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.77951093
Short name T211
Test name
Test status
Simulation time 2799850064 ps
CPU time 5.85 seconds
Started Dec 20 12:23:41 PM PST 23
Finished Dec 20 12:24:26 PM PST 23
Peak memory 202584 kb
Host smart-24f0e397-dcdf-4a82-8be4-935713bed5a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77951093 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.77951093
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2695098247
Short name T68
Test name
Test status
Simulation time 149352681 ps
CPU time 0.62 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 201412 kb
Host smart-b1cce1a3-379e-4f22-84b0-9b38464bfe76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695098247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.2695098247
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.633498965
Short name T193
Test name
Test status
Simulation time 3746571636 ps
CPU time 60.6 seconds
Started Dec 20 12:24:11 PM PST 23
Finished Dec 20 12:25:49 PM PST 23
Peak memory 202504 kb
Host smart-017895b0-cf8b-4fc5-9cf0-59f1785eb8cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633498965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.633498965
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1476110232
Short name T104
Test name
Test status
Simulation time 30954936 ps
CPU time 0.7 seconds
Started Dec 20 12:24:06 PM PST 23
Finished Dec 20 12:24:44 PM PST 23
Peak memory 202176 kb
Host smart-fe4afacd-f13b-43f2-943a-3bd1da6374da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476110232 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1476110232
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2201514465
Short name T192
Test name
Test status
Simulation time 145048822 ps
CPU time 2.37 seconds
Started Dec 20 12:24:09 PM PST 23
Finished Dec 20 12:24:49 PM PST 23
Peak memory 202448 kb
Host smart-85c6d121-bbb7-4cd7-8e48-95ebb688120c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201514465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.2201514465
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3372711392
Short name T63
Test name
Test status
Simulation time 533082119 ps
CPU time 1.92 seconds
Started Dec 20 12:23:57 PM PST 23
Finished Dec 20 12:24:38 PM PST 23
Peak memory 202472 kb
Host smart-ac755d5d-c33f-4298-8c3c-4798c500b5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372711392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.3372711392
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1362674744
Short name T233
Test name
Test status
Simulation time 1399183057 ps
CPU time 4.68 seconds
Started Dec 20 12:23:46 PM PST 23
Finished Dec 20 12:24:30 PM PST 23
Peak memory 202600 kb
Host smart-314826d7-10d4-4855-b0cb-beb36c2dec66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362674744 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1362674744
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1455555363
Short name T182
Test name
Test status
Simulation time 14958050 ps
CPU time 0.65 seconds
Started Dec 20 12:23:45 PM PST 23
Finished Dec 20 12:24:25 PM PST 23
Peak memory 202316 kb
Host smart-653a7295-710d-479e-a9eb-b46cae064ead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455555363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1455555363
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2083418423
Short name T72
Test name
Test status
Simulation time 7114945806 ps
CPU time 265.57 seconds
Started Dec 20 12:23:40 PM PST 23
Finished Dec 20 12:28:43 PM PST 23
Peak memory 202624 kb
Host smart-c1fb918e-2f53-4d38-9c6b-1a6d72b70888
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083418423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2083418423
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1232147997
Short name T185
Test name
Test status
Simulation time 15522585 ps
CPU time 0.69 seconds
Started Dec 20 12:24:05 PM PST 23
Finished Dec 20 12:24:44 PM PST 23
Peak memory 202312 kb
Host smart-fcf0d708-137c-4a47-881f-cd7e8c53c30d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232147997 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1232147997
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1973638718
Short name T199
Test name
Test status
Simulation time 54177790 ps
CPU time 1.98 seconds
Started Dec 20 12:23:50 PM PST 23
Finished Dec 20 12:24:33 PM PST 23
Peak memory 202516 kb
Host smart-1f50031c-6aff-48b2-9b82-279eca39db3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973638718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.1973638718
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3180328360
Short name T62
Test name
Test status
Simulation time 90004809 ps
CPU time 1.28 seconds
Started Dec 20 12:23:42 PM PST 23
Finished Dec 20 12:24:22 PM PST 23
Peak memory 202516 kb
Host smart-e2a8eba0-aa12-40e1-aa29-5bd15d6f3309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180328360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.3180328360
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3299982017
Short name T988
Test name
Test status
Simulation time 7593388806 ps
CPU time 316.73 seconds
Started Dec 20 01:04:49 PM PST 23
Finished Dec 20 01:10:26 PM PST 23
Peak memory 339268 kb
Host smart-42648cda-1ef0-4445-9d0b-4d8d77774c0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299982017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.3299982017
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.712495878
Short name T630
Test name
Test status
Simulation time 33293695 ps
CPU time 0.64 seconds
Started Dec 20 01:05:11 PM PST 23
Finished Dec 20 01:05:35 PM PST 23
Peak memory 201536 kb
Host smart-900cb51d-fa66-4a02-b21d-12de5d48ec3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712495878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.712495878
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1110814814
Short name T320
Test name
Test status
Simulation time 122341137404 ps
CPU time 1132.07 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:24:17 PM PST 23
Peak memory 202416 kb
Host smart-7707aacc-b257-40fb-b1ca-5e4fae77b325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110814814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1110814814
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.1586576196
Short name T676
Test name
Test status
Simulation time 2890010022 ps
CPU time 34.13 seconds
Started Dec 20 01:05:02 PM PST 23
Finished Dec 20 01:06:02 PM PST 23
Peak memory 265524 kb
Host smart-663a996e-e3c3-4941-8922-3be819649b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586576196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.1586576196
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.668192256
Short name T317
Test name
Test status
Simulation time 15031617931 ps
CPU time 81.78 seconds
Started Dec 20 01:05:00 PM PST 23
Finished Dec 20 01:06:48 PM PST 23
Peak memory 210256 kb
Host smart-07b2ee17-9243-4d51-b95d-524a53366850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668192256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca
lation.668192256
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.1002021996
Short name T594
Test name
Test status
Simulation time 1759340652 ps
CPU time 54.7 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:06:20 PM PST 23
Peak memory 296312 kb
Host smart-8a006001-e569-4dbf-bbd4-5682836fcc64
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002021996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.1002021996
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1283131047
Short name T84
Test name
Test status
Simulation time 12134591048 ps
CPU time 79.59 seconds
Started Dec 20 01:04:59 PM PST 23
Finished Dec 20 01:06:45 PM PST 23
Peak memory 211272 kb
Host smart-187ca91a-3b76-4a57-b31e-d454c364d487
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283131047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.1283131047
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1057064240
Short name T365
Test name
Test status
Simulation time 6908980649 ps
CPU time 143.78 seconds
Started Dec 20 01:05:02 PM PST 23
Finished Dec 20 01:07:52 PM PST 23
Peak memory 202316 kb
Host smart-c22939f8-c9bd-41d1-b4b2-552378e4b639
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057064240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1057064240
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.2751255681
Short name T614
Test name
Test status
Simulation time 25406304344 ps
CPU time 1121.35 seconds
Started Dec 20 01:04:54 PM PST 23
Finished Dec 20 01:24:00 PM PST 23
Peak memory 371016 kb
Host smart-cecadd22-b868-421a-a558-8dec391d2002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751255681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.2751255681
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.3045509118
Short name T138
Test name
Test status
Simulation time 4925414194 ps
CPU time 26.04 seconds
Started Dec 20 01:05:02 PM PST 23
Finished Dec 20 01:05:54 PM PST 23
Peak memory 248220 kb
Host smart-a2f643e1-f31f-498e-8e65-5d19b8e1f5b0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045509118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.3045509118
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.772507090
Short name T300
Test name
Test status
Simulation time 27201718427 ps
CPU time 467.98 seconds
Started Dec 20 01:04:49 PM PST 23
Finished Dec 20 01:12:57 PM PST 23
Peak memory 202240 kb
Host smart-dfbe3b76-78b5-47a8-a0eb-29732b4e0a72
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772507090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.sram_ctrl_partial_access_b2b.772507090
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.54535298
Short name T733
Test name
Test status
Simulation time 1354700396 ps
CPU time 14.01 seconds
Started Dec 20 01:04:48 PM PST 23
Finished Dec 20 01:05:21 PM PST 23
Peak memory 202396 kb
Host smart-2d783f41-8e12-4a12-a1da-7aa964464dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54535298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.54535298
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.178539577
Short name T413
Test name
Test status
Simulation time 3996640719 ps
CPU time 234.44 seconds
Started Dec 20 01:04:53 PM PST 23
Finished Dec 20 01:09:12 PM PST 23
Peak memory 370840 kb
Host smart-c2a692a5-3ba1-4775-b706-2eec6cdd317b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178539577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.178539577
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.3145853056
Short name T555
Test name
Test status
Simulation time 356346051 ps
CPU time 13.04 seconds
Started Dec 20 01:04:50 PM PST 23
Finished Dec 20 01:05:22 PM PST 23
Peak memory 201988 kb
Host smart-b13c005e-2d0f-4309-a149-94e0b0341704
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145853056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3145853056
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.635464043
Short name T268
Test name
Test status
Simulation time 36994254283 ps
CPU time 1909.86 seconds
Started Dec 20 01:05:03 PM PST 23
Finished Dec 20 01:37:19 PM PST 23
Peak memory 382280 kb
Host smart-69281a16-f8e5-4794-b4d9-811adab1453f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635464043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_stress_all.635464043
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2116601561
Short name T936
Test name
Test status
Simulation time 178937418 ps
CPU time 1418.04 seconds
Started Dec 20 01:05:02 PM PST 23
Finished Dec 20 01:29:06 PM PST 23
Peak memory 416956 kb
Host smart-eec48088-4685-4198-b435-2ed14fa72ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2116601561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2116601561
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.453289265
Short name T466
Test name
Test status
Simulation time 4219603251 ps
CPU time 291.65 seconds
Started Dec 20 01:04:44 PM PST 23
Finished Dec 20 01:09:48 PM PST 23
Peak memory 202204 kb
Host smart-525a10f2-9f4e-4c6a-989c-1184ef030fba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453289265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_stress_pipeline.453289265
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1081441388
Short name T244
Test name
Test status
Simulation time 3153727771 ps
CPU time 55.27 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:06:22 PM PST 23
Peak memory 283964 kb
Host smart-df9560e4-1d9c-458c-84af-fa8eafd0812f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081441388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1081441388
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2223481239
Short name T868
Test name
Test status
Simulation time 33716575580 ps
CPU time 938.28 seconds
Started Dec 20 01:05:18 PM PST 23
Finished Dec 20 01:21:17 PM PST 23
Peak memory 379148 kb
Host smart-a6d15f1b-9418-4d8a-9a96-edde8b406a0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223481239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2223481239
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.1140682508
Short name T962
Test name
Test status
Simulation time 162524265 ps
CPU time 0.63 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:05:43 PM PST 23
Peak memory 201484 kb
Host smart-395e5fa7-adf0-4393-bc33-1ccb59cfae77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140682508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.1140682508
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.1265570340
Short name T453
Test name
Test status
Simulation time 239979968793 ps
CPU time 1099.48 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:24:02 PM PST 23
Peak memory 202224 kb
Host smart-ea8b6a02-0b09-419a-9a2d-3f8e81cd1a5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265570340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
1265570340
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.1056976141
Short name T880
Test name
Test status
Simulation time 20268529917 ps
CPU time 836.55 seconds
Started Dec 20 01:05:11 PM PST 23
Finished Dec 20 01:19:32 PM PST 23
Peak memory 370840 kb
Host smart-76646335-bea3-4fc3-a477-93a6abf0d615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056976141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.1056976141
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.2264614691
Short name T304
Test name
Test status
Simulation time 742750884 ps
CPU time 52.2 seconds
Started Dec 20 01:05:00 PM PST 23
Finished Dec 20 01:06:19 PM PST 23
Peak memory 277160 kb
Host smart-485a328e-f1ac-413d-a668-afb842f6fb94
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264614691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.2264614691
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.253831276
Short name T974
Test name
Test status
Simulation time 2794185228 ps
CPU time 77.54 seconds
Started Dec 20 01:04:59 PM PST 23
Finished Dec 20 01:06:44 PM PST 23
Peak memory 211176 kb
Host smart-6a80bf41-ccf3-4062-ad34-1bdcc601883c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253831276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_mem_partial_access.253831276
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.672312367
Short name T359
Test name
Test status
Simulation time 3943916805 ps
CPU time 240.02 seconds
Started Dec 20 01:05:09 PM PST 23
Finished Dec 20 01:09:34 PM PST 23
Peak memory 202316 kb
Host smart-17f5247b-3158-4703-88a0-621d82a5a5e7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672312367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_
mem_walk.672312367
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2289199784
Short name T141
Test name
Test status
Simulation time 19947392342 ps
CPU time 252.52 seconds
Started Dec 20 01:05:07 PM PST 23
Finished Dec 20 01:09:44 PM PST 23
Peak memory 335192 kb
Host smart-80466112-0987-47a5-80d3-44d340ef38e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289199784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2289199784
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2561020395
Short name T644
Test name
Test status
Simulation time 639979225 ps
CPU time 11.22 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:05:34 PM PST 23
Peak memory 202164 kb
Host smart-248acf9a-b63e-465c-8fef-6d665d6eaac6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561020395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2561020395
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.941690970
Short name T710
Test name
Test status
Simulation time 19726454095 ps
CPU time 358.91 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:11:24 PM PST 23
Peak memory 202240 kb
Host smart-2044db30-1ed9-4f9b-9030-f2935d5c2faf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941690970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.sram_ctrl_partial_access_b2b.941690970
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1551227255
Short name T738
Test name
Test status
Simulation time 4177748009 ps
CPU time 14.07 seconds
Started Dec 20 01:05:00 PM PST 23
Finished Dec 20 01:05:40 PM PST 23
Peak memory 202624 kb
Host smart-5f0165d3-5a79-4739-8667-ae0403f4697e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551227255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1551227255
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3219848799
Short name T276
Test name
Test status
Simulation time 52058286779 ps
CPU time 771.86 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:18:17 PM PST 23
Peak memory 369780 kb
Host smart-09bf8594-46e7-4110-bc60-f66dd9e9c9a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219848799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3219848799
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3815259611
Short name T25
Test name
Test status
Simulation time 842751686 ps
CPU time 3.36 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:05:42 PM PST 23
Peak memory 223904 kb
Host smart-a840c8df-e5bc-41f8-b9a5-171594152ad6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815259611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3815259611
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.1269902421
Short name T146
Test name
Test status
Simulation time 2721348840 ps
CPU time 16.85 seconds
Started Dec 20 01:05:03 PM PST 23
Finished Dec 20 01:05:45 PM PST 23
Peak memory 237664 kb
Host smart-59fc5cc0-f575-4b0e-8f80-7451cfe4629d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269902421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1269902421
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1485768015
Short name T959
Test name
Test status
Simulation time 147066218537 ps
CPU time 3372.3 seconds
Started Dec 20 01:05:18 PM PST 23
Finished Dec 20 02:01:51 PM PST 23
Peak memory 378928 kb
Host smart-4e68bb0a-0b63-49b4-ab51-7eff2e5464e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485768015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1485768015
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3451151836
Short name T310
Test name
Test status
Simulation time 1166436837 ps
CPU time 4686.63 seconds
Started Dec 20 01:04:59 PM PST 23
Finished Dec 20 02:23:32 PM PST 23
Peak memory 698268 kb
Host smart-9bcb44c0-52c2-431c-93f3-666686f4dd98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3451151836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3451151836
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3012580150
Short name T952
Test name
Test status
Simulation time 49115191153 ps
CPU time 292.35 seconds
Started Dec 20 01:04:54 PM PST 23
Finished Dec 20 01:10:11 PM PST 23
Peak memory 202204 kb
Host smart-a53c5014-6671-4aa9-a7e5-e9634e9c9f96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012580150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.3012580150
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.877444656
Short name T263
Test name
Test status
Simulation time 3159593828 ps
CPU time 32.82 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:05:58 PM PST 23
Peak memory 237044 kb
Host smart-d195452c-ab61-4e61-99f9-ee048b424937
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877444656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.877444656
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4240362874
Short name T444
Test name
Test status
Simulation time 17934188986 ps
CPU time 954.72 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:21:34 PM PST 23
Peak memory 372732 kb
Host smart-ea072825-ae2a-4008-bd5e-14ccc39cfdd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240362874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.4240362874
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.1269120280
Short name T513
Test name
Test status
Simulation time 56456080 ps
CPU time 0.63 seconds
Started Dec 20 01:05:06 PM PST 23
Finished Dec 20 01:05:31 PM PST 23
Peak memory 201844 kb
Host smart-46060d88-d69f-4753-885a-0b8eba1837ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269120280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.1269120280
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.1202396984
Short name T954
Test name
Test status
Simulation time 99839212799 ps
CPU time 1514.11 seconds
Started Dec 20 01:05:04 PM PST 23
Finished Dec 20 01:30:43 PM PST 23
Peak memory 379172 kb
Host smart-992ce4d0-373f-4383-8b2b-21907ad4cd21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202396984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.1202396984
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.4238711723
Short name T44
Test name
Test status
Simulation time 1806986059 ps
CPU time 10.02 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:05:43 PM PST 23
Peak memory 210360 kb
Host smart-bb9908e5-1af0-483e-8fc2-f4d0e910190d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238711723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.4238711723
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.1298177405
Short name T535
Test name
Test status
Simulation time 1483225232 ps
CPU time 31.15 seconds
Started Dec 20 01:05:09 PM PST 23
Finished Dec 20 01:06:04 PM PST 23
Peak memory 223628 kb
Host smart-9bd42fe5-fa0e-4144-b5ff-70f3930f6b08
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298177405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.1298177405
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.187189404
Short name T585
Test name
Test status
Simulation time 964194737 ps
CPU time 73.62 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:07:01 PM PST 23
Peak memory 211204 kb
Host smart-874b14fd-e00e-477b-ad8b-73ec251cec56
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187189404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_mem_partial_access.187189404
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.1518206674
Short name T862
Test name
Test status
Simulation time 7903444436 ps
CPU time 123.04 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:07:51 PM PST 23
Peak memory 202192 kb
Host smart-1b655c5f-60e5-4436-9425-59de60501502
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518206674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.1518206674
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.341137051
Short name T303
Test name
Test status
Simulation time 32793448854 ps
CPU time 525.71 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:14:28 PM PST 23
Peak memory 379032 kb
Host smart-ef471885-215d-4415-b298-fedf92af28f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341137051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip
le_keys.341137051
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.1198727824
Short name T494
Test name
Test status
Simulation time 2135572632 ps
CPU time 20.57 seconds
Started Dec 20 01:05:10 PM PST 23
Finished Dec 20 01:05:55 PM PST 23
Peak memory 201964 kb
Host smart-3c0d6be2-168d-4157-aac2-350adb2d44cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198727824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.1198727824
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2643032554
Short name T966
Test name
Test status
Simulation time 22028282957 ps
CPU time 275.17 seconds
Started Dec 20 01:05:18 PM PST 23
Finished Dec 20 01:10:14 PM PST 23
Peak memory 202204 kb
Host smart-6cc4a3a7-52e3-4dd0-a53a-bf7824c6538a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643032554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2643032554
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.668503378
Short name T525
Test name
Test status
Simulation time 350036135 ps
CPU time 13.52 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:05:51 PM PST 23
Peak memory 202496 kb
Host smart-99575ce5-9618-44e0-8485-e9de4f67e611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668503378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.668503378
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.3717300083
Short name T564
Test name
Test status
Simulation time 17322514888 ps
CPU time 1307.03 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:27:35 PM PST 23
Peak memory 381024 kb
Host smart-8a411474-f0fc-4f3a-a227-1af0ea32dceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717300083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3717300083
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.180885468
Short name T584
Test name
Test status
Simulation time 794396063 ps
CPU time 97.37 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:07:19 PM PST 23
Peak memory 345228 kb
Host smart-12c3175a-652e-4c1f-8738-283767dd1766
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180885468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.180885468
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.3560918103
Short name T490
Test name
Test status
Simulation time 140654026701 ps
CPU time 2914.07 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:54:22 PM PST 23
Peak memory 388452 kb
Host smart-24de7a68-6378-40bd-8aac-61ed1d2e37df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560918103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.3560918103
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2975603988
Short name T941
Test name
Test status
Simulation time 516711145 ps
CPU time 3277.83 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 02:00:25 PM PST 23
Peak memory 698796 kb
Host smart-6a9038e2-ef60-47e2-afdb-833a4ed7620a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2975603988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2975603988
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2778313925
Short name T437
Test name
Test status
Simulation time 16257601673 ps
CPU time 318.94 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:10:58 PM PST 23
Peak memory 202272 kb
Host smart-9e5cdf21-d546-4204-b9a3-328f7fd485ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778313925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.2778313925
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2727777778
Short name T240
Test name
Test status
Simulation time 1567541404 ps
CPU time 156.6 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:08:21 PM PST 23
Peak memory 368660 kb
Host smart-03bbd213-d523-4c98-89a0-a8e6f98bd466
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727777778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2727777778
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2262160493
Short name T76
Test name
Test status
Simulation time 13094304108 ps
CPU time 818.92 seconds
Started Dec 20 01:05:21 PM PST 23
Finished Dec 20 01:19:19 PM PST 23
Peak memory 374008 kb
Host smart-0a667184-8a64-4e29-b80b-dc8f19fa8aaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262160493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.2262160493
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.1533000008
Short name T927
Test name
Test status
Simulation time 20868482 ps
CPU time 0.61 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:05:40 PM PST 23
Peak memory 201724 kb
Host smart-9c69c785-82f7-48c3-94a5-4505f256b0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533000008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.1533000008
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.1640183812
Short name T896
Test name
Test status
Simulation time 38008462921 ps
CPU time 800.55 seconds
Started Dec 20 01:05:22 PM PST 23
Finished Dec 20 01:19:02 PM PST 23
Peak memory 201980 kb
Host smart-2e429318-b343-4479-a22b-c40a4e3d0791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640183812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.1640183812
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.2167521240
Short name T301
Test name
Test status
Simulation time 20738045849 ps
CPU time 230.05 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:09:40 PM PST 23
Peak memory 359848 kb
Host smart-16478392-852b-4862-a287-3c8fec81c7a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167521240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.2167521240
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.2958130309
Short name T848
Test name
Test status
Simulation time 13437535343 ps
CPU time 71.74 seconds
Started Dec 20 01:05:10 PM PST 23
Finished Dec 20 01:06:46 PM PST 23
Peak memory 213768 kb
Host smart-bfa85778-1b77-4f44-92c9-6ca635b98b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958130309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.2958130309
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.849291588
Short name T706
Test name
Test status
Simulation time 5603614358 ps
CPU time 28.75 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:06:12 PM PST 23
Peak memory 214124 kb
Host smart-3ea69c35-da29-4c1d-887d-2e07ec909c15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849291588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.sram_ctrl_max_throughput.849291588
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1540792056
Short name T81
Test name
Test status
Simulation time 13082124290 ps
CPU time 167.11 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:08:25 PM PST 23
Peak memory 211256 kb
Host smart-5abe509e-477b-4c3e-bb4c-a66a9e50502d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540792056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.1540792056
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.1566094942
Short name T903
Test name
Test status
Simulation time 129130198977 ps
CPU time 344.47 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:11:34 PM PST 23
Peak memory 202300 kb
Host smart-2e88d3ab-618d-432d-b04a-bbb8edcf2371
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566094942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.1566094942
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.1982777693
Short name T905
Test name
Test status
Simulation time 22438145687 ps
CPU time 1209.67 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:25:55 PM PST 23
Peak memory 378108 kb
Host smart-fd3f6e9a-8dde-47d9-a08b-a10ef38a9ed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982777693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.1982777693
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.1094034160
Short name T508
Test name
Test status
Simulation time 349785031 ps
CPU time 13.85 seconds
Started Dec 20 01:05:04 PM PST 23
Finished Dec 20 01:05:43 PM PST 23
Peak memory 202204 kb
Host smart-15535587-1a02-4942-a708-386046870aab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094034160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.1094034160
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.1304385165
Short name T684
Test name
Test status
Simulation time 1686316292 ps
CPU time 6.01 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:05:45 PM PST 23
Peak memory 202492 kb
Host smart-ac7d5da4-881e-4a4e-8905-5fe12de5e1c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304385165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1304385165
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.1886773444
Short name T886
Test name
Test status
Simulation time 1171049496 ps
CPU time 247.36 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:09:52 PM PST 23
Peak memory 369760 kb
Host smart-45cc08e4-e4cc-4c05-838f-dfae5eb0d576
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886773444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1886773444
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.3834780349
Short name T507
Test name
Test status
Simulation time 915694889 ps
CPU time 55.34 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:06:34 PM PST 23
Peak memory 310808 kb
Host smart-028fef81-f279-4eb9-b0aa-c8800920c774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834780349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3834780349
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.3487016416
Short name T781
Test name
Test status
Simulation time 543127610833 ps
CPU time 6222.5 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 02:49:31 PM PST 23
Peak memory 381136 kb
Host smart-5ceb8b01-43bd-4e36-a237-51d3b67a501e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487016416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.3487016416
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.886310231
Short name T971
Test name
Test status
Simulation time 6450038242 ps
CPU time 3898.09 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 02:10:37 PM PST 23
Peak memory 734660 kb
Host smart-27abcbf5-5f22-429c-a87a-521e628f860e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=886310231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.886310231
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2125120702
Short name T549
Test name
Test status
Simulation time 11085517662 ps
CPU time 395.85 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:12:14 PM PST 23
Peak memory 202256 kb
Host smart-c44aa633-bacf-404b-bd8a-e2d8a72ce738
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125120702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.2125120702
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3275028074
Short name T355
Test name
Test status
Simulation time 3133577609 ps
CPU time 140.47 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:08:04 PM PST 23
Peak memory 365840 kb
Host smart-1019de3c-c428-4b22-b1c1-62588c8aaca0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275028074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3275028074
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1885142450
Short name T777
Test name
Test status
Simulation time 70178494119 ps
CPU time 473.67 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:13:46 PM PST 23
Peak memory 368912 kb
Host smart-7d1f9bad-be16-420b-b80e-cf536c4a6fe2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885142450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.1885142450
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.1559977786
Short name T890
Test name
Test status
Simulation time 33651168 ps
CPU time 0.65 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:05:45 PM PST 23
Peak memory 201476 kb
Host smart-df2b4425-9820-4069-941c-8fe261b88307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559977786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.1559977786
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.2703116850
Short name T550
Test name
Test status
Simulation time 19591914925 ps
CPU time 1280.1 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:27:03 PM PST 23
Peak memory 202248 kb
Host smart-686357d8-f7d7-41c9-b04b-0b44ecb2eb8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703116850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2703116850
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.1361132048
Short name T427
Test name
Test status
Simulation time 18429888141 ps
CPU time 88.52 seconds
Started Dec 20 01:05:35 PM PST 23
Finished Dec 20 01:07:23 PM PST 23
Peak memory 210392 kb
Host smart-cc41c1ac-9bc8-47a4-a11f-00b21ade4b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361132048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.1361132048
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.102162345
Short name T330
Test name
Test status
Simulation time 790203519 ps
CPU time 131.73 seconds
Started Dec 20 01:05:22 PM PST 23
Finished Dec 20 01:07:53 PM PST 23
Peak memory 365780 kb
Host smart-f53e5859-bcf3-491f-89a0-107a645132eb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102162345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.sram_ctrl_max_throughput.102162345
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3688947718
Short name T412
Test name
Test status
Simulation time 35569139348 ps
CPU time 154.06 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:08:11 PM PST 23
Peak memory 211548 kb
Host smart-1d1d5d70-89b7-4e54-a53b-72ebbc6c2a24
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688947718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.3688947718
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.2317748476
Short name T805
Test name
Test status
Simulation time 41254133114 ps
CPU time 311.72 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:10:51 PM PST 23
Peak memory 202288 kb
Host smart-762014a1-22a1-4624-9e32-b4decf6f6201
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317748476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.2317748476
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.2914800566
Short name T144
Test name
Test status
Simulation time 77172120978 ps
CPU time 520.31 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:14:20 PM PST 23
Peak memory 379096 kb
Host smart-c91716d8-3dd9-4ad5-a26d-9a0d9a7c821c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914800566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.2914800566
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.1569342780
Short name T889
Test name
Test status
Simulation time 853652137 ps
CPU time 14.01 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:06:02 PM PST 23
Peak memory 202076 kb
Host smart-03f18960-2f93-4039-b28a-56d9667c086d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569342780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.1569342780
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3447116441
Short name T632
Test name
Test status
Simulation time 18764316901 ps
CPU time 479.09 seconds
Started Dec 20 01:05:21 PM PST 23
Finished Dec 20 01:13:40 PM PST 23
Peak memory 202260 kb
Host smart-7182ac66-c584-4f48-a6fa-4a4a55e110c3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447116441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.3447116441
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.1894938817
Short name T622
Test name
Test status
Simulation time 704522727 ps
CPU time 13.03 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:05:59 PM PST 23
Peak memory 202388 kb
Host smart-3d7bb2a3-20d7-4de3-af13-846472c025de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894938817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1894938817
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.2569795528
Short name T3
Test name
Test status
Simulation time 632302223 ps
CPU time 173.92 seconds
Started Dec 20 01:05:10 PM PST 23
Finished Dec 20 01:08:28 PM PST 23
Peak memory 372832 kb
Host smart-399eb980-b34b-4ecc-a5bf-6949b80280fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569795528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2569795528
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.1640159155
Short name T582
Test name
Test status
Simulation time 989384420 ps
CPU time 14.95 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:05:53 PM PST 23
Peak memory 202164 kb
Host smart-fa58c8bd-0039-415e-965b-4b335900d7ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640159155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1640159155
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3240240610
Short name T732
Test name
Test status
Simulation time 676791102 ps
CPU time 3686.05 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 02:07:10 PM PST 23
Peak memory 676416 kb
Host smart-4ccd0f14-3cfa-4019-9a35-1f037b047f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3240240610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3240240610
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2536364292
Short name T621
Test name
Test status
Simulation time 8377175200 ps
CPU time 322.47 seconds
Started Dec 20 01:05:21 PM PST 23
Finished Dec 20 01:11:03 PM PST 23
Peak memory 202204 kb
Host smart-fa17a491-8191-45dd-8aea-4519805a3616
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536364292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.2536364292
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2579280441
Short name T482
Test name
Test status
Simulation time 696647811 ps
CPU time 29.18 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:06:17 PM PST 23
Peak memory 226384 kb
Host smart-c8599b2f-e4d9-4365-bbaa-30d34c1f719d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579280441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2579280441
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2153142290
Short name T744
Test name
Test status
Simulation time 12235167726 ps
CPU time 898.04 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:20:48 PM PST 23
Peak memory 362612 kb
Host smart-40255327-c669-4c20-b268-94b6753e8d6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153142290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.2153142290
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.813563620
Short name T753
Test name
Test status
Simulation time 31240657 ps
CPU time 0.61 seconds
Started Dec 20 01:05:35 PM PST 23
Finished Dec 20 01:05:51 PM PST 23
Peak memory 201256 kb
Host smart-8f14116c-ee63-4656-a371-6dbc6869cf2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813563620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.813563620
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.3241903975
Short name T243
Test name
Test status
Simulation time 240602693125 ps
CPU time 1258.77 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:26:46 PM PST 23
Peak memory 202292 kb
Host smart-2443ca8a-ce6a-44ef-b85e-a24488c9ca4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241903975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.3241903975
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.4176816216
Short name T801
Test name
Test status
Simulation time 48703567005 ps
CPU time 223.82 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:09:29 PM PST 23
Peak memory 202056 kb
Host smart-01599990-926b-490d-9c65-7c56c5f2ed5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176816216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.4176816216
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.719432021
Short name T672
Test name
Test status
Simulation time 756236496 ps
CPU time 128.84 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:07:55 PM PST 23
Peak memory 349404 kb
Host smart-f1953404-b159-49fa-b251-efa022ff8a34
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719432021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.719432021
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.542850740
Short name T802
Test name
Test status
Simulation time 954304713 ps
CPU time 75.84 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:06:55 PM PST 23
Peak memory 211028 kb
Host smart-ffb8b75c-39ae-42e0-8c2b-3dff1795c55d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542850740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_mem_partial_access.542850740
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.3967803687
Short name T48
Test name
Test status
Simulation time 82667923936 ps
CPU time 332.31 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:11:17 PM PST 23
Peak memory 202252 kb
Host smart-44fe34be-3ec1-4937-a066-29135e480e89
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967803687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.3967803687
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.2061010903
Short name T843
Test name
Test status
Simulation time 131993654659 ps
CPU time 1533.18 seconds
Started Dec 20 01:05:21 PM PST 23
Finished Dec 20 01:31:13 PM PST 23
Peak memory 380884 kb
Host smart-8c30c857-e281-4716-ab73-ee36a409dbdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061010903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.2061010903
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2685792844
Short name T568
Test name
Test status
Simulation time 761618949 ps
CPU time 14.09 seconds
Started Dec 20 01:05:09 PM PST 23
Finished Dec 20 01:05:47 PM PST 23
Peak memory 208716 kb
Host smart-8ea4aa5e-1e16-445f-afea-874faa2dec80
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685792844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2685792844
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.75801129
Short name T631
Test name
Test status
Simulation time 41452040133 ps
CPU time 312.98 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:10:58 PM PST 23
Peak memory 202200 kb
Host smart-719e9117-260e-4f3b-8b5a-4a86a4bbbc0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75801129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_partial_access_b2b.75801129
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.797079986
Short name T544
Test name
Test status
Simulation time 2918620128 ps
CPU time 410.84 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:12:33 PM PST 23
Peak memory 357700 kb
Host smart-1f5f2fac-7cf5-4209-83a0-5a2081ca389c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797079986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.797079986
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.2030163103
Short name T485
Test name
Test status
Simulation time 1109421754 ps
CPU time 49.2 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:06:26 PM PST 23
Peak memory 299164 kb
Host smart-310deb3e-952f-410e-bb71-a418fd334639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030163103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2030163103
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.3944110470
Short name T918
Test name
Test status
Simulation time 277415625342 ps
CPU time 3258.74 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 02:00:06 PM PST 23
Peak memory 381224 kb
Host smart-8e81eb2b-3058-4d1e-a1c0-483c65141a74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944110470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.3944110470
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1451309228
Short name T382
Test name
Test status
Simulation time 1413605654 ps
CPU time 1721.03 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:34:29 PM PST 23
Peak memory 573532 kb
Host smart-7474c24f-8e5e-414e-87c9-0634fdcdb1bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1451309228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1451309228
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3410925245
Short name T834
Test name
Test status
Simulation time 11170086775 ps
CPU time 415.97 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:12:32 PM PST 23
Peak memory 202316 kb
Host smart-1ce45704-5fdf-4344-bbe2-2183053733c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410925245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.3410925245
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.744162383
Short name T782
Test name
Test status
Simulation time 4170784664 ps
CPU time 41.19 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:06:18 PM PST 23
Peak memory 261280 kb
Host smart-16e63df0-5b40-4a7b-8153-94b393e4675c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744162383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_throughput_w_partial_write.744162383
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2294941906
Short name T595
Test name
Test status
Simulation time 8608107615 ps
CPU time 873.78 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:20:19 PM PST 23
Peak memory 380068 kb
Host smart-a1d11c3c-e1f3-480f-8876-bbc4f0f7c359
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294941906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.2294941906
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2337737895
Short name T345
Test name
Test status
Simulation time 20773751 ps
CPU time 0.64 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:05:49 PM PST 23
Peak memory 202000 kb
Host smart-6df25ef0-8bfa-4eb3-b5ae-f347fed1912c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337737895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2337737895
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.3280580923
Short name T515
Test name
Test status
Simulation time 15111085956 ps
CPU time 916.88 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:21:02 PM PST 23
Peak memory 202224 kb
Host smart-e8c92f42-ce72-45d8-a769-b043041016a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280580923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.3280580923
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.2170091288
Short name T715
Test name
Test status
Simulation time 37783721572 ps
CPU time 820.76 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:19:26 PM PST 23
Peak memory 374000 kb
Host smart-9b3d8b18-8982-42d8-814b-16e3ae3228c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170091288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.2170091288
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.358160288
Short name T411
Test name
Test status
Simulation time 18330993030 ps
CPU time 88.68 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:07:11 PM PST 23
Peak memory 214108 kb
Host smart-4dfadee4-582e-45f6-9c35-0baa7ac56d42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358160288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc
alation.358160288
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.586143069
Short name T787
Test name
Test status
Simulation time 3686782223 ps
CPU time 74.67 seconds
Started Dec 20 01:05:28 PM PST 23
Finished Dec 20 01:07:01 PM PST 23
Peak memory 322964 kb
Host smart-58815b7d-0911-4c05-92de-0cf059586d57
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586143069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.sram_ctrl_max_throughput.586143069
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3385073036
Short name T111
Test name
Test status
Simulation time 957114517 ps
CPU time 71.98 seconds
Started Dec 20 01:05:28 PM PST 23
Finished Dec 20 01:06:58 PM PST 23
Peak memory 211204 kb
Host smart-a8613f7d-8622-4dfb-8466-a8738c3fcde9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385073036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.3385073036
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.1376539729
Short name T873
Test name
Test status
Simulation time 7904217468 ps
CPU time 125.07 seconds
Started Dec 20 01:05:22 PM PST 23
Finished Dec 20 01:07:47 PM PST 23
Peak memory 202164 kb
Host smart-ade10d96-b2cd-448d-91dd-ce27c0ce7e64
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376539729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.1376539729
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3807964504
Short name T578
Test name
Test status
Simulation time 17005572068 ps
CPU time 1059.42 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:23:23 PM PST 23
Peak memory 379024 kb
Host smart-d8d49ce2-c8a5-43e0-a3fa-5fd9d517ef73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807964504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3807964504
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.2194937990
Short name T256
Test name
Test status
Simulation time 1393156158 ps
CPU time 7.15 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:05:52 PM PST 23
Peak memory 203496 kb
Host smart-3d376e45-4a7e-4d2c-9ecf-4b272be24ca7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194937990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.2194937990
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.154984062
Short name T596
Test name
Test status
Simulation time 7938194259 ps
CPU time 474.65 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:13:39 PM PST 23
Peak memory 202232 kb
Host smart-ec6a6c03-028c-437d-bce6-e7dd0a650b48
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154984062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.sram_ctrl_partial_access_b2b.154984062
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.2027937484
Short name T731
Test name
Test status
Simulation time 2094893464 ps
CPU time 7.03 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:05:47 PM PST 23
Peak memory 202452 kb
Host smart-f9fc8234-f33b-4812-9729-685c2b252104
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027937484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2027937484
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.3092534133
Short name T860
Test name
Test status
Simulation time 9667638699 ps
CPU time 477.8 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:13:40 PM PST 23
Peak memory 378080 kb
Host smart-c8726fb5-5608-42b1-a73a-ecd762161499
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092534133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3092534133
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.463881021
Short name T634
Test name
Test status
Simulation time 1103750095 ps
CPU time 37.85 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:06:17 PM PST 23
Peak memory 291560 kb
Host smart-c9bd8d79-c846-412e-9c22-4ad534b851fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463881021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.463881021
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.4174005804
Short name T973
Test name
Test status
Simulation time 226815218565 ps
CPU time 1829.18 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:36:15 PM PST 23
Peak memory 384092 kb
Host smart-5f5a9ad3-3bc5-486f-875d-e7d017bea20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174005804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.4174005804
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1190042656
Short name T529
Test name
Test status
Simulation time 4531931045 ps
CPU time 4219.9 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 02:16:05 PM PST 23
Peak memory 554292 kb
Host smart-ea004b9f-dc21-44bf-8bba-790d858afccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1190042656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1190042656
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2295993982
Short name T313
Test name
Test status
Simulation time 17393501317 ps
CPU time 344.14 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:11:27 PM PST 23
Peak memory 202240 kb
Host smart-dfd00912-c86d-4a25-aea9-e679f628bce1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295993982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2295993982
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1418802307
Short name T101
Test name
Test status
Simulation time 745048531 ps
CPU time 38.32 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:06:20 PM PST 23
Peak memory 251260 kb
Host smart-a5e9f460-c739-476b-b946-f64b5166cd15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418802307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1418802307
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2999644636
Short name T357
Test name
Test status
Simulation time 10182479908 ps
CPU time 577.31 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:15:21 PM PST 23
Peak memory 340300 kb
Host smart-dce21b24-1028-428a-8268-c41845edaf6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999644636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.2999644636
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.2161300336
Short name T586
Test name
Test status
Simulation time 40094243 ps
CPU time 0.63 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:05:40 PM PST 23
Peak memory 201928 kb
Host smart-cb6df3fa-4c5d-404e-8b17-3d38b1123eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161300336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.2161300336
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.2230168952
Short name T581
Test name
Test status
Simulation time 50781331002 ps
CPU time 1135.75 seconds
Started Dec 20 01:05:33 PM PST 23
Finished Dec 20 01:24:45 PM PST 23
Peak memory 202064 kb
Host smart-33b9f712-021e-4940-98a5-efaeeb4ccfc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230168952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.2230168952
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.1743635531
Short name T698
Test name
Test status
Simulation time 11114755974 ps
CPU time 243.58 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:09:50 PM PST 23
Peak memory 210488 kb
Host smart-4ff5ac46-8811-4fa8-b904-27e1a45db5dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743635531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.1743635531
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.2586797243
Short name T329
Test name
Test status
Simulation time 788965498 ps
CPU time 51.66 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:06:38 PM PST 23
Peak memory 276180 kb
Host smart-4e19b489-86e1-4b7b-b201-d06cfee21d75
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586797243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.2586797243
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2390643508
Short name T638
Test name
Test status
Simulation time 6233240097 ps
CPU time 130.49 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:07:55 PM PST 23
Peak memory 211128 kb
Host smart-c02e9973-57a6-4de0-821a-5356b2b9050c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390643508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.2390643508
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.60507312
Short name T563
Test name
Test status
Simulation time 28132262298 ps
CPU time 241.26 seconds
Started Dec 20 01:05:07 PM PST 23
Finished Dec 20 01:09:33 PM PST 23
Peak memory 202344 kb
Host smart-f6323661-e9a6-423d-a6ea-b6f27e66c603
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60507312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_
mem_walk.60507312
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.906556064
Short name T854
Test name
Test status
Simulation time 18528821180 ps
CPU time 388.77 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:12:14 PM PST 23
Peak memory 328592 kb
Host smart-ef58df9a-484f-4df4-9840-2cadced03d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906556064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip
le_keys.906556064
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.3249975656
Short name T351
Test name
Test status
Simulation time 349918775 ps
CPU time 13.28 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:06:01 PM PST 23
Peak memory 202176 kb
Host smart-6bc70ca4-fd2f-4535-807d-572b4920a1c7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249975656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.3249975656
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1090514143
Short name T430
Test name
Test status
Simulation time 117137425827 ps
CPU time 742.01 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:18:07 PM PST 23
Peak memory 202120 kb
Host smart-d9c8e6b3-6fa0-4ecd-ad8f-a37be888e44b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090514143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.1090514143
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.2191753466
Short name T42
Test name
Test status
Simulation time 1305193636 ps
CPU time 13.47 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:06:03 PM PST 23
Peak memory 202392 kb
Host smart-48979608-f1f3-4818-bca6-f1b6205b4f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191753466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2191753466
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.178202571
Short name T861
Test name
Test status
Simulation time 37472089115 ps
CPU time 1073.54 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:23:43 PM PST 23
Peak memory 381120 kb
Host smart-3d8ed52d-e504-4bba-86ff-ded51fde058a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178202571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.178202571
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.3621138192
Short name T505
Test name
Test status
Simulation time 1031678822 ps
CPU time 47.33 seconds
Started Dec 20 01:05:22 PM PST 23
Finished Dec 20 01:06:29 PM PST 23
Peak memory 294256 kb
Host smart-e677c3df-e335-4d78-8092-da0bf0bb189b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621138192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3621138192
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.4263329184
Short name T853
Test name
Test status
Simulation time 141346117502 ps
CPU time 2167.28 seconds
Started Dec 20 01:05:16 PM PST 23
Finished Dec 20 01:41:45 PM PST 23
Peak memory 381076 kb
Host smart-b7b446d2-628e-4244-a621-6ff54edf402c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263329184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.4263329184
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.96676112
Short name T635
Test name
Test status
Simulation time 624437354 ps
CPU time 4281.02 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 02:16:54 PM PST 23
Peak memory 674360 kb
Host smart-7d25d511-8842-4828-844c-78cd25033e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=96676112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.96676112
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.230173509
Short name T894
Test name
Test status
Simulation time 9966396714 ps
CPU time 185.1 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:08:56 PM PST 23
Peak memory 202096 kb
Host smart-aeb98fbf-a489-4921-a13b-8e903d5cbbfc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230173509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.230173509
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.959133198
Short name T804
Test name
Test status
Simulation time 2797125668 ps
CPU time 184.63 seconds
Started Dec 20 01:05:45 PM PST 23
Finished Dec 20 01:09:06 PM PST 23
Peak memory 365916 kb
Host smart-0c04ad98-652d-475e-bb42-c994175a642f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959133198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.959133198
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.4032268951
Short name T520
Test name
Test status
Simulation time 22475995494 ps
CPU time 799.42 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:18:57 PM PST 23
Peak memory 377052 kb
Host smart-63886fa7-367a-4bf7-9db4-1ac43e158a86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032268951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.4032268951
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.2194418133
Short name T755
Test name
Test status
Simulation time 16794835 ps
CPU time 0.64 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:05:38 PM PST 23
Peak memory 201868 kb
Host smart-b677735a-4807-4a08-aa15-605093fbbc15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194418133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.2194418133
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1946936670
Short name T553
Test name
Test status
Simulation time 607158072667 ps
CPU time 2446.89 seconds
Started Dec 20 01:05:04 PM PST 23
Finished Dec 20 01:46:17 PM PST 23
Peak memory 202308 kb
Host smart-6dd8bc9a-1255-4795-99b8-a84ff933d639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946936670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1946936670
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.3761068080
Short name T370
Test name
Test status
Simulation time 5118671047 ps
CPU time 154.84 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:08:15 PM PST 23
Peak memory 376036 kb
Host smart-042dfc14-e7e4-4a7e-b5f0-5ae46d1602c1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761068080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.3761068080
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1930916296
Short name T807
Test name
Test status
Simulation time 4368508741 ps
CPU time 142.89 seconds
Started Dec 20 01:05:16 PM PST 23
Finished Dec 20 01:08:01 PM PST 23
Peak memory 210504 kb
Host smart-b888a473-2683-406d-bf67-a25119421240
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930916296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.1930916296
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.3321369892
Short name T133
Test name
Test status
Simulation time 1980167342 ps
CPU time 113.05 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:07:36 PM PST 23
Peak memory 201908 kb
Host smart-7488bf2a-ec62-4f0c-be1f-c35e5adc7275
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321369892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.3321369892
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.1079228958
Short name T16
Test name
Test status
Simulation time 50734541474 ps
CPU time 1371.11 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:28:31 PM PST 23
Peak memory 380292 kb
Host smart-2b8396a1-7ba6-404f-8ce5-b3a49e89d346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079228958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.1079228958
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.567920246
Short name T820
Test name
Test status
Simulation time 5522867719 ps
CPU time 109.3 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:07:34 PM PST 23
Peak memory 348576 kb
Host smart-32fd39d0-73a4-4277-aac8-288eabb34785
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567920246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.567920246
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.881168784
Short name T645
Test name
Test status
Simulation time 4818733910 ps
CPU time 309.05 seconds
Started Dec 20 01:05:11 PM PST 23
Finished Dec 20 01:10:44 PM PST 23
Peak memory 202260 kb
Host smart-bc2f55ea-3542-4e95-bead-778575e78c9d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881168784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.sram_ctrl_partial_access_b2b.881168784
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3418288301
Short name T961
Test name
Test status
Simulation time 364132839 ps
CPU time 6.49 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:05:43 PM PST 23
Peak memory 202444 kb
Host smart-b0c28b59-bc99-43b6-be02-3589ea7fc11c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418288301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3418288301
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.2736410810
Short name T510
Test name
Test status
Simulation time 11125237766 ps
CPU time 388.74 seconds
Started Dec 20 01:05:33 PM PST 23
Finished Dec 20 01:12:17 PM PST 23
Peak memory 366636 kb
Host smart-04c791fc-3e8e-411e-a4b6-3d726729cc81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736410810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2736410810
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.560722534
Short name T806
Test name
Test status
Simulation time 1925341196 ps
CPU time 140.85 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:08:05 PM PST 23
Peak memory 368752 kb
Host smart-2a12d459-abe0-4c9f-86bd-7d6bd458ff7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560722534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.560722534
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3598318438
Short name T913
Test name
Test status
Simulation time 95944897951 ps
CPU time 333.43 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:11:12 PM PST 23
Peak memory 202272 kb
Host smart-c4d5a959-9836-4488-b5d9-4bd80d5fbbd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598318438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.3598318438
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3785984021
Short name T628
Test name
Test status
Simulation time 3194966730 ps
CPU time 137.29 seconds
Started Dec 20 01:05:21 PM PST 23
Finished Dec 20 01:07:58 PM PST 23
Peak memory 340452 kb
Host smart-efb9d29e-511b-4166-ab00-eb33a6421da7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785984021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3785984021
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.934747954
Short name T82
Test name
Test status
Simulation time 9297626039 ps
CPU time 1039.46 seconds
Started Dec 20 01:05:42 PM PST 23
Finished Dec 20 01:23:16 PM PST 23
Peak memory 377088 kb
Host smart-1a16a775-a15d-4983-95d2-9e22ee6e9bd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934747954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 17.sram_ctrl_access_during_key_req.934747954
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.1560495713
Short name T419
Test name
Test status
Simulation time 64629034 ps
CPU time 0.65 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:05:50 PM PST 23
Peak memory 201936 kb
Host smart-05a07f92-5a04-4f31-9b6c-418731ebdaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560495713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.1560495713
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.765030657
Short name T678
Test name
Test status
Simulation time 655406244499 ps
CPU time 2285.25 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:43:53 PM PST 23
Peak memory 202224 kb
Host smart-5fb582ef-a43b-4950-9670-9f66d8c16922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765030657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.
765030657
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.2090844259
Short name T590
Test name
Test status
Simulation time 71409261336 ps
CPU time 833.9 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:19:42 PM PST 23
Peak memory 378352 kb
Host smart-f71beac3-05e5-4bf5-91ec-63eb6d397eb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090844259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.2090844259
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.281890114
Short name T615
Test name
Test status
Simulation time 57620150628 ps
CPU time 150.98 seconds
Started Dec 20 01:05:42 PM PST 23
Finished Dec 20 01:08:27 PM PST 23
Peak memory 210404 kb
Host smart-8b304bcb-0ae4-4210-a45e-b471aa9dbf33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281890114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc
alation.281890114
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.3537284722
Short name T504
Test name
Test status
Simulation time 2604317300 ps
CPU time 38.22 seconds
Started Dec 20 01:05:33 PM PST 23
Finished Dec 20 01:06:32 PM PST 23
Peak memory 257756 kb
Host smart-6345633a-ad3d-43ce-a465-6c42e5ab4926
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537284722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.3537284722
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2181681364
Short name T328
Test name
Test status
Simulation time 10095851648 ps
CPU time 81.39 seconds
Started Dec 20 01:05:28 PM PST 23
Finished Dec 20 01:07:07 PM PST 23
Peak memory 211624 kb
Host smart-4910e44b-0f73-497d-a504-88cf41a8e2bb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181681364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.2181681364
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.118935208
Short name T546
Test name
Test status
Simulation time 71745628858 ps
CPU time 328.67 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:11:20 PM PST 23
Peak memory 202172 kb
Host smart-12736798-98f9-4a57-a1b5-64460c56b728
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118935208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl
_mem_walk.118935208
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.102444582
Short name T943
Test name
Test status
Simulation time 11692784330 ps
CPU time 545.73 seconds
Started Dec 20 01:05:28 PM PST 23
Finished Dec 20 01:14:51 PM PST 23
Peak memory 380248 kb
Host smart-33da10a6-b03d-4cb1-a6a6-858d9eacde3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102444582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip
le_keys.102444582
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.4209597242
Short name T870
Test name
Test status
Simulation time 1209123643 ps
CPU time 27.9 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:06:05 PM PST 23
Peak memory 202092 kb
Host smart-8ddf8851-c0ce-4814-9a1f-53ef64fb1db7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209597242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.4209597242
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2380948339
Short name T457
Test name
Test status
Simulation time 18334047183 ps
CPU time 227.76 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:09:38 PM PST 23
Peak memory 202208 kb
Host smart-63657f4a-9d45-44d5-b1b3-b971eb7ded0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380948339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2380948339
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.2595961934
Short name T473
Test name
Test status
Simulation time 1404823486 ps
CPU time 5.35 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:05:53 PM PST 23
Peak memory 202260 kb
Host smart-38429a68-427b-4c96-a578-e86539ae6394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595961934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2595961934
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.3816427912
Short name T823
Test name
Test status
Simulation time 26307847033 ps
CPU time 650.52 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:16:42 PM PST 23
Peak memory 373176 kb
Host smart-cfc0e54a-5037-45b3-9104-925428053593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816427912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3816427912
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.1169773605
Short name T150
Test name
Test status
Simulation time 3897267354 ps
CPU time 24.08 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:06:09 PM PST 23
Peak memory 202212 kb
Host smart-419d6ab8-9038-4471-be9a-0bfbe30513bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169773605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1169773605
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1742815995
Short name T248
Test name
Test status
Simulation time 3248384573 ps
CPU time 1672.1 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:33:48 PM PST 23
Peak memory 414980 kb
Host smart-cfd779ca-4271-43b1-8dea-1c6ea0e1851c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1742815995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1742815995
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.4006496015
Short name T480
Test name
Test status
Simulation time 17228683793 ps
CPU time 296.32 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:10:38 PM PST 23
Peak memory 202192 kb
Host smart-53ddeef5-9cea-4b3a-822e-82116cfbe0d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006496015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.4006496015
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2052829614
Short name T293
Test name
Test status
Simulation time 1209871682 ps
CPU time 155.23 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:08:24 PM PST 23
Peak memory 375220 kb
Host smart-0fe3c2de-796e-4f3b-9468-1cb19077ec90
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052829614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2052829614
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3164818
Short name T887
Test name
Test status
Simulation time 12583546781 ps
CPU time 777.64 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:18:49 PM PST 23
Peak memory 380216 kb
Host smart-2afecebc-b310-45d8-9b0e-806aa1736083
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_access_during_key_req.3164818
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.1629769846
Short name T743
Test name
Test status
Simulation time 16728121 ps
CPU time 0.63 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:05:55 PM PST 23
Peak memory 201500 kb
Host smart-771af7dc-4747-4e15-ab20-8c56f0043f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629769846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.1629769846
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.2759109020
Short name T605
Test name
Test status
Simulation time 26908122941 ps
CPU time 915.59 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:21:03 PM PST 23
Peak memory 202068 kb
Host smart-474591e4-345a-450c-bda5-c1c393152c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759109020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.2759109020
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.4194132797
Short name T322
Test name
Test status
Simulation time 694529024 ps
CPU time 26.68 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:06:19 PM PST 23
Peak memory 216912 kb
Host smart-9d80ba3e-7975-47ef-ac9a-e6ae6c980fc7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194132797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.4194132797
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2168259424
Short name T391
Test name
Test status
Simulation time 17973522921 ps
CPU time 81.72 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:07:16 PM PST 23
Peak memory 218548 kb
Host smart-55409cdd-27bc-427d-83fe-0420bdf215d0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168259424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.2168259424
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.511852295
Short name T288
Test name
Test status
Simulation time 9384802972 ps
CPU time 235.52 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:09:48 PM PST 23
Peak memory 202188 kb
Host smart-6f6200ce-7789-48c1-bf90-05c26df31339
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511852295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.511852295
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.1884142569
Short name T610
Test name
Test status
Simulation time 5354171825 ps
CPU time 812.89 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:19:24 PM PST 23
Peak memory 369896 kb
Host smart-f9ea0628-8017-4cb8-8566-2ad4032a2bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884142569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.1884142569
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2931025898
Short name T14
Test name
Test status
Simulation time 2335634440 ps
CPU time 88.46 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:07:20 PM PST 23
Peak memory 339232 kb
Host smart-03fc5b51-89f6-4d79-b05c-ace8d05a3b80
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931025898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2931025898
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1777981047
Short name T612
Test name
Test status
Simulation time 16400755917 ps
CPU time 291.54 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:10:42 PM PST 23
Peak memory 202328 kb
Host smart-ae2a9f56-5428-4333-8200-0d4754a0d660
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777981047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.1777981047
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.2264145226
Short name T775
Test name
Test status
Simulation time 383801921 ps
CPU time 13.08 seconds
Started Dec 20 01:05:28 PM PST 23
Finished Dec 20 01:05:59 PM PST 23
Peak memory 202436 kb
Host smart-ff037f57-4b4f-4c48-8941-ffdd3f3dd0a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264145226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2264145226
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.2492242733
Short name T797
Test name
Test status
Simulation time 40038948027 ps
CPU time 585.38 seconds
Started Dec 20 01:05:40 PM PST 23
Finished Dec 20 01:15:41 PM PST 23
Peak memory 364208 kb
Host smart-f164f9dd-7316-4c52-8182-93b5d3523884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492242733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2492242733
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.3257709788
Short name T285
Test name
Test status
Simulation time 2115770495 ps
CPU time 119.1 seconds
Started Dec 20 01:05:48 PM PST 23
Finished Dec 20 01:08:03 PM PST 23
Peak memory 362672 kb
Host smart-a879285c-6ccf-42be-8487-656ef3e95222
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257709788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3257709788
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1533336453
Short name T260
Test name
Test status
Simulation time 1176517283 ps
CPU time 2487.35 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:47:15 PM PST 23
Peak memory 676028 kb
Host smart-723bfd57-ad15-4138-b87e-4ccbd2ac48a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1533336453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1533336453
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.4156631815
Short name T498
Test name
Test status
Simulation time 22174965221 ps
CPU time 405.4 seconds
Started Dec 20 01:05:44 PM PST 23
Finished Dec 20 01:12:45 PM PST 23
Peak memory 202204 kb
Host smart-3bbaa66f-2071-4815-bcce-6c3cac8596d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156631815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.4156631815
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3301473265
Short name T789
Test name
Test status
Simulation time 14302151320 ps
CPU time 47.5 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:06:41 PM PST 23
Peak memory 273264 kb
Host smart-67d2e533-e02b-46c3-9cf1-6421a47db09c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301473265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3301473265
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3403072161
Short name T739
Test name
Test status
Simulation time 6789379815 ps
CPU time 757.48 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:18:30 PM PST 23
Peak memory 373048 kb
Host smart-9f6bee2e-740c-442e-8276-6447f02e706a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403072161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3403072161
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.1335599199
Short name T990
Test name
Test status
Simulation time 34523958 ps
CPU time 0.65 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:05:52 PM PST 23
Peak memory 201940 kb
Host smart-10b14b11-a0df-4598-91a3-e98afa3deef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335599199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.1335599199
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.1622393767
Short name T727
Test name
Test status
Simulation time 105681230732 ps
CPU time 535.44 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:14:46 PM PST 23
Peak memory 202212 kb
Host smart-cf60c7a9-d609-4670-9259-0a2fc907ee22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622393767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.1622393767
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.736081228
Short name T354
Test name
Test status
Simulation time 11516896425 ps
CPU time 300.54 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:10:51 PM PST 23
Peak memory 210356 kb
Host smart-02855877-5be1-4327-aae8-c83bb8e87fda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736081228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esc
alation.736081228
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.4110955251
Short name T875
Test name
Test status
Simulation time 3175678010 ps
CPU time 177.04 seconds
Started Dec 20 01:05:33 PM PST 23
Finished Dec 20 01:08:46 PM PST 23
Peak memory 365900 kb
Host smart-73781c7f-fb4f-40c7-a3c4-d15a7e36c974
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110955251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.4110955251
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2641393233
Short name T369
Test name
Test status
Simulation time 26649806056 ps
CPU time 78.89 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:07:30 PM PST 23
Peak memory 218512 kb
Host smart-6eb795a7-2558-43f8-885e-29caf7f08281
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641393233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.2641393233
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2891660586
Short name T254
Test name
Test status
Simulation time 7892112760 ps
CPU time 128.71 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:08:05 PM PST 23
Peak memory 202212 kb
Host smart-1fe042e0-0aeb-486a-b7af-00c9d7950101
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891660586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2891660586
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.3874361089
Short name T977
Test name
Test status
Simulation time 33744070442 ps
CPU time 1172.69 seconds
Started Dec 20 01:05:40 PM PST 23
Finished Dec 20 01:25:28 PM PST 23
Peak memory 375048 kb
Host smart-5943a95b-f5ff-4db7-987c-6432a6000f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874361089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.3874361089
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.1729592766
Short name T484
Test name
Test status
Simulation time 2410962117 ps
CPU time 10.73 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:06:01 PM PST 23
Peak memory 202204 kb
Host smart-9fc4917d-0b48-4010-8133-b8089aa9971d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729592766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.1729592766
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.141180520
Short name T100
Test name
Test status
Simulation time 8356090437 ps
CPU time 449.45 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:13:20 PM PST 23
Peak memory 202160 kb
Host smart-d7b725bc-d45d-4405-8088-3ee263575db6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141180520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.sram_ctrl_partial_access_b2b.141180520
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.247316540
Short name T409
Test name
Test status
Simulation time 1475518710 ps
CPU time 14.11 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:06:05 PM PST 23
Peak memory 202480 kb
Host smart-780be74c-8cad-4355-b220-a356e4d66855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247316540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.247316540
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2970030883
Short name T524
Test name
Test status
Simulation time 4401010523 ps
CPU time 652.52 seconds
Started Dec 20 01:05:40 PM PST 23
Finished Dec 20 01:16:47 PM PST 23
Peak memory 378104 kb
Host smart-7fd7f229-930e-4a5f-97ce-a7dec142731a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970030883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2970030883
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.862986571
Short name T305
Test name
Test status
Simulation time 1546666936 ps
CPU time 15.3 seconds
Started Dec 20 01:05:43 PM PST 23
Finished Dec 20 01:06:13 PM PST 23
Peak memory 213776 kb
Host smart-f9c34c73-a5c2-4718-8820-8f0331f499e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862986571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.862986571
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.3832745570
Short name T648
Test name
Test status
Simulation time 169541209666 ps
CPU time 2811.71 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:52:45 PM PST 23
Peak memory 381212 kb
Host smart-f728e97b-ffa6-4727-bd7c-dd489cf3ec18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832745570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.3832745570
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3107335162
Short name T813
Test name
Test status
Simulation time 5533064008 ps
CPU time 2736.04 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:51:29 PM PST 23
Peak memory 609000 kb
Host smart-ee77a8e8-d334-4f02-91b5-6f7f5176c7dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3107335162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3107335162
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.648898062
Short name T580
Test name
Test status
Simulation time 3440494194 ps
CPU time 289.61 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:10:44 PM PST 23
Peak memory 202264 kb
Host smart-fd124d5f-3c9f-40f0-873a-d5ba1173a0e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648898062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_stress_pipeline.648898062
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.805675602
Short name T18
Test name
Test status
Simulation time 763756345 ps
CPU time 65.87 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:06:59 PM PST 23
Peak memory 313164 kb
Host smart-fd96173f-49da-4dde-92a6-a9919f5320c6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805675602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.805675602
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2316703344
Short name T407
Test name
Test status
Simulation time 13015190851 ps
CPU time 863.16 seconds
Started Dec 20 01:04:55 PM PST 23
Finished Dec 20 01:19:44 PM PST 23
Peak memory 375020 kb
Host smart-9ea69470-53da-4f85-96d4-bb000f52e661
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316703344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.2316703344
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.2853256663
Short name T589
Test name
Test status
Simulation time 15326421 ps
CPU time 0.66 seconds
Started Dec 20 01:04:55 PM PST 23
Finished Dec 20 01:05:22 PM PST 23
Peak memory 201804 kb
Host smart-64d09d72-4ebc-4a6e-9432-bab15d8e14f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853256663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.2853256663
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.3467726599
Short name T401
Test name
Test status
Simulation time 189971138552 ps
CPU time 1854.72 seconds
Started Dec 20 01:05:16 PM PST 23
Finished Dec 20 01:36:32 PM PST 23
Peak memory 202188 kb
Host smart-481ce798-294d-4169-bf03-94fcaee950e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467726599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
3467726599
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.1538660789
Short name T477
Test name
Test status
Simulation time 7930531786 ps
CPU time 84.38 seconds
Started Dec 20 01:04:57 PM PST 23
Finished Dec 20 01:06:49 PM PST 23
Peak memory 210312 kb
Host smart-e879e250-9151-4cc8-b7c2-894af272d329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538660789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.1538660789
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.2640065018
Short name T791
Test name
Test status
Simulation time 2836006822 ps
CPU time 45.43 seconds
Started Dec 20 01:04:47 PM PST 23
Finished Dec 20 01:05:51 PM PST 23
Peak memory 276784 kb
Host smart-5aedabb8-79ec-449d-adb0-29613e4b49d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640065018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.2640065018
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2303850958
Short name T296
Test name
Test status
Simulation time 1596087488 ps
CPU time 129.56 seconds
Started Dec 20 01:04:59 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 211168 kb
Host smart-515d66ef-b617-4a70-bd82-d4aa1c09c73d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303850958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.2303850958
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.152489167
Short name T904
Test name
Test status
Simulation time 8228248181 ps
CPU time 126.66 seconds
Started Dec 20 01:04:55 PM PST 23
Finished Dec 20 01:07:27 PM PST 23
Peak memory 202204 kb
Host smart-4b5056bd-5b81-41fc-9f6c-2bfb151cc19f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152489167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
mem_walk.152489167
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.95174580
Short name T718
Test name
Test status
Simulation time 5049663079 ps
CPU time 767.9 seconds
Started Dec 20 01:05:01 PM PST 23
Finished Dec 20 01:18:15 PM PST 23
Peak memory 381216 kb
Host smart-6d21dd0d-c0b3-42c9-aa7b-3825c03b7348
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95174580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple
_keys.95174580
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.3027724587
Short name T991
Test name
Test status
Simulation time 1703957529 ps
CPU time 31.65 seconds
Started Dec 20 01:05:06 PM PST 23
Finished Dec 20 01:06:02 PM PST 23
Peak memory 202176 kb
Host smart-53d8db89-2de0-4923-9811-8141a198f0ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027724587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.3027724587
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.769885209
Short name T481
Test name
Test status
Simulation time 61194193681 ps
CPU time 362.7 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:11:28 PM PST 23
Peak memory 202244 kb
Host smart-c1b14df5-2343-41f3-a95d-cd86511127bf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769885209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.sram_ctrl_partial_access_b2b.769885209
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.1286436324
Short name T968
Test name
Test status
Simulation time 1690187480 ps
CPU time 5.62 seconds
Started Dec 20 01:04:47 PM PST 23
Finished Dec 20 01:05:11 PM PST 23
Peak memory 202612 kb
Host smart-0e346e1d-5694-4a1d-9c6c-0588ad1e0bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286436324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1286436324
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.2329151431
Short name T764
Test name
Test status
Simulation time 12440166467 ps
CPU time 886.33 seconds
Started Dec 20 01:04:47 PM PST 23
Finished Dec 20 01:19:52 PM PST 23
Peak memory 379028 kb
Host smart-8f8c78d8-7327-47ce-a983-90830e59d68f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329151431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2329151431
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.1097765498
Short name T38
Test name
Test status
Simulation time 450405296 ps
CPU time 3.75 seconds
Started Dec 20 01:04:51 PM PST 23
Finished Dec 20 01:05:15 PM PST 23
Peak memory 220972 kb
Host smart-2162b3f5-357a-4df6-a662-99eb58ac577e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097765498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.1097765498
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1148941462
Short name T625
Test name
Test status
Simulation time 1166490114 ps
CPU time 22.32 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:06:07 PM PST 23
Peak memory 202168 kb
Host smart-c37d18b3-f8e4-468b-90b1-b701060c31f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148941462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1148941462
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.3344285518
Short name T545
Test name
Test status
Simulation time 494332411870 ps
CPU time 5597.79 seconds
Started Dec 20 01:04:59 PM PST 23
Finished Dec 20 02:38:44 PM PST 23
Peak memory 377212 kb
Host smart-8fa63e13-4451-4ec4-be85-871fc201e376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344285518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.3344285518
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.413064289
Short name T265
Test name
Test status
Simulation time 1497987436 ps
CPU time 1892.98 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:36:55 PM PST 23
Peak memory 420104 kb
Host smart-50c7867f-2622-4cfd-8f2e-4cead7b85aab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=413064289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.413064289
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.459916021
Short name T405
Test name
Test status
Simulation time 43112592278 ps
CPU time 214.83 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:09:13 PM PST 23
Peak memory 202196 kb
Host smart-e3207f70-a3fb-4df6-9624-a5e24079a164
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459916021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_stress_pipeline.459916021
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.231049765
Short name T749
Test name
Test status
Simulation time 3001691623 ps
CPU time 41.89 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:06:14 PM PST 23
Peak memory 267480 kb
Host smart-ff827c33-5c80-44f0-8569-820168f4120e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231049765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.231049765
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2931216474
Short name T400
Test name
Test status
Simulation time 7451748441 ps
CPU time 1096.05 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:24:15 PM PST 23
Peak memory 380208 kb
Host smart-43854ce4-4c93-4793-a73b-9f72b9f9072b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931216474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2931216474
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.2133080957
Short name T298
Test name
Test status
Simulation time 88572610 ps
CPU time 0.63 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:05:58 PM PST 23
Peak memory 201888 kb
Host smart-b1293358-6977-49c0-9c3d-74b29643e2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133080957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.2133080957
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.3271502211
Short name T700
Test name
Test status
Simulation time 41532278780 ps
CPU time 1328.81 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:28:05 PM PST 23
Peak memory 202240 kb
Host smart-00f23f1e-2598-4d6e-aa9d-1e1788a834b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271502211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.3271502211
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.2708533788
Short name T876
Test name
Test status
Simulation time 38992588426 ps
CPU time 1137.62 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:24:54 PM PST 23
Peak memory 373112 kb
Host smart-680cdb5a-8fe3-4264-8e39-6c6e145a38a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708533788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.2708533788
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.639566070
Short name T856
Test name
Test status
Simulation time 136035034862 ps
CPU time 248.35 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:10:02 PM PST 23
Peak memory 210516 kb
Host smart-48873242-f7d1-4f53-a21a-7c4001e4c23a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639566070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc
alation.639566070
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1385898796
Short name T796
Test name
Test status
Simulation time 888661993 ps
CPU time 141.44 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:08:18 PM PST 23
Peak memory 361348 kb
Host smart-c4cb010b-08b5-4c18-995e-a3eef900f5d2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385898796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1385898796
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2244864637
Short name T314
Test name
Test status
Simulation time 11082087520 ps
CPU time 81.48 seconds
Started Dec 20 01:05:47 PM PST 23
Finished Dec 20 01:07:25 PM PST 23
Peak memory 211572 kb
Host smart-e1149713-2f54-4578-ab34-41eec7bba07e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244864637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2244864637
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.2870782324
Short name T397
Test name
Test status
Simulation time 23241795230 ps
CPU time 311.49 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:11:03 PM PST 23
Peak memory 202208 kb
Host smart-a4c1e1f6-e171-4338-8113-fa1d70376ccb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870782324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.2870782324
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.130291948
Short name T349
Test name
Test status
Simulation time 240591543013 ps
CPU time 478.19 seconds
Started Dec 20 01:05:51 PM PST 23
Finished Dec 20 01:14:04 PM PST 23
Peak memory 352224 kb
Host smart-adf9a206-62dd-4c8b-80f2-8ca7e3c84a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130291948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.130291948
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.3699447173
Short name T249
Test name
Test status
Simulation time 6915976870 ps
CPU time 24.19 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:06:17 PM PST 23
Peak memory 202312 kb
Host smart-27f51ba5-8277-43f0-986c-92c066748ed8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699447173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.3699447173
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3608754350
Short name T105
Test name
Test status
Simulation time 25199467716 ps
CPU time 630.95 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:16:37 PM PST 23
Peak memory 202224 kb
Host smart-59c03775-97dc-4d80-8fee-09f1fa80df94
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608754350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.3608754350
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.4284212410
Short name T264
Test name
Test status
Simulation time 359116709 ps
CPU time 13.41 seconds
Started Dec 20 01:05:45 PM PST 23
Finished Dec 20 01:06:14 PM PST 23
Peak memory 202472 kb
Host smart-aebb7539-1c5d-4442-a672-ab102dc635d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284212410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.4284212410
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.2993704037
Short name T800
Test name
Test status
Simulation time 51934423175 ps
CPU time 823.67 seconds
Started Dec 20 01:05:52 PM PST 23
Finished Dec 20 01:19:51 PM PST 23
Peak memory 377936 kb
Host smart-fa20a37f-3fee-4416-9333-9f7d5c7094e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993704037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2993704037
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.1374208499
Short name T588
Test name
Test status
Simulation time 2327059095 ps
CPU time 9.69 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:05:57 PM PST 23
Peak memory 202168 kb
Host smart-0b8d0671-d348-45f9-b460-897969ba6a87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374208499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1374208499
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.1679568310
Short name T798
Test name
Test status
Simulation time 369584140210 ps
CPU time 2747.11 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:51:43 PM PST 23
Peak memory 381112 kb
Host smart-eeb286c8-3efe-464c-b9a3-45cd0179f262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679568310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.1679568310
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.345510598
Short name T113
Test name
Test status
Simulation time 4706427750 ps
CPU time 3345.79 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 02:01:36 PM PST 23
Peak memory 654516 kb
Host smart-77f94988-15f5-4c35-b40c-58e92b0f262b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=345510598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.345510598
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1126823786
Short name T107
Test name
Test status
Simulation time 25444031069 ps
CPU time 469.56 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:13:42 PM PST 23
Peak memory 202252 kb
Host smart-53f87172-c7cb-463a-a6de-0b0027f98806
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126823786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1126823786
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.898923479
Short name T633
Test name
Test status
Simulation time 2691784757 ps
CPU time 29.39 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:06:24 PM PST 23
Peak memory 217756 kb
Host smart-58cd069a-4a07-4f1e-a08e-602cad260650
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898923479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.898923479
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.532657222
Short name T486
Test name
Test status
Simulation time 29628858468 ps
CPU time 488.37 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:13:56 PM PST 23
Peak memory 377996 kb
Host smart-d9798698-b4bc-4fdd-8f6f-1144413e7596
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532657222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.sram_ctrl_access_during_key_req.532657222
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.2470608078
Short name T667
Test name
Test status
Simulation time 117204410 ps
CPU time 0.68 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:06:06 PM PST 23
Peak memory 201920 kb
Host smart-21a11af9-b704-4c26-85fe-9a0097b019c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470608078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.2470608078
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.2921344541
Short name T626
Test name
Test status
Simulation time 231798587840 ps
CPU time 2083.86 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:40:36 PM PST 23
Peak memory 202252 kb
Host smart-501abd2f-b101-4de6-9287-e05077a41e91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921344541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2921344541
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.1051038271
Short name T606
Test name
Test status
Simulation time 47234722657 ps
CPU time 770.7 seconds
Started Dec 20 01:05:42 PM PST 23
Finished Dec 20 01:18:47 PM PST 23
Peak memory 373004 kb
Host smart-b0a8fe1b-1c71-4fe0-ba6a-d336134c97ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051038271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.1051038271
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.1147076668
Short name T699
Test name
Test status
Simulation time 10083757817 ps
CPU time 119 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:07:46 PM PST 23
Peak memory 210476 kb
Host smart-c2272f57-6a74-4220-a788-e92f21a8d031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147076668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.1147076668
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.2461003153
Short name T930
Test name
Test status
Simulation time 1646337847 ps
CPU time 138.3 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:08:08 PM PST 23
Peak memory 356608 kb
Host smart-f3d51c34-09a6-4b67-a9a8-c474b47da2a5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461003153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.2461003153
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3394383561
Short name T85
Test name
Test status
Simulation time 3014508503 ps
CPU time 76.37 seconds
Started Dec 20 01:05:51 PM PST 23
Finished Dec 20 01:07:23 PM PST 23
Peak memory 211240 kb
Host smart-2995f9ed-5d3c-4b8f-b91b-45a7799b722b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394383561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.3394383561
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.1962170229
Short name T885
Test name
Test status
Simulation time 196615184170 ps
CPU time 312.73 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:11:04 PM PST 23
Peak memory 202188 kb
Host smart-2dde7c2e-d490-4510-b099-e46f359da335
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962170229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.1962170229
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.3841501011
Short name T967
Test name
Test status
Simulation time 15619116202 ps
CPU time 1051.11 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:23:25 PM PST 23
Peak memory 380256 kb
Host smart-723335cf-2376-471d-a304-1814282c8422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841501011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.3841501011
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.2449283438
Short name T910
Test name
Test status
Simulation time 1245035186 ps
CPU time 28.7 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:06:39 PM PST 23
Peak memory 252800 kb
Host smart-99f88073-ad1d-4e33-b007-f0b7edf0f123
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449283438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.2449283438
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.382742757
Short name T387
Test name
Test status
Simulation time 18564309765 ps
CPU time 465.78 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:13:39 PM PST 23
Peak memory 202184 kb
Host smart-c9a71985-0354-4df4-a19a-1b2c926d096b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382742757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.sram_ctrl_partial_access_b2b.382742757
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3966786621
Short name T681
Test name
Test status
Simulation time 1406953914 ps
CPU time 13.92 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:06:03 PM PST 23
Peak memory 202444 kb
Host smart-5bf69b64-aa07-4e14-add1-1e41a79d8c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966786621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3966786621
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.273332014
Short name T17
Test name
Test status
Simulation time 40548324648 ps
CPU time 1448.94 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:30:05 PM PST 23
Peak memory 380152 kb
Host smart-c7580633-dc82-4ca2-b20f-120cae77e30f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273332014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.273332014
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3204653911
Short name T839
Test name
Test status
Simulation time 3209897893 ps
CPU time 133.77 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:08:05 PM PST 23
Peak memory 365116 kb
Host smart-57ae9be2-6724-484d-b9ab-5c6c4f87677e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204653911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3204653911
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2335918533
Short name T343
Test name
Test status
Simulation time 1726371520 ps
CPU time 3597.75 seconds
Started Dec 20 01:05:46 PM PST 23
Finished Dec 20 02:06:00 PM PST 23
Peak memory 698648 kb
Host smart-a490bebf-47bf-4357-afb1-08796f22af75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2335918533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2335918533
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3503063501
Short name T742
Test name
Test status
Simulation time 6180021893 ps
CPU time 383.95 seconds
Started Dec 20 01:05:43 PM PST 23
Finished Dec 20 01:12:22 PM PST 23
Peak memory 202252 kb
Host smart-8a88dcf3-9496-4ea9-9c04-8942fd068adf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503063501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.3503063501
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.622520369
Short name T901
Test name
Test status
Simulation time 1511462594 ps
CPU time 91.59 seconds
Started Dec 20 01:05:47 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 322072 kb
Host smart-0db4f8eb-5303-46bd-8266-2067b7525a46
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622520369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.622520369
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2923628241
Short name T828
Test name
Test status
Simulation time 6194521241 ps
CPU time 694.89 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:17:26 PM PST 23
Peak memory 376932 kb
Host smart-aed44d3f-da9c-4c19-9129-799c273af739
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923628241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.2923628241
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.3153925536
Short name T538
Test name
Test status
Simulation time 16392202 ps
CPU time 0.64 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:05:48 PM PST 23
Peak memory 201816 kb
Host smart-be5523a6-41fe-486b-82c0-fff67ea06de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153925536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.3153925536
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.764827923
Short name T506
Test name
Test status
Simulation time 736304449363 ps
CPU time 2402.19 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:45:54 PM PST 23
Peak memory 202188 kb
Host smart-2efa6246-6b93-4f64-a5de-87d0ba5c1302
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764827923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.
764827923
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.479683409
Short name T432
Test name
Test status
Simulation time 47258098950 ps
CPU time 77.02 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:07:05 PM PST 23
Peak memory 210432 kb
Host smart-0f2fed5c-be46-43ce-979e-0e9476f8359c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479683409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc
alation.479683409
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.2696354752
Short name T472
Test name
Test status
Simulation time 1461057510 ps
CPU time 64.49 seconds
Started Dec 20 01:05:42 PM PST 23
Finished Dec 20 01:07:01 PM PST 23
Peak memory 305448 kb
Host smart-355cad33-53fe-4f6e-a688-82967a9638e3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696354752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.2696354752
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.271290758
Short name T497
Test name
Test status
Simulation time 9642507925 ps
CPU time 79.59 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:07:13 PM PST 23
Peak memory 211180 kb
Host smart-bf895e24-be0c-4755-a873-bbbf6d4d508c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271290758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_mem_partial_access.271290758
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3089665993
Short name T559
Test name
Test status
Simulation time 4065841236 ps
CPU time 243.65 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:09:55 PM PST 23
Peak memory 202188 kb
Host smart-a785e645-d38a-4058-9a3a-fe3efb9e059f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089665993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3089665993
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.2184826746
Short name T574
Test name
Test status
Simulation time 9361225877 ps
CPU time 628.54 seconds
Started Dec 20 01:05:38 PM PST 23
Finished Dec 20 01:16:21 PM PST 23
Peak memory 378092 kb
Host smart-728c9a9d-f74a-4364-8a96-9cc479074a5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184826746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.2184826746
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.2898344700
Short name T438
Test name
Test status
Simulation time 2730970665 ps
CPU time 13.32 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:06:01 PM PST 23
Peak memory 202140 kb
Host smart-a47b2e42-1659-47e9-abbb-4b820fbcafa0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898344700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.2898344700
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2585219346
Short name T914
Test name
Test status
Simulation time 6949977417 ps
CPU time 159.98 seconds
Started Dec 20 01:05:46 PM PST 23
Finished Dec 20 01:08:42 PM PST 23
Peak memory 202068 kb
Host smart-61aef707-a179-4e2f-8168-7092882df212
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585219346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.2585219346
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.1396204156
Short name T688
Test name
Test status
Simulation time 4176594954 ps
CPU time 6.5 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:05:54 PM PST 23
Peak memory 202576 kb
Host smart-7057e13c-2fb6-47ed-98cd-9cadaef83330
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396204156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1396204156
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.724407371
Short name T822
Test name
Test status
Simulation time 58945480151 ps
CPU time 1169.01 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:25:22 PM PST 23
Peak memory 378108 kb
Host smart-1fe7e7ac-139d-4be3-a71f-f41141b86fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724407371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.724407371
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.1541491329
Short name T561
Test name
Test status
Simulation time 2085342521 ps
CPU time 38.15 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:06:25 PM PST 23
Peak memory 286732 kb
Host smart-5c74e4cc-fe8d-4cd9-9702-536c04c69779
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541491329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1541491329
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.9862498
Short name T503
Test name
Test status
Simulation time 188399937656 ps
CPU time 1626.29 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:32:53 PM PST 23
Peak memory 377144 kb
Host smart-8cfb4483-b7ff-441d-88a6-dcc83132a28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9862498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_stress_all.9862498
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1551211743
Short name T765
Test name
Test status
Simulation time 8667099337 ps
CPU time 2747.34 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:51:36 PM PST 23
Peak memory 677312 kb
Host smart-ba1816cc-3525-4dd6-9773-dd3aef850a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1551211743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1551211743
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.131435997
Short name T603
Test name
Test status
Simulation time 15382520019 ps
CPU time 275.8 seconds
Started Dec 20 01:05:35 PM PST 23
Finished Dec 20 01:10:26 PM PST 23
Peak memory 202252 kb
Host smart-5981a06d-7cb8-4092-aa7b-e32fcbb3dcaf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131435997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.131435997
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2396149581
Short name T846
Test name
Test status
Simulation time 795551928 ps
CPU time 141.76 seconds
Started Dec 20 01:05:33 PM PST 23
Finished Dec 20 01:08:10 PM PST 23
Peak memory 353380 kb
Host smart-f201c3bf-d91d-413f-896a-350f0d41b51b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396149581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2396149581
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3672381165
Short name T519
Test name
Test status
Simulation time 2116505435 ps
CPU time 236.37 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:09:41 PM PST 23
Peak memory 375036 kb
Host smart-fee37093-b6cb-404b-9eb1-770bae9d12db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672381165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.3672381165
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.953171510
Short name T270
Test name
Test status
Simulation time 14590413 ps
CPU time 0.63 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:06:11 PM PST 23
Peak memory 201580 kb
Host smart-69eb6f99-6c83-4b51-a358-2ea9dbf72aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953171510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.953171510
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.2884751150
Short name T376
Test name
Test status
Simulation time 34223561084 ps
CPU time 608.08 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:15:56 PM PST 23
Peak memory 202180 kb
Host smart-48562318-10e9-4a7b-bbcd-cfbc0a9ad3f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884751150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.2884751150
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.1954560102
Short name T770
Test name
Test status
Simulation time 86919594825 ps
CPU time 802.77 seconds
Started Dec 20 01:05:31 PM PST 23
Finished Dec 20 01:19:11 PM PST 23
Peak memory 379132 kb
Host smart-77c91146-b976-49b8-9a92-9d8e847644a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954560102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.1954560102
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.3727303426
Short name T7
Test name
Test status
Simulation time 2410963285 ps
CPU time 30.2 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:06:19 PM PST 23
Peak memory 210404 kb
Host smart-00ffa8a6-9e5d-4c39-bc3d-307c084aaab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727303426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.3727303426
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.2187016553
Short name T512
Test name
Test status
Simulation time 3682513232 ps
CPU time 86.3 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:07:16 PM PST 23
Peak memory 327588 kb
Host smart-a35c57a8-d9ea-4ae7-bb76-8e40a1f8cf6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187016553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.2187016553
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3955074412
Short name T840
Test name
Test status
Simulation time 950501755 ps
CPU time 74.05 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:07:09 PM PST 23
Peak memory 211084 kb
Host smart-9eaba112-f080-42e5-a1d3-c6479b8c63c3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955074412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.3955074412
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2690993186
Short name T906
Test name
Test status
Simulation time 7185442286 ps
CPU time 143.76 seconds
Started Dec 20 01:05:37 PM PST 23
Finished Dec 20 01:08:20 PM PST 23
Peak memory 202212 kb
Host smart-62e25d76-43f8-4c72-80a2-949ef47c46de
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690993186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2690993186
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.3838740289
Short name T13
Test name
Test status
Simulation time 10016058908 ps
CPU time 139.47 seconds
Started Dec 20 01:05:30 PM PST 23
Finished Dec 20 01:08:07 PM PST 23
Peak memory 348404 kb
Host smart-4d9f4dc9-2a98-42da-a0a1-eb3c50719511
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838740289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.3838740289
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.2867765943
Short name T429
Test name
Test status
Simulation time 747656029 ps
CPU time 68.12 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:06:56 PM PST 23
Peak memory 307424 kb
Host smart-ebcb65a5-1b6e-42be-bb28-d5414252082c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867765943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.2867765943
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1453196268
Short name T702
Test name
Test status
Simulation time 5989459168 ps
CPU time 356.3 seconds
Started Dec 20 01:05:41 PM PST 23
Finished Dec 20 01:11:52 PM PST 23
Peak memory 202236 kb
Host smart-4b433636-9708-4da2-9d8d-fd89b652ad1e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453196268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.1453196268
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2742533723
Short name T576
Test name
Test status
Simulation time 453298691 ps
CPU time 5.85 seconds
Started Dec 20 01:05:46 PM PST 23
Finished Dec 20 01:06:08 PM PST 23
Peak memory 202344 kb
Host smart-8cbce79c-ada7-4577-bd6d-5a4be23496bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742533723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2742533723
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.1397119191
Short name T324
Test name
Test status
Simulation time 7428068613 ps
CPU time 483.27 seconds
Started Dec 20 01:05:46 PM PST 23
Finished Dec 20 01:14:06 PM PST 23
Peak memory 375892 kb
Host smart-0953d23d-03c6-4f3b-97f4-db615b69a290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397119191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1397119191
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.1823510677
Short name T518
Test name
Test status
Simulation time 959987963 ps
CPU time 9.26 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:06:04 PM PST 23
Peak memory 202060 kb
Host smart-bab77b80-09cc-4f1e-9a83-68d44a4eb8cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823510677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1823510677
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.3238657206
Short name T279
Test name
Test status
Simulation time 306059115434 ps
CPU time 5291.07 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 02:34:18 PM PST 23
Peak memory 377108 kb
Host smart-0afe8579-31ed-41bf-8e66-9a50f1fdb680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238657206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.3238657206
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.933498490
Short name T891
Test name
Test status
Simulation time 684987915 ps
CPU time 2113.31 seconds
Started Dec 20 01:06:03 PM PST 23
Finished Dec 20 01:41:25 PM PST 23
Peak memory 652600 kb
Host smart-f4a56a08-86f9-4078-9e8f-bbe154fcf66e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=933498490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.933498490
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.578965633
Short name T284
Test name
Test status
Simulation time 21360518648 ps
CPU time 405.31 seconds
Started Dec 20 01:05:39 PM PST 23
Finished Dec 20 01:12:39 PM PST 23
Peak memory 202272 kb
Host smart-cbfb5937-0fcf-4a66-bbcd-6d86d0bfac37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578965633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.sram_ctrl_stress_pipeline.578965633
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1668764076
Short name T736
Test name
Test status
Simulation time 822476106 ps
CPU time 119.78 seconds
Started Dec 20 01:05:34 PM PST 23
Finished Dec 20 01:07:49 PM PST 23
Peak memory 346344 kb
Host smart-2cf4a304-6605-49bd-bcf5-fc13fbeb25cb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668764076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1668764076
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2477365368
Short name T866
Test name
Test status
Simulation time 37737166748 ps
CPU time 681.58 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:17:44 PM PST 23
Peak memory 379496 kb
Host smart-be5ea826-002a-44f0-a1ce-039f5af6f880
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477365368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.2477365368
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.25260082
Short name T734
Test name
Test status
Simulation time 19018876 ps
CPU time 0.64 seconds
Started Dec 20 01:05:55 PM PST 23
Finished Dec 20 01:06:10 PM PST 23
Peak memory 201832 kb
Host smart-6d24e3da-1478-4610-9362-17b9b8d50319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25260082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_alert_test.25260082
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.459700853
Short name T140
Test name
Test status
Simulation time 67263399924 ps
CPU time 1451.24 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:30:28 PM PST 23
Peak memory 202240 kb
Host smart-8de82faf-d3b1-46b9-bc70-c69c571a1656
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459700853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.
459700853
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.2114904098
Short name T912
Test name
Test status
Simulation time 13467288476 ps
CPU time 60.2 seconds
Started Dec 20 01:05:54 PM PST 23
Finished Dec 20 01:07:09 PM PST 23
Peak memory 210412 kb
Host smart-296f331b-6477-4f52-9712-c468608ab00d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114904098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.2114904098
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.3101873946
Short name T701
Test name
Test status
Simulation time 1543938583 ps
CPU time 110.25 seconds
Started Dec 20 01:05:44 PM PST 23
Finished Dec 20 01:07:49 PM PST 23
Peak memory 327876 kb
Host smart-5ec7524f-7be3-4269-b222-e184c7c52923
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101873946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.3101873946
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3363361233
Short name T604
Test name
Test status
Simulation time 4119441015 ps
CPU time 135.94 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:08:36 PM PST 23
Peak memory 211232 kb
Host smart-16ac63cc-b34f-48d6-915a-9da5615585f6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363361233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.3363361233
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.184155505
Short name T793
Test name
Test status
Simulation time 57465135371 ps
CPU time 146.53 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:08:32 PM PST 23
Peak memory 202276 kb
Host smart-a45521bd-c62f-4f37-acc7-e67a627bdec3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184155505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.184155505
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.1746106616
Short name T340
Test name
Test status
Simulation time 52723957063 ps
CPU time 140.3 seconds
Started Dec 20 01:05:48 PM PST 23
Finished Dec 20 01:08:24 PM PST 23
Peak memory 340456 kb
Host smart-be946404-33f0-46aa-b6f0-7892b88dec80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746106616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.1746106616
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3211970206
Short name T915
Test name
Test status
Simulation time 14956392923 ps
CPU time 33.17 seconds
Started Dec 20 01:05:55 PM PST 23
Finished Dec 20 01:06:42 PM PST 23
Peak memory 202240 kb
Host smart-61f6e748-9f9b-421e-a976-efa39b2fbc34
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211970206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3211970206
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.3661959709
Short name T987
Test name
Test status
Simulation time 1400484618 ps
CPU time 5.8 seconds
Started Dec 20 01:05:47 PM PST 23
Finished Dec 20 01:06:10 PM PST 23
Peak memory 202520 kb
Host smart-09fb521b-18ac-45a3-affc-e70ad6c607a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661959709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3661959709
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.1767578253
Short name T741
Test name
Test status
Simulation time 38797758404 ps
CPU time 1009.51 seconds
Started Dec 20 01:05:52 PM PST 23
Finished Dec 20 01:22:56 PM PST 23
Peak memory 381028 kb
Host smart-e8da1fb2-5d9f-42cf-a20d-b77bd593752b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767578253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1767578253
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.3814305091
Short name T668
Test name
Test status
Simulation time 967857704 ps
CPU time 131.78 seconds
Started Dec 20 01:05:45 PM PST 23
Finished Dec 20 01:08:12 PM PST 23
Peak memory 375024 kb
Host smart-e5d8fbef-2377-4a93-8163-75fb3cc393a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814305091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3814305091
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3244603614
Short name T808
Test name
Test status
Simulation time 399579710 ps
CPU time 1548.67 seconds
Started Dec 20 01:05:46 PM PST 23
Finished Dec 20 01:31:52 PM PST 23
Peak memory 386552 kb
Host smart-12c0db46-4199-4341-827b-f6ac263f8b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3244603614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3244603614
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2499348550
Short name T745
Test name
Test status
Simulation time 4382370686 ps
CPU time 322.49 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:11:29 PM PST 23
Peak memory 202160 kb
Host smart-19767d92-1963-40f9-90e8-8abc43050a33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499348550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.2499348550
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1425115541
Short name T148
Test name
Test status
Simulation time 1528616181 ps
CPU time 82 seconds
Started Dec 20 01:05:55 PM PST 23
Finished Dec 20 01:07:31 PM PST 23
Peak memory 300392 kb
Host smart-8aa84a1b-66b4-45fa-b55c-35b6742303cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425115541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1425115541
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.610020875
Short name T792
Test name
Test status
Simulation time 33431676211 ps
CPU time 1003.64 seconds
Started Dec 20 01:05:51 PM PST 23
Finished Dec 20 01:22:50 PM PST 23
Peak memory 379164 kb
Host smart-ec9d59e3-4559-409b-aa19-acac5e595f1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610020875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.sram_ctrl_access_during_key_req.610020875
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.1776470060
Short name T690
Test name
Test status
Simulation time 18980492 ps
CPU time 0.7 seconds
Started Dec 20 01:05:52 PM PST 23
Finished Dec 20 01:06:08 PM PST 23
Peak memory 201940 kb
Host smart-03256491-964a-43af-88ea-ad77f244677e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776470060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.1776470060
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.3605553074
Short name T390
Test name
Test status
Simulation time 88787464086 ps
CPU time 1509.28 seconds
Started Dec 20 01:05:52 PM PST 23
Finished Dec 20 01:31:16 PM PST 23
Peak memory 202192 kb
Host smart-4eeaf18c-2f18-4df1-8a97-79b0909f2cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605553074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.3605553074
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.1885222778
Short name T360
Test name
Test status
Simulation time 55067008349 ps
CPU time 858.09 seconds
Started Dec 20 01:05:42 PM PST 23
Finished Dec 20 01:20:15 PM PST 23
Peak memory 378120 kb
Host smart-cf539883-1a55-4b1e-90a0-fb3ee9f295ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885222778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.1885222778
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.761305511
Short name T907
Test name
Test status
Simulation time 39142938943 ps
CPU time 106.46 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:08:06 PM PST 23
Peak memory 210324 kb
Host smart-4f5b4518-4a14-402d-9662-4babae05048c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761305511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc
alation.761305511
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.65521810
Short name T408
Test name
Test status
Simulation time 791301567 ps
CPU time 138.32 seconds
Started Dec 20 01:05:58 PM PST 23
Finished Dec 20 01:08:29 PM PST 23
Peak memory 356544 kb
Host smart-bf9f02eb-f0c7-43be-8091-463800b3df9f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65521810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.sram_ctrl_max_throughput.65521810
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2737574503
Short name T693
Test name
Test status
Simulation time 1620326607 ps
CPU time 135.69 seconds
Started Dec 20 01:05:42 PM PST 23
Finished Dec 20 01:08:12 PM PST 23
Peak memory 211108 kb
Host smart-4f3fb6a6-25a7-4902-aa40-faf769f97d2c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737574503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2737574503
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.135903371
Short name T414
Test name
Test status
Simulation time 10440717602 ps
CPU time 156.43 seconds
Started Dec 20 01:05:42 PM PST 23
Finished Dec 20 01:08:33 PM PST 23
Peak memory 202272 kb
Host smart-5876dfe6-a84b-4b4c-9297-0008d3b7d04f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135903371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_mem_walk.135903371
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.61389574
Short name T945
Test name
Test status
Simulation time 70755003311 ps
CPU time 1050.56 seconds
Started Dec 20 01:05:44 PM PST 23
Finished Dec 20 01:23:29 PM PST 23
Peak memory 381152 kb
Host smart-608ec83c-ca65-438f-9508-4b0a9c95d68c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61389574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multipl
e_keys.61389574
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.782728527
Short name T346
Test name
Test status
Simulation time 5353335391 ps
CPU time 27.23 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:06:38 PM PST 23
Peak memory 202184 kb
Host smart-81f10ad4-7bcc-421c-97cc-4fd5023ee9a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782728527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s
ram_ctrl_partial_access.782728527
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3876590080
Short name T704
Test name
Test status
Simulation time 24380978906 ps
CPU time 295.53 seconds
Started Dec 20 01:05:51 PM PST 23
Finished Dec 20 01:11:02 PM PST 23
Peak memory 202292 kb
Host smart-7d89b747-de22-4506-a62a-cf1b8ac01a97
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876590080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3876590080
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.2809832436
Short name T461
Test name
Test status
Simulation time 2792868747 ps
CPU time 6.09 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:06:12 PM PST 23
Peak memory 202588 kb
Host smart-d662d1d4-1757-46c8-918f-3387321acbab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809832436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2809832436
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.2695141137
Short name T714
Test name
Test status
Simulation time 100737517330 ps
CPU time 921.67 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:21:36 PM PST 23
Peak memory 379252 kb
Host smart-035672df-67e6-4256-9ace-37c600e35a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695141137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2695141137
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.3583378687
Short name T289
Test name
Test status
Simulation time 5292946287 ps
CPU time 25.5 seconds
Started Dec 20 01:05:44 PM PST 23
Finished Dec 20 01:06:24 PM PST 23
Peak memory 202248 kb
Host smart-e077b344-570d-446a-b026-2755ec7e3007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583378687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3583378687
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3372625652
Short name T554
Test name
Test status
Simulation time 7882617055 ps
CPU time 2958.32 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:55:45 PM PST 23
Peak memory 405336 kb
Host smart-2c5334bb-973f-4c70-a8ca-e810874b7191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3372625652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3372625652
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2606138202
Short name T624
Test name
Test status
Simulation time 17655037382 ps
CPU time 359.63 seconds
Started Dec 20 01:05:48 PM PST 23
Finished Dec 20 01:12:05 PM PST 23
Peak memory 202248 kb
Host smart-dd0b6885-8aa2-45ba-9054-f3a78787fe56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606138202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.2606138202
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3300418849
Short name T944
Test name
Test status
Simulation time 2725110859 ps
CPU time 30.39 seconds
Started Dec 20 01:05:52 PM PST 23
Finished Dec 20 01:06:37 PM PST 23
Peak memory 223896 kb
Host smart-c044eb69-1e41-44d0-ae99-6548504fe411
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300418849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3300418849
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3509810672
Short name T985
Test name
Test status
Simulation time 34660127912 ps
CPU time 1091.24 seconds
Started Dec 20 01:05:47 PM PST 23
Finished Dec 20 01:24:15 PM PST 23
Peak memory 378164 kb
Host smart-460554c1-f0dc-46b6-815c-853a87fc0af5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509810672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.3509810672
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.1550776418
Short name T740
Test name
Test status
Simulation time 31045848 ps
CPU time 0.63 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:06:07 PM PST 23
Peak memory 201812 kb
Host smart-48cac35d-e882-4e38-bb42-3f3be8b2dd5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550776418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.1550776418
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.2267413023
Short name T136
Test name
Test status
Simulation time 77635571601 ps
CPU time 1242.3 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:26:56 PM PST 23
Peak memory 202112 kb
Host smart-f7af7234-db99-4283-8a1a-e181059c4478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267413023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.2267413023
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.3485762205
Short name T471
Test name
Test status
Simulation time 99423091251 ps
CPU time 930.57 seconds
Started Dec 20 01:05:52 PM PST 23
Finished Dec 20 01:21:38 PM PST 23
Peak memory 374732 kb
Host smart-12d12145-a42f-47b5-aed2-b37baa38ebaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485762205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.3485762205
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.962531968
Short name T616
Test name
Test status
Simulation time 18217006807 ps
CPU time 70.64 seconds
Started Dec 20 01:05:49 PM PST 23
Finished Dec 20 01:07:15 PM PST 23
Peak memory 210416 kb
Host smart-1042a2f4-ad00-484b-bf0a-6f8898c73aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962531968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc
alation.962531968
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.1748881826
Short name T275
Test name
Test status
Simulation time 1359479347 ps
CPU time 31.16 seconds
Started Dec 20 01:05:48 PM PST 23
Finished Dec 20 01:06:35 PM PST 23
Peak memory 220008 kb
Host smart-a12b7085-c14b-454f-af7f-51b72fa63879
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748881826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.1748881826
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1220202064
Short name T934
Test name
Test status
Simulation time 10475633705 ps
CPU time 159.86 seconds
Started Dec 20 01:05:51 PM PST 23
Finished Dec 20 01:08:46 PM PST 23
Peak memory 210668 kb
Host smart-eb453504-6aac-4ef5-a8ee-9b5a78ecda62
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220202064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1220202064
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.1212781732
Short name T922
Test name
Test status
Simulation time 8227958731 ps
CPU time 132.63 seconds
Started Dec 20 01:05:51 PM PST 23
Finished Dec 20 01:08:19 PM PST 23
Peak memory 202200 kb
Host smart-7aeab65b-6b29-4681-a5f0-b0397b672d08
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212781732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.1212781732
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.1184615565
Short name T756
Test name
Test status
Simulation time 39033005925 ps
CPU time 972.87 seconds
Started Dec 20 01:05:45 PM PST 23
Finished Dec 20 01:22:13 PM PST 23
Peak memory 378228 kb
Host smart-01451ba1-fbaf-4b58-8a68-824386fe4305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184615565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.1184615565
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.346971071
Short name T575
Test name
Test status
Simulation time 2018025731 ps
CPU time 17.46 seconds
Started Dec 20 01:05:45 PM PST 23
Finished Dec 20 01:06:18 PM PST 23
Peak memory 202168 kb
Host smart-72e0b3b8-9f14-49fc-a39a-fc9104dd6981
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346971071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s
ram_ctrl_partial_access.346971071
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.646413018
Short name T562
Test name
Test status
Simulation time 98616772009 ps
CPU time 566.72 seconds
Started Dec 20 01:05:58 PM PST 23
Finished Dec 20 01:15:37 PM PST 23
Peak memory 202244 kb
Host smart-0478a175-cc90-4c16-b11f-4a39a3e94464
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646413018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.sram_ctrl_partial_access_b2b.646413018
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.3278169180
Short name T436
Test name
Test status
Simulation time 2786499928 ps
CPU time 7.01 seconds
Started Dec 20 01:05:55 PM PST 23
Finished Dec 20 01:06:16 PM PST 23
Peak memory 202508 kb
Host smart-57e6b7e3-dba2-4a6f-ae79-98b765e662ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278169180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3278169180
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.2275700570
Short name T255
Test name
Test status
Simulation time 15890645037 ps
CPU time 1060.47 seconds
Started Dec 20 01:05:47 PM PST 23
Finished Dec 20 01:23:44 PM PST 23
Peak memory 374968 kb
Host smart-911741c1-3538-413a-94c5-4f6a8f847adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275700570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2275700570
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.4130205271
Short name T98
Test name
Test status
Simulation time 2414787908 ps
CPU time 84.15 seconds
Started Dec 20 01:05:58 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 334180 kb
Host smart-72fdfa25-4192-4dca-8e93-c506bde4a745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130205271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.4130205271
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.1552734766
Short name T735
Test name
Test status
Simulation time 429405365531 ps
CPU time 4461.42 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 02:20:33 PM PST 23
Peak memory 380200 kb
Host smart-3fd5695d-f4ac-41d4-aef2-53d34482a9ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552734766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.1552734766
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.473631837
Short name T650
Test name
Test status
Simulation time 229474390 ps
CPU time 3054.01 seconds
Started Dec 20 01:05:43 PM PST 23
Finished Dec 20 01:56:52 PM PST 23
Peak memory 735552 kb
Host smart-5029ad2a-0f21-4b0d-8994-9acf409514f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=473631837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.473631837
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.405762226
Short name T754
Test name
Test status
Simulation time 5474081367 ps
CPU time 415.59 seconds
Started Dec 20 01:05:57 PM PST 23
Finished Dec 20 01:13:05 PM PST 23
Peak memory 202292 kb
Host smart-7eeabe1f-0627-43dc-8f7e-d22accb83178
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405762226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_stress_pipeline.405762226
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4008940419
Short name T468
Test name
Test status
Simulation time 3297754874 ps
CPU time 34.61 seconds
Started Dec 20 01:05:55 PM PST 23
Finished Dec 20 01:06:43 PM PST 23
Peak memory 238740 kb
Host smart-0a8036b0-6996-40be-acb3-d911d0036378
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008940419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.4008940419
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.174663931
Short name T767
Test name
Test status
Simulation time 18295024975 ps
CPU time 1346.98 seconds
Started Dec 20 01:05:49 PM PST 23
Finished Dec 20 01:28:32 PM PST 23
Peak memory 375076 kb
Host smart-fec388f1-eb67-4941-861d-0111c9c5512a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174663931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.sram_ctrl_access_during_key_req.174663931
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.710493047
Short name T869
Test name
Test status
Simulation time 24805043 ps
CPU time 0.66 seconds
Started Dec 20 01:05:48 PM PST 23
Finished Dec 20 01:06:04 PM PST 23
Peak memory 201396 kb
Host smart-5fe45bed-a0b9-469a-b5f0-7f12277b013a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710493047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.710493047
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.315413125
Short name T2
Test name
Test status
Simulation time 170771397781 ps
CPU time 2418.14 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:46:32 PM PST 23
Peak memory 202176 kb
Host smart-dec75b8b-a60a-4157-99ff-0e819f9d76e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315413125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.
315413125
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.405148663
Short name T126
Test name
Test status
Simulation time 265041489694 ps
CPU time 1446.2 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:30:20 PM PST 23
Peak memory 380144 kb
Host smart-3f5c2c8a-b693-4f3a-b2c4-010cc8894ac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405148663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl
e.405148663
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.1642713651
Short name T652
Test name
Test status
Simulation time 19454161887 ps
CPU time 195.04 seconds
Started Dec 20 01:06:01 PM PST 23
Finished Dec 20 01:09:26 PM PST 23
Peak memory 210468 kb
Host smart-e07ac649-c306-4f5f-993b-b5c0668a9687
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642713651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.1642713651
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.4170094236
Short name T956
Test name
Test status
Simulation time 1742856720 ps
CPU time 29.95 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:06:36 PM PST 23
Peak memory 224384 kb
Host smart-e24f20db-90df-4e53-9c58-95704a103ecf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170094236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.4170094236
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2169983513
Short name T902
Test name
Test status
Simulation time 6794098317 ps
CPU time 129.16 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:08:27 PM PST 23
Peak memory 214504 kb
Host smart-75446765-68ef-4ee5-a3fc-5cf9efa15648
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169983513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.2169983513
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1059651453
Short name T311
Test name
Test status
Simulation time 4110401160 ps
CPU time 251.2 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:10:26 PM PST 23
Peak memory 202156 kb
Host smart-d3c00894-0109-46d3-b13d-8f0e26828fbb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059651453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1059651453
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.4173769302
Short name T829
Test name
Test status
Simulation time 7196869805 ps
CPU time 1029.67 seconds
Started Dec 20 01:05:56 PM PST 23
Finished Dec 20 01:23:19 PM PST 23
Peak memory 379200 kb
Host smart-cf80c724-9b28-4c94-b1d9-66e58647b798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173769302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.4173769302
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1003035389
Short name T332
Test name
Test status
Simulation time 713857067 ps
CPU time 29.33 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:06:43 PM PST 23
Peak memory 202176 kb
Host smart-f99c6bc0-4df3-4855-97e9-ae20508733a3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003035389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1003035389
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3119152723
Short name T448
Test name
Test status
Simulation time 15775178267 ps
CPU time 341.34 seconds
Started Dec 20 01:05:54 PM PST 23
Finished Dec 20 01:11:50 PM PST 23
Peak memory 210464 kb
Host smart-9a32f48b-a25a-4c69-9cf5-904b6a785a9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119152723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.3119152723
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.3832902886
Short name T946
Test name
Test status
Simulation time 360434733 ps
CPU time 13.84 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:06:31 PM PST 23
Peak memory 202440 kb
Host smart-939e2b43-502d-451a-825a-a03704a987a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832902886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3832902886
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.30883078
Short name T380
Test name
Test status
Simulation time 27487467201 ps
CPU time 1523.86 seconds
Started Dec 20 01:05:54 PM PST 23
Finished Dec 20 01:31:32 PM PST 23
Peak memory 381100 kb
Host smart-81c53ec2-e301-4d66-9a01-f7816d3f6cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30883078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.30883078
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.3336815755
Short name T492
Test name
Test status
Simulation time 731555099 ps
CPU time 49.03 seconds
Started Dec 20 01:05:52 PM PST 23
Finished Dec 20 01:06:56 PM PST 23
Peak memory 303360 kb
Host smart-d7c9b1d6-e059-4ca4-bdc9-986055cc0eaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336815755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3336815755
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.2531698610
Short name T928
Test name
Test status
Simulation time 33824373282 ps
CPU time 2051.56 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:40:23 PM PST 23
Peak memory 379152 kb
Host smart-d5f0a8a2-5db6-45a1-808c-2821b0effe9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531698610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.2531698610
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2050566829
Short name T452
Test name
Test status
Simulation time 460203463 ps
CPU time 1821.79 seconds
Started Dec 20 01:05:55 PM PST 23
Finished Dec 20 01:36:31 PM PST 23
Peak memory 625324 kb
Host smart-f135e62b-4108-486e-8ac5-0e57394a4529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2050566829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2050566829
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1169922725
Short name T760
Test name
Test status
Simulation time 4645102737 ps
CPU time 352.13 seconds
Started Dec 20 01:06:01 PM PST 23
Finished Dec 20 01:12:04 PM PST 23
Peak memory 202208 kb
Host smart-829eabea-2f74-41cc-ac2b-81533cfe69ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169922725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.1169922725
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.820548703
Short name T483
Test name
Test status
Simulation time 761217824 ps
CPU time 90.43 seconds
Started Dec 20 01:05:49 PM PST 23
Finished Dec 20 01:07:36 PM PST 23
Peak memory 329944 kb
Host smart-1be0136b-6d2e-45b4-b72e-877b2a995e45
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820548703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_throughput_w_partial_write.820548703
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3153039453
Short name T441
Test name
Test status
Simulation time 14797954565 ps
CPU time 863.45 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:20:41 PM PST 23
Peak memory 369960 kb
Host smart-217c974f-be4e-480c-88b8-da0285f49add
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153039453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.3153039453
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.2523355726
Short name T815
Test name
Test status
Simulation time 13666991 ps
CPU time 0.66 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:06:24 PM PST 23
Peak memory 201520 kb
Host smart-d46de933-b597-45c6-85c8-061fb2487029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523355726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.2523355726
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.1351634478
Short name T250
Test name
Test status
Simulation time 50568730688 ps
CPU time 859.66 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:20:35 PM PST 23
Peak memory 202176 kb
Host smart-ad84271e-358a-4b91-b729-a87c743f0144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351634478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.1351634478
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.2280094137
Short name T587
Test name
Test status
Simulation time 2066085561 ps
CPU time 190.07 seconds
Started Dec 20 01:05:50 PM PST 23
Finished Dec 20 01:09:16 PM PST 23
Peak memory 368828 kb
Host smart-0a10b61e-6166-4e1d-9bd1-703aba4f7909
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280094137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.2280094137
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.767853114
Short name T487
Test name
Test status
Simulation time 2446822546 ps
CPU time 74.67 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:07:32 PM PST 23
Peak memory 211364 kb
Host smart-0fba1a0c-8143-4526-b47f-393bad585039
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767853114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.767853114
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.1699599027
Short name T824
Test name
Test status
Simulation time 7105655151 ps
CPU time 138.51 seconds
Started Dec 20 01:05:58 PM PST 23
Finished Dec 20 01:08:29 PM PST 23
Peak memory 202284 kb
Host smart-9e208cab-578f-47e6-9c4a-9537444a5ed1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699599027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.1699599027
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.3797437213
Short name T871
Test name
Test status
Simulation time 44703570550 ps
CPU time 1181.65 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:25:54 PM PST 23
Peak memory 379164 kb
Host smart-6914a3cb-883c-4771-aaec-d4e5fd2d9016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797437213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.3797437213
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.1396839908
Short name T392
Test name
Test status
Simulation time 1702219610 ps
CPU time 19.24 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:06:41 PM PST 23
Peak memory 202008 kb
Host smart-3456d6a3-49a9-4a77-afc3-7644403dcf73
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396839908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.1396839908
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1092451436
Short name T318
Test name
Test status
Simulation time 19710657046 ps
CPU time 464.42 seconds
Started Dec 20 01:05:51 PM PST 23
Finished Dec 20 01:13:51 PM PST 23
Peak memory 202188 kb
Host smart-b5531bbd-3134-428e-8d44-afd87a26620c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092451436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1092451436
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.423924480
Short name T786
Test name
Test status
Simulation time 345875527 ps
CPU time 5.71 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:06:17 PM PST 23
Peak memory 202436 kb
Host smart-40c1bf89-e59b-439b-aac4-796005e36f64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423924480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.423924480
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3292435767
Short name T319
Test name
Test status
Simulation time 29754346226 ps
CPU time 602.28 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:16:26 PM PST 23
Peak memory 373080 kb
Host smart-ccd97065-8690-46ea-ad14-a3d5ebd0184e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292435767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3292435767
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.3965890155
Short name T378
Test name
Test status
Simulation time 858192100 ps
CPU time 14.5 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:06:32 PM PST 23
Peak memory 220356 kb
Host smart-b963ff6e-5c94-48a9-ad99-4587ca3244a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965890155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3965890155
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.440282643
Short name T6
Test name
Test status
Simulation time 48784205640 ps
CPU time 3448.19 seconds
Started Dec 20 01:06:00 PM PST 23
Finished Dec 20 02:03:40 PM PST 23
Peak memory 381164 kb
Host smart-01f2a8eb-9399-4f8d-b2ae-1fb3e5008a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440282643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_stress_all.440282643
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2581265720
Short name T416
Test name
Test status
Simulation time 966951124 ps
CPU time 1460.9 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:30:37 PM PST 23
Peak memory 522676 kb
Host smart-5f783c0c-0966-4f26-9011-58ad3d9fac79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2581265720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2581265720
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2814515338
Short name T707
Test name
Test status
Simulation time 20187186843 ps
CPU time 395.87 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:12:55 PM PST 23
Peak memory 202072 kb
Host smart-bf11d27f-a7cd-4f6d-92ea-3e75cd314769
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814515338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.2814515338
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2189577608
Short name T838
Test name
Test status
Simulation time 760614189 ps
CPU time 72.34 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:07:26 PM PST 23
Peak memory 301388 kb
Host smart-b0eca315-c836-446d-b8f9-14b4d1b28ff2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189577608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2189577608
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.985568730
Short name T865
Test name
Test status
Simulation time 15601932517 ps
CPU time 1283.86 seconds
Started Dec 20 01:05:53 PM PST 23
Finished Dec 20 01:27:32 PM PST 23
Peak memory 377168 kb
Host smart-e0b249d7-e382-4deb-a468-39bb767090ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985568730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.sram_ctrl_access_during_key_req.985568730
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.2427390556
Short name T333
Test name
Test status
Simulation time 59972756 ps
CPU time 0.65 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:06:11 PM PST 23
Peak memory 201892 kb
Host smart-b780558c-73a6-46fb-97f5-22dcb724adb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427390556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.2427390556
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.228272851
Short name T259
Test name
Test status
Simulation time 368542107985 ps
CPU time 2104.23 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:41:26 PM PST 23
Peak memory 202252 kb
Host smart-12081981-00cb-4d7e-a7e7-a5df11a8c2c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228272851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.
228272851
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.3954814481
Short name T746
Test name
Test status
Simulation time 7639251601 ps
CPU time 65.35 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:07:20 PM PST 23
Peak memory 213916 kb
Host smart-c32a0816-a18f-4bb9-9ed5-980a191a359d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954814481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.3954814481
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.3902151276
Short name T810
Test name
Test status
Simulation time 3189921757 ps
CPU time 158.17 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:08:49 PM PST 23
Peak memory 375560 kb
Host smart-20a9e883-5161-4e3d-ac42-7a436f59765b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902151276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.3902151276
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3867257771
Short name T420
Test name
Test status
Simulation time 19891887544 ps
CPU time 151.89 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:08:56 PM PST 23
Peak memory 211120 kb
Host smart-84dd1cf6-8e98-4c08-b439-1b0195a9a450
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867257771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.3867257771
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.201052782
Short name T246
Test name
Test status
Simulation time 13150835234 ps
CPU time 124.85 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:08:25 PM PST 23
Peak memory 202516 kb
Host smart-a836be42-fe11-4d83-858f-ecec39c2aa9e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201052782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl
_mem_walk.201052782
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.1150498117
Short name T266
Test name
Test status
Simulation time 18354066163 ps
CPU time 953.22 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:22:11 PM PST 23
Peak memory 377152 kb
Host smart-a2e52875-92df-46a7-9ca1-9d6be1444798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150498117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.1150498117
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.3451995056
Short name T15
Test name
Test status
Simulation time 2777609169 ps
CPU time 158.1 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:08:52 PM PST 23
Peak memory 366812 kb
Host smart-36994157-081f-4e0b-b258-952f8a9a81d3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451995056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.3451995056
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2664358779
Short name T819
Test name
Test status
Simulation time 22911039798 ps
CPU time 342.79 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:11:59 PM PST 23
Peak memory 202128 kb
Host smart-63eedcd1-44e7-48a7-bd94-c026bc29efc3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664358779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.2664358779
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.775198214
Short name T899
Test name
Test status
Simulation time 2244854906 ps
CPU time 12.93 seconds
Started Dec 20 01:05:57 PM PST 23
Finished Dec 20 01:06:22 PM PST 23
Peak memory 202476 kb
Host smart-616e3339-d1ff-4e66-819d-8d95b555b3f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775198214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.775198214
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.150701059
Short name T976
Test name
Test status
Simulation time 655719807 ps
CPU time 27.18 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:06:44 PM PST 23
Peak memory 271604 kb
Host smart-bea9237e-8dd8-401d-af74-bfd134cdda63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150701059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.150701059
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1889085679
Short name T673
Test name
Test status
Simulation time 1584724184 ps
CPU time 1762.22 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:35:44 PM PST 23
Peak memory 633780 kb
Host smart-e42c7744-688a-46bc-bf14-6e666645e8d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1889085679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1889085679
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.196413026
Short name T323
Test name
Test status
Simulation time 4091804625 ps
CPU time 282.38 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:10:58 PM PST 23
Peak memory 202204 kb
Host smart-6bbb71a6-6a7e-4ddf-8f39-c8c02ccf6a1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196413026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_stress_pipeline.196413026
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.130426997
Short name T523
Test name
Test status
Simulation time 784497929 ps
CPU time 70.63 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:07:32 PM PST 23
Peak memory 300264 kb
Host smart-d2ae89a6-411e-4a0f-b170-f2aa1ff3e942
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130426997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.130426997
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.532151440
Short name T572
Test name
Test status
Simulation time 15488435256 ps
CPU time 1074.23 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:23:27 PM PST 23
Peak memory 374084 kb
Host smart-a0e51b8b-ff0a-47f2-8c81-4a6919a0b668
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532151440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.532151440
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.1949052461
Short name T548
Test name
Test status
Simulation time 14197403 ps
CPU time 0.63 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:05:37 PM PST 23
Peak memory 201448 kb
Host smart-5c6a5aaa-9bec-4917-9dd5-673d505f945f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949052461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.1949052461
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.3620634407
Short name T280
Test name
Test status
Simulation time 15223180563 ps
CPU time 1003.74 seconds
Started Dec 20 01:05:11 PM PST 23
Finished Dec 20 01:22:18 PM PST 23
Peak memory 202144 kb
Host smart-fd08f7eb-7722-42db-98d6-3a9387480293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620634407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
3620634407
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.926558594
Short name T859
Test name
Test status
Simulation time 16753105672 ps
CPU time 159.53 seconds
Started Dec 20 01:05:12 PM PST 23
Finished Dec 20 01:08:15 PM PST 23
Peak memory 210432 kb
Host smart-08d63985-4edf-4b55-8b4a-fcb5a65e4820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926558594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca
lation.926558594
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3478200987
Short name T696
Test name
Test status
Simulation time 806897572 ps
CPU time 116.69 seconds
Started Dec 20 01:04:51 PM PST 23
Finished Dec 20 01:07:08 PM PST 23
Peak memory 354384 kb
Host smart-288c6da3-9105-45fe-9d46-c0dc8e145f33
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478200987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3478200987
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3963725945
Short name T4
Test name
Test status
Simulation time 11305668375 ps
CPU time 159.07 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:08:04 PM PST 23
Peak memory 218580 kb
Host smart-8e8a61c4-e508-4c81-a886-607ad39c7a38
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963725945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.3963725945
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.3869905312
Short name T386
Test name
Test status
Simulation time 4295468049 ps
CPU time 124.88 seconds
Started Dec 20 01:05:01 PM PST 23
Finished Dec 20 01:07:36 PM PST 23
Peak memory 202268 kb
Host smart-de9aaa58-2cb4-4912-a7d9-732e0313e478
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869905312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.3869905312
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.4180153368
Short name T245
Test name
Test status
Simulation time 15290427499 ps
CPU time 1183.68 seconds
Started Dec 20 01:04:57 PM PST 23
Finished Dec 20 01:25:07 PM PST 23
Peak memory 379212 kb
Host smart-f059007d-a248-44b9-8f00-bf9bf2a5e840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180153368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.4180153368
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3913787631
Short name T552
Test name
Test status
Simulation time 1720232246 ps
CPU time 29.54 seconds
Started Dec 20 01:05:01 PM PST 23
Finished Dec 20 01:05:57 PM PST 23
Peak memory 202104 kb
Host smart-25adc961-bd17-49a9-b39e-27634a1f50b6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913787631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3913787631
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3268532801
Short name T108
Test name
Test status
Simulation time 34404722330 ps
CPU time 515.34 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:14:00 PM PST 23
Peak memory 202208 kb
Host smart-7e6fe80d-d6c8-40b2-b6ef-d588699803f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268532801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3268532801
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.1684516846
Short name T932
Test name
Test status
Simulation time 358091129 ps
CPU time 6.84 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:05:51 PM PST 23
Peak memory 202528 kb
Host smart-105312bb-94f5-46ad-9166-25f308212236
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684516846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1684516846
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1253248149
Short name T980
Test name
Test status
Simulation time 8829775077 ps
CPU time 731.65 seconds
Started Dec 20 01:05:01 PM PST 23
Finished Dec 20 01:17:39 PM PST 23
Peak memory 375020 kb
Host smart-a7984eb3-30ca-4ffd-874d-da037efb6c4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253248149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1253248149
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.2859515421
Short name T23
Test name
Test status
Simulation time 311023862 ps
CPU time 2.05 seconds
Started Dec 20 01:05:12 PM PST 23
Finished Dec 20 01:05:38 PM PST 23
Peak memory 221052 kb
Host smart-f2043d49-5416-45b0-944f-718104bbe7c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859515421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.2859515421
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2104975930
Short name T511
Test name
Test status
Simulation time 1948046510 ps
CPU time 76.46 seconds
Started Dec 20 01:05:03 PM PST 23
Finished Dec 20 01:06:45 PM PST 23
Peak memory 343068 kb
Host smart-779d0b08-8832-44da-88f4-f869001a8e4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104975930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2104975930
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3968409930
Short name T942
Test name
Test status
Simulation time 5088390057 ps
CPU time 2246.34 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:43:04 PM PST 23
Peak memory 586900 kb
Host smart-b6a93077-1e44-4e1e-bc5f-15be1915e101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3968409930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3968409930
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1219339114
Short name T434
Test name
Test status
Simulation time 3103550351 ps
CPU time 229.28 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:09:12 PM PST 23
Peak memory 202244 kb
Host smart-c830a812-ac80-4256-bd25-1b0b0edb6e67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219339114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.1219339114
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3769361350
Short name T253
Test name
Test status
Simulation time 748976919 ps
CPU time 75.44 seconds
Started Dec 20 01:05:05 PM PST 23
Finished Dec 20 01:06:45 PM PST 23
Peak memory 311144 kb
Host smart-b38ff8d7-d4ab-4648-993c-94567e48d7be
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769361350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3769361350
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2354768450
Short name T694
Test name
Test status
Simulation time 32413088530 ps
CPU time 759.4 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:18:53 PM PST 23
Peak memory 348484 kb
Host smart-ca55e84b-b63a-4acc-b0ca-320a3760db5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354768450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.2354768450
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.3711311545
Short name T21
Test name
Test status
Simulation time 16344730 ps
CPU time 0.71 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:06:16 PM PST 23
Peak memory 201440 kb
Host smart-91f6eb7e-eea8-4f63-9233-5b670dbee14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711311545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.3711311545
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.3267471939
Short name T911
Test name
Test status
Simulation time 92658103268 ps
CPU time 1468.4 seconds
Started Dec 20 01:06:20 PM PST 23
Finished Dec 20 01:30:57 PM PST 23
Peak memory 202244 kb
Host smart-1fd08315-d64b-43a5-8048-4de72576c4b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267471939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.3267471939
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.3723691161
Short name T711
Test name
Test status
Simulation time 12161254186 ps
CPU time 129.1 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:08:22 PM PST 23
Peak memory 210468 kb
Host smart-ebad0ae2-4bd1-4f6f-8e43-a764d2744e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723691161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.3723691161
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.3916166277
Short name T526
Test name
Test status
Simulation time 2803797518 ps
CPU time 29.01 seconds
Started Dec 20 01:06:01 PM PST 23
Finished Dec 20 01:06:40 PM PST 23
Peak memory 210424 kb
Host smart-b6aa47d9-3b3c-4a6d-b441-6ac2decdb171
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916166277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.3916166277
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.443733978
Short name T842
Test name
Test status
Simulation time 62213280485 ps
CPU time 159.25 seconds
Started Dec 20 01:06:21 PM PST 23
Finished Dec 20 01:09:09 PM PST 23
Peak memory 214576 kb
Host smart-27ca9538-32e6-4197-b4c3-bc3edeb6f7dd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443733978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.sram_ctrl_mem_partial_access.443733978
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.1613026055
Short name T462
Test name
Test status
Simulation time 10767504469 ps
CPU time 148.66 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:08:48 PM PST 23
Peak memory 202184 kb
Host smart-15d80dbb-3bb2-46b9-b806-c88405be4464
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613026055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.1613026055
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.1618779386
Short name T410
Test name
Test status
Simulation time 11025608770 ps
CPU time 1020.64 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:23:24 PM PST 23
Peak memory 376936 kb
Host smart-0b27c531-af78-46ae-8a96-48437863ce42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618779386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.1618779386
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.2383385255
Short name T613
Test name
Test status
Simulation time 1615063960 ps
CPU time 22.81 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:06:37 PM PST 23
Peak memory 236848 kb
Host smart-236fc363-d866-4fd6-a38a-7f6398ded903
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383385255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.2383385255
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.482381533
Short name T849
Test name
Test status
Simulation time 7908306041 ps
CPU time 351.43 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:12:16 PM PST 23
Peak memory 202320 kb
Host smart-2f26dcbf-1338-4776-84f1-b8b44bda2e2d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482381533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.sram_ctrl_partial_access_b2b.482381533
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.2860077477
Short name T656
Test name
Test status
Simulation time 357764826 ps
CPU time 6.59 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:06:21 PM PST 23
Peak memory 202476 kb
Host smart-2f32a3f9-7e88-4a03-b218-2aa8a51c8243
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860077477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2860077477
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.3035138778
Short name T278
Test name
Test status
Simulation time 14553826002 ps
CPU time 440.15 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:13:31 PM PST 23
Peak memory 376016 kb
Host smart-46df2856-35d2-415f-b106-d07ec9557a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035138778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3035138778
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2028034192
Short name T424
Test name
Test status
Simulation time 1885249673 ps
CPU time 6.4 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:06:20 PM PST 23
Peak memory 202080 kb
Host smart-5916bc3c-2101-4ef6-b041-df529077a698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028034192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2028034192
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.2368884330
Short name T27
Test name
Test status
Simulation time 19024336684 ps
CPU time 2105.37 seconds
Started Dec 20 01:06:02 PM PST 23
Finished Dec 20 01:41:17 PM PST 23
Peak memory 382276 kb
Host smart-58165a11-6037-4d55-9658-689605b071ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368884330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.2368884330
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2693367189
Short name T892
Test name
Test status
Simulation time 4125996941 ps
CPU time 1315.12 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:28:15 PM PST 23
Peak memory 568572 kb
Host smart-aa21fc76-10d1-4077-8ee9-98398fe7e2e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2693367189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2693367189
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1759132584
Short name T521
Test name
Test status
Simulation time 14766611199 ps
CPU time 248.38 seconds
Started Dec 20 01:06:00 PM PST 23
Finished Dec 20 01:10:20 PM PST 23
Peak memory 202252 kb
Host smart-dee27a2a-67c0-4572-b26a-d183d18f8f3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759132584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.1759132584
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2917857713
Short name T45
Test name
Test status
Simulation time 2956673618 ps
CPU time 42.63 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:06:56 PM PST 23
Peak memory 262912 kb
Host smart-3d8b80f0-b211-41cb-b677-bf460460a7e5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917857713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2917857713
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.650254470
Short name T338
Test name
Test status
Simulation time 138525408173 ps
CPU time 1055.78 seconds
Started Dec 20 01:05:57 PM PST 23
Finished Dec 20 01:23:46 PM PST 23
Peak memory 378164 kb
Host smart-1e769208-164f-4141-99d3-4994e0ac952f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650254470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.sram_ctrl_access_during_key_req.650254470
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.3429983594
Short name T9
Test name
Test status
Simulation time 18317227 ps
CPU time 0.66 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:06:27 PM PST 23
Peak memory 201824 kb
Host smart-4c8c0953-c0a8-49c0-a57a-046815bef935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429983594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.3429983594
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2202095513
Short name T335
Test name
Test status
Simulation time 265881337643 ps
CPU time 1733.19 seconds
Started Dec 20 01:06:02 PM PST 23
Finished Dec 20 01:35:05 PM PST 23
Peak memory 202044 kb
Host smart-3a209477-e4a9-4dab-8e79-541a22379d12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202095513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2202095513
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.1395029973
Short name T282
Test name
Test status
Simulation time 20321687440 ps
CPU time 904.53 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:21:22 PM PST 23
Peak memory 368024 kb
Host smart-0c97344e-f30f-4622-a97c-83518016a5b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395029973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.1395029973
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.4032888457
Short name T478
Test name
Test status
Simulation time 3132706068 ps
CPU time 132.16 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:08:25 PM PST 23
Peak memory 351748 kb
Host smart-bd0b7502-2cde-43d7-a782-3245d23c3972
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032888457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.4032888457
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1760585681
Short name T363
Test name
Test status
Simulation time 2408602450 ps
CPU time 82.47 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:07:45 PM PST 23
Peak memory 211080 kb
Host smart-b4a9e65e-f225-48ba-b584-be25ec841fe8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760585681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.1760585681
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.800463112
Short name T560
Test name
Test status
Simulation time 35898412633 ps
CPU time 143.57 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:08:34 PM PST 23
Peak memory 202208 kb
Host smart-b60ed770-ad74-40d5-9eb4-b61b0eb9e44c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800463112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl
_mem_walk.800463112
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.1374780529
Short name T646
Test name
Test status
Simulation time 4814629080 ps
CPU time 200.61 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:09:41 PM PST 23
Peak memory 365864 kb
Host smart-fafd69fd-5e58-451e-9986-da522498d117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374780529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.1374780529
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.2170012047
Short name T251
Test name
Test status
Simulation time 3284912470 ps
CPU time 59.07 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:07:22 PM PST 23
Peak memory 311652 kb
Host smart-41f2e6ea-1efd-4f9d-a04f-cfc9c912a5fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170012047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.2170012047
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1680596890
Short name T705
Test name
Test status
Simulation time 80524283991 ps
CPU time 475.79 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:14:19 PM PST 23
Peak memory 202248 kb
Host smart-d0817145-d97f-4728-a25c-604f5c77ba81
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680596890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.1680596890
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.3527810642
Short name T878
Test name
Test status
Simulation time 363376563 ps
CPU time 6.07 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:06:23 PM PST 23
Peak memory 202460 kb
Host smart-6b515832-81d0-4045-9c60-eacd9d87f617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527810642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3527810642
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.3933250625
Short name T348
Test name
Test status
Simulation time 35938731471 ps
CPU time 1060.79 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:23:59 PM PST 23
Peak memory 377136 kb
Host smart-488781bc-750b-4d36-b9e0-b742172ec478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933250625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3933250625
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.434865237
Short name T388
Test name
Test status
Simulation time 993425265 ps
CPU time 15.99 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:06:34 PM PST 23
Peak memory 242272 kb
Host smart-bd6f2d82-7dac-4018-952f-090212a05255
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434865237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.434865237
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.291418927
Short name T375
Test name
Test status
Simulation time 657905807086 ps
CPU time 3742.97 seconds
Started Dec 20 01:05:58 PM PST 23
Finished Dec 20 02:08:34 PM PST 23
Peak memory 346656 kb
Host smart-9c3af7a2-1f7d-49e6-97c2-d7599bc28e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291418927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_stress_all.291418927
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2186067536
Short name T826
Test name
Test status
Simulation time 3345953927 ps
CPU time 1370.09 seconds
Started Dec 20 01:06:00 PM PST 23
Finished Dec 20 01:29:02 PM PST 23
Peak memory 412856 kb
Host smart-507546ad-aaa4-411a-ab9d-d2078f22f342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2186067536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2186067536
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1069569102
Short name T384
Test name
Test status
Simulation time 68369767053 ps
CPU time 259.21 seconds
Started Dec 20 01:05:54 PM PST 23
Finished Dec 20 01:10:28 PM PST 23
Peak memory 202264 kb
Host smart-f996d641-19f8-4263-baff-548fde378ea7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069569102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.1069569102
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2901696663
Short name T814
Test name
Test status
Simulation time 3402291492 ps
CPU time 158.09 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:08:54 PM PST 23
Peak memory 365716 kb
Host smart-8e6aec7d-a949-4091-8283-0c4acef17601
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901696663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2901696663
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1643234205
Short name T780
Test name
Test status
Simulation time 20468660632 ps
CPU time 1572.74 seconds
Started Dec 20 01:06:02 PM PST 23
Finished Dec 20 01:32:25 PM PST 23
Peak memory 378124 kb
Host smart-e8b0817d-39bd-4f00-892b-01861cf4a394
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643234205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.1643234205
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.1791697583
Short name T371
Test name
Test status
Simulation time 22522032 ps
CPU time 0.63 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:06:18 PM PST 23
Peak memory 201504 kb
Host smart-f7d27398-3b40-42f3-acaa-7ccbfbec1d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791697583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.1791697583
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.845853362
Short name T762
Test name
Test status
Simulation time 181436689254 ps
CPU time 2795.35 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:52:53 PM PST 23
Peak memory 202232 kb
Host smart-f5404441-5dd3-45ff-aebe-5d96ad9b548c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845853362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.
845853362
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.4246366537
Short name T637
Test name
Test status
Simulation time 68250496851 ps
CPU time 1073.16 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:24:17 PM PST 23
Peak memory 379084 kb
Host smart-c87ad857-d1e6-4e8d-a36b-190e14771981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246366537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.4246366537
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.454085906
Short name T132
Test name
Test status
Simulation time 62144804269 ps
CPU time 242.71 seconds
Started Dec 20 01:06:01 PM PST 23
Finished Dec 20 01:10:14 PM PST 23
Peak memory 210464 kb
Host smart-72c59c82-2de9-4ffc-88fe-33b92be3ea9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454085906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc
alation.454085906
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1822710832
Short name T5
Test name
Test status
Simulation time 1510400554 ps
CPU time 87.55 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:07:49 PM PST 23
Peak memory 321716 kb
Host smart-84a5a7e3-c67e-4288-b1c0-653ff2ea6b6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822710832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1822710832
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3703445086
Short name T724
Test name
Test status
Simulation time 2621721833 ps
CPU time 75.63 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:07:29 PM PST 23
Peak memory 211184 kb
Host smart-f1d1f347-ea4b-4bd2-aa04-f0e3272374ca
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703445086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3703445086
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.2283439490
Short name T981
Test name
Test status
Simulation time 18658854237 ps
CPU time 310.9 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:11:34 PM PST 23
Peak memory 202188 kb
Host smart-a6af1093-17b4-44ae-bc49-439e4c3e1ca7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283439490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.2283439490
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.3527732483
Short name T257
Test name
Test status
Simulation time 7724253471 ps
CPU time 448.74 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:13:52 PM PST 23
Peak memory 375320 kb
Host smart-af2f0e15-15da-4263-93b6-6cdd8c571ca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527732483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.3527732483
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.2536341463
Short name T795
Test name
Test status
Simulation time 2866832110 ps
CPU time 37.26 seconds
Started Dec 20 01:05:59 PM PST 23
Finished Dec 20 01:06:48 PM PST 23
Peak memory 244580 kb
Host smart-95bc3b5d-d42a-491f-9c75-96a2533b9617
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536341463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.2536341463
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3114260630
Short name T467
Test name
Test status
Simulation time 23570563698 ps
CPU time 559.71 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:15:41 PM PST 23
Peak memory 202284 kb
Host smart-f364970f-8559-4534-bc59-8ddc9086f239
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114260630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.3114260630
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.3522918912
Short name T283
Test name
Test status
Simulation time 343996071 ps
CPU time 5.53 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:06:24 PM PST 23
Peak memory 202316 kb
Host smart-d59a9170-2638-49fb-88cf-402a7b084284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522918912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3522918912
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.2575109688
Short name T768
Test name
Test status
Simulation time 1226205021 ps
CPU time 142.6 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:08:39 PM PST 23
Peak memory 323780 kb
Host smart-67f9017f-2fce-42a6-9420-ad24c3205a52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575109688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2575109688
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.2465785250
Short name T721
Test name
Test status
Simulation time 1828553015 ps
CPU time 35.86 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:06:50 PM PST 23
Peak memory 202100 kb
Host smart-1b0e37cc-088d-47e0-bf56-aa75ea77952e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465785250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2465785250
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.1813267363
Short name T500
Test name
Test status
Simulation time 347835231570 ps
CPU time 2996.34 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:56:12 PM PST 23
Peak memory 388456 kb
Host smart-4fb01551-ca14-4fa7-a0a9-44827612a45f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813267363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.1813267363
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3720190396
Short name T32
Test name
Test status
Simulation time 757521513 ps
CPU time 3896.03 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 02:11:11 PM PST 23
Peak memory 612684 kb
Host smart-955378ca-89ea-4b10-80ab-d7d77bd6b8e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3720190396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3720190396
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2421970396
Short name T106
Test name
Test status
Simulation time 2617881865 ps
CPU time 170.33 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:09:17 PM PST 23
Peak memory 202184 kb
Host smart-a05384a3-5f80-401e-8ce7-871478757f40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421970396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.2421970396
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3254105164
Short name T281
Test name
Test status
Simulation time 822700362 ps
CPU time 152.84 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:08:46 PM PST 23
Peak memory 371968 kb
Host smart-78a96230-7e8c-41f8-a992-677fc2faf4f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254105164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3254105164
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2790112078
Short name T295
Test name
Test status
Simulation time 7041170460 ps
CPU time 376.69 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:12:34 PM PST 23
Peak memory 333036 kb
Host smart-4c37ef43-66d7-460c-af8d-0a7b6898fe76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790112078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.2790112078
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.604444271
Short name T855
Test name
Test status
Simulation time 164808188 ps
CPU time 0.66 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:06:23 PM PST 23
Peak memory 201888 kb
Host smart-f9e1a6dc-b2ac-4e6a-a666-113988151a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604444271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.604444271
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.1328414757
Short name T516
Test name
Test status
Simulation time 259407644951 ps
CPU time 1065.8 seconds
Started Dec 20 01:06:14 PM PST 23
Finished Dec 20 01:24:11 PM PST 23
Peak memory 210440 kb
Host smart-50d6baa5-d566-459a-bea4-2ba07f4365f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328414757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.1328414757
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.2937185423
Short name T470
Test name
Test status
Simulation time 13744517028 ps
CPU time 219.36 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:09:56 PM PST 23
Peak memory 210492 kb
Host smart-db53f460-bcf7-4443-b489-ffc83c9ffb90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937185423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.2937185423
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2424630770
Short name T474
Test name
Test status
Simulation time 801499852 ps
CPU time 154.08 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:08:48 PM PST 23
Peak memory 369824 kb
Host smart-eba4de79-4f55-4736-97a8-32a7903c123b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424630770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2424630770
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2113050538
Short name T86
Test name
Test status
Simulation time 2431741056 ps
CPU time 75.29 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:07:42 PM PST 23
Peak memory 211476 kb
Host smart-9d12e354-c282-427f-a6dc-fd025fc58541
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113050538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.2113050538
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.1732917141
Short name T847
Test name
Test status
Simulation time 3943497653 ps
CPU time 246.54 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:10:21 PM PST 23
Peak memory 202112 kb
Host smart-57ce8d0a-a96f-4d65-aeb4-db1b623e5e8f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732917141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.1732917141
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1925785546
Short name T381
Test name
Test status
Simulation time 11085260132 ps
CPU time 839.57 seconds
Started Dec 20 01:06:07 PM PST 23
Finished Dec 20 01:20:16 PM PST 23
Peak memory 377956 kb
Host smart-878580ff-f73d-4ea4-bf0f-606f713f7406
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925785546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1925785546
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.4239513859
Short name T297
Test name
Test status
Simulation time 552417416 ps
CPU time 9.86 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:06:27 PM PST 23
Peak memory 201980 kb
Host smart-23dcd66c-9e27-4ec1-b4d9-cd4ef0298ce9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239513859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.4239513859
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3985356664
Short name T129
Test name
Test status
Simulation time 69328119882 ps
CPU time 350.27 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:12:04 PM PST 23
Peak memory 202240 kb
Host smart-36ae8272-2cdb-43ab-906c-73d55c200f38
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985356664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.3985356664
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.826993762
Short name T908
Test name
Test status
Simulation time 347769443 ps
CPU time 5.7 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:06:30 PM PST 23
Peak memory 202516 kb
Host smart-da9ec23c-d120-49c3-8221-a90dffd6af8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826993762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.826993762
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.2953526429
Short name T872
Test name
Test status
Simulation time 7807188399 ps
CPU time 188.28 seconds
Started Dec 20 01:06:04 PM PST 23
Finished Dec 20 01:09:21 PM PST 23
Peak memory 302396 kb
Host smart-696a6f87-f1dc-4e32-85a6-455306cf565b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953526429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2953526429
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.1779535685
Short name T617
Test name
Test status
Simulation time 1093838238 ps
CPU time 16.71 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:06:43 PM PST 23
Peak memory 202080 kb
Host smart-708ce2d0-a435-4fbb-89d2-f3f5c571dd69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779535685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1779535685
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.798331926
Short name T790
Test name
Test status
Simulation time 18850094673 ps
CPU time 3031.86 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:56:57 PM PST 23
Peak memory 633556 kb
Host smart-ef290f1b-0dbf-4bee-a94d-e224da3e3355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=798331926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.798331926
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1085841027
Short name T970
Test name
Test status
Simulation time 4231990411 ps
CPU time 309.83 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:11:27 PM PST 23
Peak memory 202212 kb
Host smart-6b7ec004-a143-40e9-9a4c-edc1c9d4f3e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085841027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.1085841027
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2457434178
Short name T290
Test name
Test status
Simulation time 2805415143 ps
CPU time 30.24 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:06:50 PM PST 23
Peak memory 215056 kb
Host smart-a04ce691-6915-4c5c-bb49-a9fb1af2cffc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457434178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2457434178
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.4173375548
Short name T367
Test name
Test status
Simulation time 4899078023 ps
CPU time 907.43 seconds
Started Dec 20 01:06:14 PM PST 23
Finished Dec 20 01:21:34 PM PST 23
Peak memory 378092 kb
Host smart-cc39ae0a-3ab5-492c-8fee-d0fdf39b71e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173375548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.4173375548
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.2085221685
Short name T47
Test name
Test status
Simulation time 16996824 ps
CPU time 0.64 seconds
Started Dec 20 01:06:20 PM PST 23
Finished Dec 20 01:06:30 PM PST 23
Peak memory 201944 kb
Host smart-8b72619e-bb08-473d-9765-bd5666112b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085221685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.2085221685
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.475601340
Short name T686
Test name
Test status
Simulation time 62482517381 ps
CPU time 1066.44 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:24:14 PM PST 23
Peak memory 202244 kb
Host smart-cd64c6fa-44dd-48ce-8c2b-2b5f6d61a618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475601340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.
475601340
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.913877263
Short name T522
Test name
Test status
Simulation time 45588343621 ps
CPU time 251.14 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:10:38 PM PST 23
Peak memory 210368 kb
Host smart-2b0e1a4c-67d9-43b3-a8c8-4d877e878311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913877263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc
alation.913877263
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.4032128218
Short name T139
Test name
Test status
Simulation time 1481835902 ps
CPU time 61.14 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:07:26 PM PST 23
Peak memory 300112 kb
Host smart-c18e84d0-9335-49ff-95d6-b6ce92d5cebe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032128218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.4032128218
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.787081629
Short name T431
Test name
Test status
Simulation time 2940778498 ps
CPU time 75.45 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:07:30 PM PST 23
Peak memory 218512 kb
Host smart-25bfa93d-76f7-451c-aad1-61edb5397947
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787081629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_mem_partial_access.787081629
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.1833295534
Short name T11
Test name
Test status
Simulation time 3948232021 ps
CPU time 242.04 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:10:28 PM PST 23
Peak memory 202196 kb
Host smart-8c5a43fe-acab-4f41-be8e-3a1ac94c1969
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833295534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.1833295534
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.2486561164
Short name T422
Test name
Test status
Simulation time 11280200828 ps
CPU time 1309.37 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:28:13 PM PST 23
Peak memory 380120 kb
Host smart-65e1215e-701b-44ad-ae37-8677fd585d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486561164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.2486561164
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.4205009600
Short name T339
Test name
Test status
Simulation time 1608076194 ps
CPU time 33.04 seconds
Started Dec 20 01:06:18 PM PST 23
Finished Dec 20 01:07:01 PM PST 23
Peak memory 210360 kb
Host smart-cc43cdf9-2242-453e-8f27-fe9511dadfe3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205009600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.4205009600
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2094994615
Short name T286
Test name
Test status
Simulation time 55725567841 ps
CPU time 492.83 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:14:30 PM PST 23
Peak memory 202284 kb
Host smart-7a6bd424-a0ac-4dde-942a-efc3a3c91fd0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094994615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.2094994615
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3506924782
Short name T773
Test name
Test status
Simulation time 1400685922 ps
CPU time 7 seconds
Started Dec 20 01:06:21 PM PST 23
Finished Dec 20 01:06:36 PM PST 23
Peak memory 202520 kb
Host smart-3897c217-1e06-4476-b806-d9c89dddc37e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506924782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3506924782
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.2262347947
Short name T725
Test name
Test status
Simulation time 11295887465 ps
CPU time 769.32 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:19:11 PM PST 23
Peak memory 353568 kb
Host smart-31a7ee21-c1c9-4fc1-950f-ff219c67190a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262347947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2262347947
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.3486277475
Short name T533
Test name
Test status
Simulation time 383832828 ps
CPU time 6.68 seconds
Started Dec 20 01:06:23 PM PST 23
Finished Dec 20 01:06:38 PM PST 23
Peak memory 202140 kb
Host smart-960dd8f1-33ff-471d-83d3-8c62915f35bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486277475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3486277475
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.452737168
Short name T833
Test name
Test status
Simulation time 4519691815 ps
CPU time 2819.68 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:53:21 PM PST 23
Peak memory 690940 kb
Host smart-1b94647a-23df-4539-a2f7-d3b132a2a472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=452737168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.452737168
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.322714021
Short name T827
Test name
Test status
Simulation time 19628152013 ps
CPU time 365.42 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:12:27 PM PST 23
Peak memory 202192 kb
Host smart-9c2cc1e9-8178-45c2-91e7-3e86875a3064
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322714021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_stress_pipeline.322714021
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1373654755
Short name T709
Test name
Test status
Simulation time 758574678 ps
CPU time 70.23 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:07:34 PM PST 23
Peak memory 303316 kb
Host smart-cdb80aed-6a0e-4d8d-9b7f-90937de59408
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373654755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1373654755
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.804231436
Short name T949
Test name
Test status
Simulation time 10812265081 ps
CPU time 1106.72 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:24:50 PM PST 23
Peak memory 369904 kb
Host smart-1619e9c3-7b55-4d0c-944f-a8e475e50e12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804231436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.sram_ctrl_access_during_key_req.804231436
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2546265743
Short name T491
Test name
Test status
Simulation time 20904128 ps
CPU time 0.66 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:06:15 PM PST 23
Peak memory 201892 kb
Host smart-5fe3d519-2d35-49fb-afac-2cf0d9ce42f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546265743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2546265743
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.2128196465
Short name T665
Test name
Test status
Simulation time 17738017839 ps
CPU time 1172.27 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:25:57 PM PST 23
Peak memory 202080 kb
Host smart-961b2c7d-6412-4611-8e38-a8e3722cf455
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128196465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.2128196465
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.1994240242
Short name T447
Test name
Test status
Simulation time 8601203580 ps
CPU time 419.81 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:13:26 PM PST 23
Peak memory 376244 kb
Host smart-08eb9357-9129-4987-afd9-77fd7197a1f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994240242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.1994240242
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.1687475761
Short name T451
Test name
Test status
Simulation time 8077397407 ps
CPU time 73.94 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:07:36 PM PST 23
Peak memory 210572 kb
Host smart-4b09a713-adc8-48bb-ae8d-af9b50cb42ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687475761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.1687475761
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.672199121
Short name T415
Test name
Test status
Simulation time 4246204325 ps
CPU time 33.46 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:06:54 PM PST 23
Peak memory 231248 kb
Host smart-10e3dc50-e213-4419-958c-1f618f345dc2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672199121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.sram_ctrl_max_throughput.672199121
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.798195960
Short name T882
Test name
Test status
Simulation time 2494828964 ps
CPU time 77.9 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 211340 kb
Host smart-61a44143-1ecb-4262-9105-9d0d7bd62fd9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798195960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.798195960
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.2328681187
Short name T720
Test name
Test status
Simulation time 4106530434 ps
CPU time 253.14 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:10:27 PM PST 23
Peak memory 202132 kb
Host smart-21af7f13-0eb9-4387-8751-ec20b97c1089
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328681187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.2328681187
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.2656280804
Short name T963
Test name
Test status
Simulation time 19028366314 ps
CPU time 864.09 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:20:38 PM PST 23
Peak memory 380348 kb
Host smart-fcc9fc3b-2ca8-4411-86a2-179ffb74343c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656280804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.2656280804
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.1759979784
Short name T779
Test name
Test status
Simulation time 1964442088 ps
CPU time 25.04 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:06:46 PM PST 23
Peak memory 202120 kb
Host smart-33d7c27c-18a6-4ce5-8d11-5e25e62aac4a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759979784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.1759979784
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2905805779
Short name T398
Test name
Test status
Simulation time 16225338685 ps
CPU time 394.15 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:12:59 PM PST 23
Peak memory 202224 kb
Host smart-5332b605-01d0-4c43-b09a-7f7d92048e82
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905805779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.2905805779
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2942469612
Short name T671
Test name
Test status
Simulation time 2596003316 ps
CPU time 5.76 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:06:27 PM PST 23
Peak memory 202504 kb
Host smart-7fab46b5-2e39-4fba-b6c2-71f6d32496f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942469612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2942469612
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.2799651802
Short name T600
Test name
Test status
Simulation time 10963922619 ps
CPU time 818.5 seconds
Started Dec 20 01:06:08 PM PST 23
Finished Dec 20 01:19:56 PM PST 23
Peak memory 379068 kb
Host smart-b7b604d1-c714-4e9a-af58-a5fd00d6d7b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799651802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2799651802
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.2134341942
Short name T666
Test name
Test status
Simulation time 1841983731 ps
CPU time 31.15 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:06:53 PM PST 23
Peak memory 202208 kb
Host smart-6db39bde-1756-4f42-b1bc-28f11b72f27d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134341942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2134341942
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.1836490697
Short name T501
Test name
Test status
Simulation time 264343517802 ps
CPU time 6180.11 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 02:49:25 PM PST 23
Peak memory 380232 kb
Host smart-745286a8-cf7f-47f3-bbf6-92cf38ba6a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836490697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.1836490697
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1116045374
Short name T649
Test name
Test status
Simulation time 372881664 ps
CPU time 1774.42 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:35:58 PM PST 23
Peak memory 445688 kb
Host smart-d8a63a60-2e58-49d3-85d7-93739a83ed92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1116045374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1116045374
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.792208600
Short name T361
Test name
Test status
Simulation time 5525242794 ps
CPU time 422.9 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:13:27 PM PST 23
Peak memory 202224 kb
Host smart-1ee95fa7-f157-433b-9384-d329ad18c15b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792208600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_stress_pipeline.792208600
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3204353006
Short name T443
Test name
Test status
Simulation time 3247801517 ps
CPU time 160.41 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:09:03 PM PST 23
Peak memory 367952 kb
Host smart-42faa0e7-77e6-42d4-8d47-ca063b71e5d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204353006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3204353006
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.154774829
Short name T19
Test name
Test status
Simulation time 77369048497 ps
CPU time 961.2 seconds
Started Dec 20 01:06:05 PM PST 23
Finished Dec 20 01:22:15 PM PST 23
Peak memory 379152 kb
Host smart-9f53b01e-3567-4503-a6b4-edd1f26be893
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154774829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.sram_ctrl_access_during_key_req.154774829
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.2590649743
Short name T558
Test name
Test status
Simulation time 51552979 ps
CPU time 0.64 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:06:25 PM PST 23
Peak memory 201916 kb
Host smart-a3d9e591-db18-406b-803b-8bdcd0ca31f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590649743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.2590649743
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.4215336902
Short name T241
Test name
Test status
Simulation time 50825179792 ps
CPU time 832.65 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:20:20 PM PST 23
Peak memory 202200 kb
Host smart-113f1a8a-5da6-43cc-9f47-9838d456d503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215336902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.4215336902
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.3434564794
Short name T43
Test name
Test status
Simulation time 1203654677 ps
CPU time 29.04 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:06:51 PM PST 23
Peak memory 210416 kb
Host smart-3ea39b40-2aec-45ab-b1e9-1411d5bbe6ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434564794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.3434564794
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.3044090683
Short name T964
Test name
Test status
Simulation time 1515356941 ps
CPU time 107.07 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:08:09 PM PST 23
Peak memory 316664 kb
Host smart-aa546c2c-4da4-41f5-8c9a-9749235cee29
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044090683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.3044090683
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3505546854
Short name T592
Test name
Test status
Simulation time 2664048779 ps
CPU time 81.37 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:07:42 PM PST 23
Peak memory 211204 kb
Host smart-c2a559bd-9150-449f-b18b-380ba3510251
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505546854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.3505546854
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.2840843816
Short name T147
Test name
Test status
Simulation time 15987033888 ps
CPU time 155.54 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:08:57 PM PST 23
Peak memory 202216 kb
Host smart-7c3ad011-3000-4dfb-ba23-9f5f57ad6d26
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840843816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.2840843816
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3967305248
Short name T965
Test name
Test status
Simulation time 14656072685 ps
CPU time 842.65 seconds
Started Dec 20 01:06:06 PM PST 23
Finished Dec 20 01:20:17 PM PST 23
Peak memory 382240 kb
Host smart-56c9c671-feb7-4e68-ac33-2d726db9ebf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967305248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3967305248
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.958581524
Short name T327
Test name
Test status
Simulation time 532668301 ps
CPU time 139.9 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:08:47 PM PST 23
Peak memory 364672 kb
Host smart-4845c645-c1f3-4026-b7d2-46d0c401a81a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958581524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.958581524
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.73999012
Short name T920
Test name
Test status
Simulation time 18202883684 ps
CPU time 278.12 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:11:05 PM PST 23
Peak memory 202268 kb
Host smart-4f6d0555-c80b-4045-a2a0-29a84e3b59e4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73999012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_partial_access_b2b.73999012
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.2637367271
Short name T897
Test name
Test status
Simulation time 365544278 ps
CPU time 6.73 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:06:29 PM PST 23
Peak memory 202456 kb
Host smart-ecf47a44-7561-4f5d-ae9b-255b73c3baf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637367271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2637367271
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.2113386463
Short name T131
Test name
Test status
Simulation time 73866663049 ps
CPU time 1044.45 seconds
Started Dec 20 01:06:14 PM PST 23
Finished Dec 20 01:23:50 PM PST 23
Peak memory 379156 kb
Host smart-09663558-d0ca-4c41-8806-4516d8b0abc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113386463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2113386463
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.1387132822
Short name T306
Test name
Test status
Simulation time 1150846934 ps
CPU time 17.86 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:06:41 PM PST 23
Peak memory 202156 kb
Host smart-b3107618-04f2-431b-9554-e51fb16ac965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387132822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1387132822
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1517221658
Short name T623
Test name
Test status
Simulation time 450994322 ps
CPU time 1696.19 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:34:40 PM PST 23
Peak memory 422360 kb
Host smart-500a792d-354f-46d2-ad4a-ed3df872802c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1517221658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1517221658
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2059434858
Short name T402
Test name
Test status
Simulation time 4808034075 ps
CPU time 340.47 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:11:58 PM PST 23
Peak memory 202256 kb
Host smart-216ff6f2-6bbb-405b-822c-a2de54429f71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059434858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.2059434858
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1958085407
Short name T658
Test name
Test status
Simulation time 2272072987 ps
CPU time 58.9 seconds
Started Dec 20 01:06:25 PM PST 23
Finished Dec 20 01:07:31 PM PST 23
Peak memory 288076 kb
Host smart-f688c8e2-9f3d-485c-97f0-fe71d61d95b9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958085407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.1958085407
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2338277582
Short name T426
Test name
Test status
Simulation time 2765304983 ps
CPU time 227.65 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:10:15 PM PST 23
Peak memory 329052 kb
Host smart-bf709970-595e-4a76-8c4b-2c4277c178bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338277582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.2338277582
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.2215257831
Short name T979
Test name
Test status
Simulation time 40472862 ps
CPU time 0.64 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:06:28 PM PST 23
Peak memory 201932 kb
Host smart-4631959c-78bd-47b5-92b6-a504a6b279de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215257831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.2215257831
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.1357261651
Short name T102
Test name
Test status
Simulation time 41608266556 ps
CPU time 922.3 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:21:44 PM PST 23
Peak memory 202208 kb
Host smart-2241b3fa-cd8b-467a-8f7b-8e5843b34f11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357261651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.1357261651
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.1859660399
Short name T403
Test name
Test status
Simulation time 26691499113 ps
CPU time 811.99 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:19:59 PM PST 23
Peak memory 369268 kb
Host smart-39849b70-0d2f-4025-a629-2671f7e1c80e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859660399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.1859660399
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.871087441
Short name T867
Test name
Test status
Simulation time 34732623622 ps
CPU time 87.2 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:07:54 PM PST 23
Peak memory 202240 kb
Host smart-2f0c9dc8-d4be-49e2-81be-4642d231bc01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871087441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc
alation.871087441
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3261430860
Short name T752
Test name
Test status
Simulation time 1655780914 ps
CPU time 142 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:08:45 PM PST 23
Peak memory 359868 kb
Host smart-e14c5c44-c85a-4ade-b3f3-20f4260b7e53
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261430860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3261430860
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1677576707
Short name T771
Test name
Test status
Simulation time 4806900046 ps
CPU time 152.89 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:08:59 PM PST 23
Peak memory 211812 kb
Host smart-8a220037-e24c-4aa2-a6d3-2a78abc81ca0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677576707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.1677576707
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2876434428
Short name T670
Test name
Test status
Simulation time 44898770473 ps
CPU time 318.79 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:11:43 PM PST 23
Peak memory 202248 kb
Host smart-73c1205b-721e-42fd-9280-8262d0ee0c67
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876434428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2876434428
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.2357989121
Short name T969
Test name
Test status
Simulation time 30703991291 ps
CPU time 680.47 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:17:47 PM PST 23
Peak memory 374064 kb
Host smart-1e7ed656-7e4d-4bd3-b442-e4be0f44c41a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357989121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.2357989121
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.691324514
Short name T898
Test name
Test status
Simulation time 494279073 ps
CPU time 11.12 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:06:38 PM PST 23
Peak memory 226120 kb
Host smart-f7dc167b-c54f-4678-94b6-ddad949e3328
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691324514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s
ram_ctrl_partial_access.691324514
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1236030172
Short name T476
Test name
Test status
Simulation time 28745196858 ps
CPU time 473.57 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 01:14:22 PM PST 23
Peak memory 202260 kb
Host smart-b58793c2-f7a3-4afd-b5d0-53c41b3bb97d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236030172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.1236030172
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.3359360818
Short name T273
Test name
Test status
Simulation time 1408338723 ps
CPU time 7 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:06:31 PM PST 23
Peak memory 202480 kb
Host smart-be7a482a-f4dd-46cd-9aa8-44a7d2cfbc89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359360818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3359360818
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.39900809
Short name T571
Test name
Test status
Simulation time 77769360376 ps
CPU time 1406.08 seconds
Started Dec 20 01:06:11 PM PST 23
Finished Dec 20 01:29:49 PM PST 23
Peak memory 376128 kb
Host smart-81dd06d6-1a1e-4b0e-ac0b-ad41759de6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.39900809
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.2859440767
Short name T960
Test name
Test status
Simulation time 1629034940 ps
CPU time 142.95 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:08:42 PM PST 23
Peak memory 373920 kb
Host smart-b0d88909-4f44-4482-bdef-f86acea72ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859440767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2859440767
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.176595469
Short name T719
Test name
Test status
Simulation time 168405774057 ps
CPU time 2416.24 seconds
Started Dec 20 01:06:14 PM PST 23
Finished Dec 20 01:46:43 PM PST 23
Peak memory 381184 kb
Host smart-33c3b248-1d12-464b-b8da-958493ae41d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176595469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_stress_all.176595469
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.926439862
Short name T531
Test name
Test status
Simulation time 815741796 ps
CPU time 2441.39 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:47:08 PM PST 23
Peak memory 413428 kb
Host smart-3039c1b1-7fb4-485b-a350-600bec79a630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=926439862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.926439862
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2099608407
Short name T334
Test name
Test status
Simulation time 7206826561 ps
CPU time 245.01 seconds
Started Dec 20 01:06:21 PM PST 23
Finished Dec 20 01:10:34 PM PST 23
Peak memory 202196 kb
Host smart-eb4bc5a1-3ef6-465a-b445-ba208ecc8ae0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099608407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.2099608407
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.494099809
Short name T948
Test name
Test status
Simulation time 3572440675 ps
CPU time 84.94 seconds
Started Dec 20 01:06:23 PM PST 23
Finished Dec 20 01:07:56 PM PST 23
Peak memory 329044 kb
Host smart-6fac2767-d66f-4caf-bdcf-2ab98ffc6612
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494099809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.494099809
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.4156633900
Short name T12
Test name
Test status
Simulation time 6239811682 ps
CPU time 777.03 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:19:25 PM PST 23
Peak memory 374900 kb
Host smart-e4c9c544-e516-4976-8d06-9c9f50e01691
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156633900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.4156633900
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.3570451499
Short name T406
Test name
Test status
Simulation time 83337885901 ps
CPU time 1386.83 seconds
Started Dec 20 01:06:18 PM PST 23
Finished Dec 20 01:29:35 PM PST 23
Peak memory 202116 kb
Host smart-95d8ff09-0de0-417d-8b14-cfb2cdc72786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570451499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.3570451499
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.3728778271
Short name T570
Test name
Test status
Simulation time 7103833146 ps
CPU time 100.62 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 01:08:09 PM PST 23
Peak memory 210472 kb
Host smart-37924661-fee0-4b20-9832-825a22d289a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728778271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.3728778271
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.709735056
Short name T262
Test name
Test status
Simulation time 743951331 ps
CPU time 48.63 seconds
Started Dec 20 01:06:14 PM PST 23
Finished Dec 20 01:07:15 PM PST 23
Peak memory 277812 kb
Host smart-f90671cd-0fe5-47c2-bf4c-bd3e262065b6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709735056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.sram_ctrl_max_throughput.709735056
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1172604115
Short name T835
Test name
Test status
Simulation time 2470747133 ps
CPU time 71.96 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:07:40 PM PST 23
Peak memory 210796 kb
Host smart-37a2cfc4-7bcc-4192-a75a-925f2b01633d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172604115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.1172604115
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1726524257
Short name T830
Test name
Test status
Simulation time 14330728384 ps
CPU time 271.09 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:10:59 PM PST 23
Peak memory 202192 kb
Host smart-dbbf5371-d2b9-41c5-93a3-aedfcd2d330c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726524257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1726524257
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.832428702
Short name T685
Test name
Test status
Simulation time 5502745524 ps
CPU time 459.14 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:14:07 PM PST 23
Peak memory 360364 kb
Host smart-c56acc77-d50f-49c9-a628-51cdd984662c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832428702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.832428702
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.1411218361
Short name T662
Test name
Test status
Simulation time 1225912677 ps
CPU time 22.03 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:06:49 PM PST 23
Peak memory 202164 kb
Host smart-e066f843-9381-461c-b230-27fc4fbb2d70
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411218361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.1411218361
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2840136881
Short name T527
Test name
Test status
Simulation time 7367350810 ps
CPU time 470.05 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:14:17 PM PST 23
Peak memory 202244 kb
Host smart-e3079020-d79a-49a4-a7d0-fbac6f1df1aa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840136881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.2840136881
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.4201651108
Short name T37
Test name
Test status
Simulation time 364227973 ps
CPU time 13.31 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:06:41 PM PST 23
Peak memory 202464 kb
Host smart-4070433b-e2d7-4753-8b9c-5fbeda64569b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201651108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.4201651108
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.3305667701
Short name T818
Test name
Test status
Simulation time 15281495361 ps
CPU time 608.04 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:16:36 PM PST 23
Peak memory 379116 kb
Host smart-91b0cbc7-ff20-46e3-ba07-c241fb31e8d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305667701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3305667701
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.1712926069
Short name T939
Test name
Test status
Simulation time 1335565101 ps
CPU time 20.28 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:06:48 PM PST 23
Peak memory 202028 kb
Host smart-1c75b629-aea4-46fa-bee8-974313fad2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712926069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1712926069
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2432247364
Short name T785
Test name
Test status
Simulation time 3140731971 ps
CPU time 313.75 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 01:11:42 PM PST 23
Peak memory 374064 kb
Host smart-7d85e1c0-db17-4ec4-b949-0c07b0648940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2432247364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2432247364
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.75883626
Short name T110
Test name
Test status
Simulation time 6356715789 ps
CPU time 408.23 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:13:16 PM PST 23
Peak memory 202144 kb
Host smart-93a9206e-fd2d-4099-96a6-750ab99d6676
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75883626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_stress_pipeline.75883626
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3615506322
Short name T353
Test name
Test status
Simulation time 752652180 ps
CPU time 63.49 seconds
Started Dec 20 01:06:18 PM PST 23
Finished Dec 20 01:07:32 PM PST 23
Peak memory 298896 kb
Host smart-6e13d6ed-1157-4a31-80aa-136f331498f2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615506322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.3615506322
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.462067284
Short name T972
Test name
Test status
Simulation time 7345447502 ps
CPU time 756.69 seconds
Started Dec 20 01:06:18 PM PST 23
Finished Dec 20 01:19:05 PM PST 23
Peak memory 368860 kb
Host smart-2ec879fa-183f-4055-9038-9fa655899856
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462067284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.sram_ctrl_access_during_key_req.462067284
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.344774071
Short name T469
Test name
Test status
Simulation time 21997412 ps
CPU time 0.63 seconds
Started Dec 20 01:06:23 PM PST 23
Finished Dec 20 01:06:31 PM PST 23
Peak memory 201492 kb
Host smart-703f4614-917e-4068-9a91-8f1b15e1365a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344774071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.344774071
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.4255607420
Short name T237
Test name
Test status
Simulation time 277304067956 ps
CPU time 1482.74 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:31:10 PM PST 23
Peak memory 202204 kb
Host smart-abdbaf01-2a71-4fb7-a63c-bead9d9f5562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255607420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.4255607420
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.2754403369
Short name T514
Test name
Test status
Simulation time 27752161347 ps
CPU time 36.22 seconds
Started Dec 20 01:06:14 PM PST 23
Finished Dec 20 01:07:02 PM PST 23
Peak memory 210480 kb
Host smart-1ae672f6-1e52-4ca5-a5bf-56198071ffee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754403369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.2754403369
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.2457666582
Short name T134
Test name
Test status
Simulation time 1389239809 ps
CPU time 29.7 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:06:56 PM PST 23
Peak memory 218556 kb
Host smart-b0b6628d-e575-40e9-82b6-c82c49fc40bb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457666582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.2457666582
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.980998490
Short name T352
Test name
Test status
Simulation time 1653254169 ps
CPU time 127.8 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:08:34 PM PST 23
Peak memory 218540 kb
Host smart-27f16944-f620-45f8-8a5f-fce00257c4ac
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980998490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_mem_partial_access.980998490
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.1547342751
Short name T456
Test name
Test status
Simulation time 7024344904 ps
CPU time 146.45 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 01:08:55 PM PST 23
Peak memory 202248 kb
Host smart-046c5ae1-4733-415b-b098-a70b563a3e45
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547342751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.1547342751
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3947253382
Short name T532
Test name
Test status
Simulation time 2621006571 ps
CPU time 43.9 seconds
Started Dec 20 01:06:20 PM PST 23
Finished Dec 20 01:07:13 PM PST 23
Peak memory 210264 kb
Host smart-ca630227-d79e-4c8d-838e-71aedd39e3b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947253382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3947253382
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.2798852292
Short name T454
Test name
Test status
Simulation time 1228902567 ps
CPU time 83.55 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:07:50 PM PST 23
Peak memory 318684 kb
Host smart-28c7fc79-255f-4bc4-86d9-e8d909df7b25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798852292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.2798852292
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2281534597
Short name T663
Test name
Test status
Simulation time 40446660439 ps
CPU time 481.39 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:14:29 PM PST 23
Peak memory 202212 kb
Host smart-91c4fc97-ff75-434b-bc20-a775a4f9fba1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281534597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.2281534597
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.42794881
Short name T900
Test name
Test status
Simulation time 1397043098 ps
CPU time 6.64 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 01:06:35 PM PST 23
Peak memory 202480 kb
Host smart-35a29a29-4088-470b-89ec-b125f8f73690
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.42794881
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.2455509989
Short name T28
Test name
Test status
Simulation time 3193323754 ps
CPU time 283.72 seconds
Started Dec 20 01:06:17 PM PST 23
Finished Dec 20 01:11:11 PM PST 23
Peak memory 353788 kb
Host smart-ca31ee6b-0340-41fd-b682-220a7ba3ba88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455509989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2455509989
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.308101508
Short name T356
Test name
Test status
Simulation time 2078660799 ps
CPU time 11.61 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:06:34 PM PST 23
Peak memory 202168 kb
Host smart-3464f723-2201-4a74-8eb4-f37a39158b37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308101508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.308101508
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.2738412754
Short name T425
Test name
Test status
Simulation time 181433271496 ps
CPU time 1916.4 seconds
Started Dec 20 01:06:12 PM PST 23
Finished Dec 20 01:38:20 PM PST 23
Peak memory 389400 kb
Host smart-aee3f984-4e6c-4db2-9f84-47ee6e3854da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738412754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.2738412754
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3589746409
Short name T460
Test name
Test status
Simulation time 220593558 ps
CPU time 874.48 seconds
Started Dec 20 01:06:24 PM PST 23
Finished Dec 20 01:21:06 PM PST 23
Peak memory 474396 kb
Host smart-767d275f-2e6d-4ea2-8f2e-06ef9df842aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3589746409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3589746409
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1702417136
Short name T851
Test name
Test status
Simulation time 23857467232 ps
CPU time 394.88 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:12:59 PM PST 23
Peak memory 202140 kb
Host smart-cdb3d520-2c1d-4457-b54f-ac957d5fb36b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702417136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.1702417136
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4124263670
Short name T247
Test name
Test status
Simulation time 1446643396 ps
CPU time 26.52 seconds
Started Dec 20 01:06:13 PM PST 23
Finished Dec 20 01:06:51 PM PST 23
Peak memory 210320 kb
Host smart-ee3b11b2-e552-4379-908f-aa9c5cee72d6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124263670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.4124263670
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.660067381
Short name T502
Test name
Test status
Simulation time 7798974019 ps
CPU time 280.62 seconds
Started Dec 20 01:05:22 PM PST 23
Finished Dec 20 01:10:22 PM PST 23
Peak memory 336812 kb
Host smart-26745b33-b755-434e-84d7-7ae97a8de9cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660067381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.sram_ctrl_access_during_key_req.660067381
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3106785999
Short name T336
Test name
Test status
Simulation time 42835026 ps
CPU time 0.65 seconds
Started Dec 20 01:05:11 PM PST 23
Finished Dec 20 01:05:36 PM PST 23
Peak memory 201956 kb
Host smart-d8fcb594-207a-4dc0-bec4-ae8e8bf9b8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106785999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3106785999
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.1661615848
Short name T149
Test name
Test status
Simulation time 77878662956 ps
CPU time 1286.22 seconds
Started Dec 20 01:05:10 PM PST 23
Finished Dec 20 01:27:01 PM PST 23
Peak memory 202028 kb
Host smart-eca0b894-0dfa-49bc-987a-31927ebe9f6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661615848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
1661615848
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.3338059166
Short name T783
Test name
Test status
Simulation time 23524737538 ps
CPU time 502.14 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:14:10 PM PST 23
Peak memory 361104 kb
Host smart-0153738d-0cef-4e0f-98a8-eaa44dfff82a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338059166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.3338059166
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.3165809393
Short name T46
Test name
Test status
Simulation time 752301996 ps
CPU time 41.48 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:06:20 PM PST 23
Peak memory 267600 kb
Host smart-f063d62a-0273-42ae-a8cf-38db528ee5b0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165809393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.3165809393
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2299140942
Short name T687
Test name
Test status
Simulation time 17360070006 ps
CPU time 152.65 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:08:18 PM PST 23
Peak memory 211284 kb
Host smart-f2983752-909d-4103-92c0-b14d5f8cbfa6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299140942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.2299140942
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.4138280277
Short name T499
Test name
Test status
Simulation time 35820954402 ps
CPU time 255.14 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:10:00 PM PST 23
Peak memory 202720 kb
Host smart-6d8484f1-b4e3-415e-a794-a8c35276dbb4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138280277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.4138280277
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.4080572435
Short name T374
Test name
Test status
Simulation time 5801282857 ps
CPU time 303.88 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:10:49 PM PST 23
Peak memory 376096 kb
Host smart-8ab4e681-514a-444c-8aee-eea1333adac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080572435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.4080572435
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.2605256078
Short name T884
Test name
Test status
Simulation time 504196916 ps
CPU time 107.14 seconds
Started Dec 20 01:05:05 PM PST 23
Finished Dec 20 01:07:17 PM PST 23
Peak memory 346312 kb
Host smart-32991dfb-094e-4bf3-9a96-2ac8c7d8a15a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605256078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.2605256078
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1070790674
Short name T669
Test name
Test status
Simulation time 52604207801 ps
CPU time 379.23 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:11:56 PM PST 23
Peak memory 202212 kb
Host smart-4d656097-4091-423a-9f45-00fe4ce8342d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070790674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.1070790674
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.2628030809
Short name T763
Test name
Test status
Simulation time 1342080936 ps
CPU time 13.13 seconds
Started Dec 20 01:05:21 PM PST 23
Finished Dec 20 01:05:54 PM PST 23
Peak memory 202484 kb
Host smart-e489ae01-2bbb-4b6d-a4dd-a0bfe9409793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628030809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2628030809
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.1311614761
Short name T325
Test name
Test status
Simulation time 48839474224 ps
CPU time 463.5 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:13:21 PM PST 23
Peak memory 348188 kb
Host smart-71c37610-f9f4-4209-815c-869132c71e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311614761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1311614761
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.1448813951
Short name T39
Test name
Test status
Simulation time 491289575 ps
CPU time 2.16 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:05:24 PM PST 23
Peak memory 232012 kb
Host smart-23154ac0-6271-4902-88ea-2e1426d76d28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448813951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.1448813951
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.3949188229
Short name T312
Test name
Test status
Simulation time 1782692087 ps
CPU time 28.64 seconds
Started Dec 20 01:05:18 PM PST 23
Finished Dec 20 01:06:07 PM PST 23
Peak memory 202120 kb
Host smart-18fb0627-bff2-4d92-9d19-7fcd9c40e312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949188229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3949188229
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2298052396
Short name T465
Test name
Test status
Simulation time 2263975730 ps
CPU time 1816.16 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:35:49 PM PST 23
Peak memory 729228 kb
Host smart-9860d0cc-8eb5-4e72-bf23-d8ab236d3b99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2298052396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2298052396
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3762390965
Short name T601
Test name
Test status
Simulation time 9694761422 ps
CPU time 282.27 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:10:27 PM PST 23
Peak memory 202156 kb
Host smart-705f82a8-25b4-45e1-874c-9332db9c07ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762390965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.3762390965
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1865134168
Short name T641
Test name
Test status
Simulation time 4321597970 ps
CPU time 76.72 seconds
Started Dec 20 01:05:10 PM PST 23
Finished Dec 20 01:06:51 PM PST 23
Peak memory 302524 kb
Host smart-43619c76-32e6-41e0-bd1e-15d0b8ad7bb3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865134168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1865134168
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1698627019
Short name T788
Test name
Test status
Simulation time 15559573110 ps
CPU time 1204.71 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:26:31 PM PST 23
Peak memory 381252 kb
Host smart-606beeda-914a-4690-b4d0-90065f85f140
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698627019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1698627019
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.538587566
Short name T565
Test name
Test status
Simulation time 80584919 ps
CPU time 0.64 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:07:12 PM PST 23
Peak memory 201908 kb
Host smart-739aa92c-eb0a-4ccb-bcda-13218993d0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538587566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.538587566
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.2985152409
Short name T238
Test name
Test status
Simulation time 197363929047 ps
CPU time 2095.59 seconds
Started Dec 20 01:06:09 PM PST 23
Finished Dec 20 01:41:14 PM PST 23
Peak memory 202072 kb
Host smart-49eb8a81-2404-40e3-bc03-c20777945deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985152409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.2985152409
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.964648315
Short name T766
Test name
Test status
Simulation time 35849263741 ps
CPU time 421.08 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 01:13:30 PM PST 23
Peak memory 366876 kb
Host smart-7d9e657b-a3e9-4af2-abf6-41140194f168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964648315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl
e.964648315
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.703434629
Short name T680
Test name
Test status
Simulation time 22038826785 ps
CPU time 79.11 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:07:39 PM PST 23
Peak memory 210452 kb
Host smart-f71b54ac-ee93-46c3-9a13-19dcda46afdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703434629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc
alation.703434629
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.2358998045
Short name T421
Test name
Test status
Simulation time 2857378438 ps
CPU time 41.5 seconds
Started Dec 20 01:06:18 PM PST 23
Finished Dec 20 01:07:10 PM PST 23
Peak memory 258912 kb
Host smart-adfb50e1-9010-437a-8f82-e0ca4fca0c9a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358998045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.2358998045
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.168576204
Short name T542
Test name
Test status
Simulation time 8892991173 ps
CPU time 143.65 seconds
Started Dec 20 01:06:41 PM PST 23
Finished Dec 20 01:09:30 PM PST 23
Peak memory 214380 kb
Host smart-2cb8c88c-1bff-4f4d-a107-4ab004576fbd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168576204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_mem_partial_access.168576204
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.4200748481
Short name T811
Test name
Test status
Simulation time 7115688748 ps
CPU time 142.57 seconds
Started Dec 20 01:06:48 PM PST 23
Finished Dec 20 01:09:37 PM PST 23
Peak memory 202200 kb
Host smart-94468023-39ba-4e02-8194-566a5122fcdb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200748481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.4200748481
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.3975288553
Short name T640
Test name
Test status
Simulation time 145265439034 ps
CPU time 889.97 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:21:17 PM PST 23
Peak memory 380080 kb
Host smart-f91254bf-f98f-444d-aaa3-72de6c78e3c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975288553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.3975288553
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2029463861
Short name T569
Test name
Test status
Simulation time 2817392032 ps
CPU time 154.9 seconds
Started Dec 20 01:06:16 PM PST 23
Finished Dec 20 01:09:02 PM PST 23
Peak memory 375244 kb
Host smart-d466780a-ea45-499c-83e7-5edd44e69bb9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029463861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2029463861
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3308858177
Short name T888
Test name
Test status
Simulation time 12224492656 ps
CPU time 301.06 seconds
Started Dec 20 01:06:19 PM PST 23
Finished Dec 20 01:11:30 PM PST 23
Peak memory 202236 kb
Host smart-02c3f5ae-5c58-48cb-a55f-72933d689238
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308858177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.3308858177
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.3446340325
Short name T730
Test name
Test status
Simulation time 1407947854 ps
CPU time 13.52 seconds
Started Dec 20 01:06:41 PM PST 23
Finished Dec 20 01:07:18 PM PST 23
Peak memory 202460 kb
Host smart-3f16c08f-28d3-4fb3-9f5b-657c027d970d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446340325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3446340325
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.2441327038
Short name T799
Test name
Test status
Simulation time 14602703518 ps
CPU time 1177.47 seconds
Started Dec 20 01:06:20 PM PST 23
Finished Dec 20 01:26:07 PM PST 23
Peak memory 377168 kb
Host smart-d69f11ac-a4b2-40ed-9839-0bf9ece2ee12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441327038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2441327038
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.2711029577
Short name T368
Test name
Test status
Simulation time 803003735 ps
CPU time 136.16 seconds
Started Dec 20 01:06:23 PM PST 23
Finished Dec 20 01:08:47 PM PST 23
Peak memory 374908 kb
Host smart-a66741e8-2fc4-40b6-aaed-9be6bfda646b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711029577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2711029577
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1907364775
Short name T347
Test name
Test status
Simulation time 6191613291 ps
CPU time 2601.6 seconds
Started Dec 20 01:06:40 PM PST 23
Finished Dec 20 01:50:26 PM PST 23
Peak memory 632664 kb
Host smart-cfc7ed98-6511-4053-82d4-ac8ddadd198a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1907364775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1907364775
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1322493231
Short name T689
Test name
Test status
Simulation time 4957798022 ps
CPU time 353.35 seconds
Started Dec 20 01:06:15 PM PST 23
Finished Dec 20 01:12:20 PM PST 23
Peak memory 210432 kb
Host smart-620298eb-d34f-4d23-a08d-6db26f1c1c0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322493231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.1322493231
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1594149508
Short name T778
Test name
Test status
Simulation time 5954618083 ps
CPU time 44.48 seconds
Started Dec 20 01:06:10 PM PST 23
Finished Dec 20 01:07:05 PM PST 23
Peak memory 270780 kb
Host smart-565cd3bf-0dd2-44c8-bcf1-a1b686df3e04
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594149508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1594149508
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2765911013
Short name T661
Test name
Test status
Simulation time 40450797623 ps
CPU time 915.04 seconds
Started Dec 20 01:06:41 PM PST 23
Finished Dec 20 01:22:20 PM PST 23
Peak memory 367956 kb
Host smart-621a116d-e1e9-4022-aef1-becb65673399
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765911013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.2765911013
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.1305863741
Short name T258
Test name
Test status
Simulation time 78429885 ps
CPU time 0.66 seconds
Started Dec 20 01:06:49 PM PST 23
Finished Dec 20 01:07:15 PM PST 23
Peak memory 201960 kb
Host smart-2b5f6af6-fc00-4796-b832-aa8a453d9bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305863741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.1305863741
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.4093828592
Short name T821
Test name
Test status
Simulation time 34516278009 ps
CPU time 2162.21 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:43:12 PM PST 23
Peak memory 202144 kb
Host smart-835c0727-530c-4b69-abe9-7d9a1e789839
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093828592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.4093828592
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.1882979349
Short name T116
Test name
Test status
Simulation time 2607961349 ps
CPU time 33.83 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:07:44 PM PST 23
Peak memory 213284 kb
Host smart-81a776eb-51a4-4c19-b341-1083f381c23e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882979349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.1882979349
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.2084473797
Short name T647
Test name
Test status
Simulation time 739418861 ps
CPU time 101 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:08:51 PM PST 23
Peak memory 317900 kb
Host smart-fc4b910b-3f10-4cdf-bb6a-5f284051ab9a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084473797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.2084473797
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1913516022
Short name T50
Test name
Test status
Simulation time 5049229008 ps
CPU time 81.52 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:08:32 PM PST 23
Peak memory 211932 kb
Host smart-1bd3d414-fe53-4400-929d-bfef5bf1cb36
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913516022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1913516022
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.232136174
Short name T722
Test name
Test status
Simulation time 14338387830 ps
CPU time 273.47 seconds
Started Dec 20 01:06:47 PM PST 23
Finished Dec 20 01:11:48 PM PST 23
Peak memory 202340 kb
Host smart-867bf9cb-d2d0-47ce-9695-311a21aab6a0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232136174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl
_mem_walk.232136174
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.986856994
Short name T691
Test name
Test status
Simulation time 24401533448 ps
CPU time 871.89 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:21:42 PM PST 23
Peak memory 380204 kb
Host smart-28eda01f-1625-4457-8566-220abdf57110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986856994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip
le_keys.986856994
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.4153860783
Short name T423
Test name
Test status
Simulation time 2666614883 ps
CPU time 10.65 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:07:20 PM PST 23
Peak memory 202176 kb
Host smart-fdaae1a3-1d7f-4d23-b931-5411e18acf2a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153860783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.4153860783
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.285925862
Short name T940
Test name
Test status
Simulation time 31739222848 ps
CPU time 475.9 seconds
Started Dec 20 01:06:38 PM PST 23
Finished Dec 20 01:14:51 PM PST 23
Peak memory 202132 kb
Host smart-7ea407b6-9ba1-4ada-b6e4-1557deb0a1a6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285925862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.285925862
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.88131214
Short name T379
Test name
Test status
Simulation time 363194212 ps
CPU time 5.52 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:07:15 PM PST 23
Peak memory 202468 kb
Host smart-4719496c-d408-46ed-83c3-152b2884085a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88131214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.88131214
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.3210079194
Short name T143
Test name
Test status
Simulation time 4682360830 ps
CPU time 378.52 seconds
Started Dec 20 01:06:44 PM PST 23
Finished Dec 20 01:13:28 PM PST 23
Peak memory 361400 kb
Host smart-2bf1f88a-fead-49b9-9632-2bfa3c1870a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210079194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3210079194
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.2923609519
Short name T274
Test name
Test status
Simulation time 8289480781 ps
CPU time 63.31 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:08:13 PM PST 23
Peak memory 311568 kb
Host smart-8bcc5c41-f497-4b93-ae59-abed8c45be30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923609519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2923609519
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2614906721
Short name T679
Test name
Test status
Simulation time 6014274060 ps
CPU time 1100.92 seconds
Started Dec 20 01:06:49 PM PST 23
Finished Dec 20 01:25:36 PM PST 23
Peak memory 416540 kb
Host smart-dec94315-b397-47c0-89c9-436809685825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2614906721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2614906721
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3391990626
Short name T750
Test name
Test status
Simulation time 21094648647 ps
CPU time 406.78 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:13:57 PM PST 23
Peak memory 202068 kb
Host smart-cdb75d06-1265-460c-8ea4-f7fcb8513f37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391990626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3391990626
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3981309307
Short name T137
Test name
Test status
Simulation time 7780380617 ps
CPU time 140.66 seconds
Started Dec 20 01:06:44 PM PST 23
Finished Dec 20 01:09:31 PM PST 23
Peak memory 363792 kb
Host smart-7ee0d061-3f4a-442d-b865-d204a993a918
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981309307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3981309307
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.39044653
Short name T40
Test name
Test status
Simulation time 34106449702 ps
CPU time 1021.76 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:24:13 PM PST 23
Peak memory 379132 kb
Host smart-a8e89826-49f5-47f1-8541-898de05bc0eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39044653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.sram_ctrl_access_during_key_req.39044653
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.2323882343
Short name T271
Test name
Test status
Simulation time 41728945 ps
CPU time 0.67 seconds
Started Dec 20 01:06:41 PM PST 23
Finished Dec 20 01:07:05 PM PST 23
Peak memory 201464 kb
Host smart-7479cd17-5c10-442e-ae34-5ae6ee7a7c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323882343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.2323882343
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.889691496
Short name T776
Test name
Test status
Simulation time 61502644107 ps
CPU time 1005.63 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:24:06 PM PST 23
Peak memory 202080 kb
Host smart-501616cc-2a60-45d5-8509-0f4bced31a9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889691496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.
889691496
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.1441480185
Short name T639
Test name
Test status
Simulation time 22883942302 ps
CPU time 654.08 seconds
Started Dec 20 01:06:44 PM PST 23
Finished Dec 20 01:18:04 PM PST 23
Peak memory 366688 kb
Host smart-cdaabe46-2065-4624-b5ec-4f89551b9301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441480185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.1441480185
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.174801676
Short name T362
Test name
Test status
Simulation time 41576677426 ps
CPU time 126.88 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:09:17 PM PST 23
Peak memory 210404 kb
Host smart-1f0804a6-12bb-46f1-a5d1-34df6ffa7d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174801676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc
alation.174801676
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.1353132361
Short name T852
Test name
Test status
Simulation time 3259984376 ps
CPU time 119.47 seconds
Started Dec 20 01:06:47 PM PST 23
Finished Dec 20 01:09:14 PM PST 23
Peak memory 333152 kb
Host smart-fe0a957a-6db7-45dc-a336-5046480286d5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353132361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.1353132361
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1543128875
Short name T917
Test name
Test status
Simulation time 5328585727 ps
CPU time 77.48 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:08:33 PM PST 23
Peak memory 211568 kb
Host smart-b4eabbb6-fcad-4b89-96f0-d92184147783
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543128875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.1543128875
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.1692755649
Short name T751
Test name
Test status
Simulation time 16412943757 ps
CPU time 248.73 seconds
Started Dec 20 01:06:47 PM PST 23
Finished Dec 20 01:11:23 PM PST 23
Peak memory 202584 kb
Host smart-a280fffc-fc82-4c9f-af03-7301fb07edf0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692755649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.1692755649
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.274371533
Short name T459
Test name
Test status
Simulation time 12967194376 ps
CPU time 476.02 seconds
Started Dec 20 01:06:49 PM PST 23
Finished Dec 20 01:15:11 PM PST 23
Peak memory 379208 kb
Host smart-4379d6ff-34d3-4c46-a057-5abf1372033f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274371533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip
le_keys.274371533
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.4200447290
Short name T242
Test name
Test status
Simulation time 2900385192 ps
CPU time 42.83 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:07:54 PM PST 23
Peak memory 253180 kb
Host smart-a3ee1b30-7fd2-4523-a760-7c122fb8d0d7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200447290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.4200447290
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4056768241
Short name T109
Test name
Test status
Simulation time 32177445271 ps
CPU time 253.46 seconds
Started Dec 20 01:06:52 PM PST 23
Finished Dec 20 01:11:30 PM PST 23
Peak memory 202004 kb
Host smart-ab8c7de1-3531-4cd1-9e04-dd5452564113
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056768241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.4056768241
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.1954079034
Short name T372
Test name
Test status
Simulation time 1403098395 ps
CPU time 6.82 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:07:22 PM PST 23
Peak memory 202468 kb
Host smart-7698c98e-ed07-423a-8171-71d00874ed85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954079034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1954079034
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.2133949399
Short name T831
Test name
Test status
Simulation time 1716657369 ps
CPU time 7.9 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:07:27 PM PST 23
Peak memory 210736 kb
Host smart-f217a8d2-79b5-4ca5-a36d-b5ab9fd7f790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133949399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2133949399
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.408577038
Short name T947
Test name
Test status
Simulation time 736852761 ps
CPU time 12.42 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:07:33 PM PST 23
Peak memory 210004 kb
Host smart-36e906c4-269b-4dac-b9a6-975ab88dc9d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408577038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.408577038
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.1109507913
Short name T874
Test name
Test status
Simulation time 134250520771 ps
CPU time 2847.56 seconds
Started Dec 20 01:06:39 PM PST 23
Finished Dec 20 01:54:30 PM PST 23
Peak memory 349808 kb
Host smart-ff4488d8-e49c-442d-ac73-896c2c9e8607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109507913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.1109507913
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3724354406
Short name T726
Test name
Test status
Simulation time 3436297063 ps
CPU time 1803.06 seconds
Started Dec 20 01:06:53 PM PST 23
Finished Dec 20 01:37:19 PM PST 23
Peak memory 460600 kb
Host smart-5946ae66-db37-4155-9d40-0d83a7ab3b3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3724354406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3724354406
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2648029511
Short name T433
Test name
Test status
Simulation time 19685345897 ps
CPU time 176.27 seconds
Started Dec 20 01:06:53 PM PST 23
Finished Dec 20 01:10:13 PM PST 23
Peak memory 202248 kb
Host smart-abb0c046-9ba2-4dad-ae49-506ea264d82f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648029511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.2648029511
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1378162294
Short name T342
Test name
Test status
Simulation time 1470025416 ps
CPU time 61.7 seconds
Started Dec 20 01:06:46 PM PST 23
Finished Dec 20 01:08:16 PM PST 23
Peak memory 294800 kb
Host smart-1217b569-b33e-4cd2-bde3-2d46efc64d73
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378162294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1378162294
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.137107912
Short name T723
Test name
Test status
Simulation time 40592271 ps
CPU time 0.63 seconds
Started Dec 20 01:06:46 PM PST 23
Finished Dec 20 01:07:15 PM PST 23
Peak memory 201920 kb
Host smart-496b74fd-36be-46c3-ad89-2fd0d3c52d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137107912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.137107912
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.2169710221
Short name T654
Test name
Test status
Simulation time 23161039823 ps
CPU time 1508.22 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:32:18 PM PST 23
Peak memory 202240 kb
Host smart-2b5267bb-ea51-4bad-a873-f0d416c8ad8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169710221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.2169710221
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.353320598
Short name T620
Test name
Test status
Simulation time 9323281462 ps
CPU time 258.63 seconds
Started Dec 20 01:06:46 PM PST 23
Finished Dec 20 01:11:33 PM PST 23
Peak memory 370908 kb
Host smart-54df5742-6bad-4c2d-b051-caa6c751b83f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353320598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl
e.353320598
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3050894948
Short name T986
Test name
Test status
Simulation time 13295213260 ps
CPU time 151.76 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:09:42 PM PST 23
Peak memory 210452 kb
Host smart-fcfda5f6-fd10-43a8-a52c-66929df3478f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050894948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3050894948
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.710355837
Short name T836
Test name
Test status
Simulation time 2991475985 ps
CPU time 56.48 seconds
Started Dec 20 01:06:33 PM PST 23
Finished Dec 20 01:07:38 PM PST 23
Peak memory 284008 kb
Host smart-81c19e0f-a444-4b0f-bdb9-6b9d3745636e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710355837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_max_throughput.710355837
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.150425950
Short name T489
Test name
Test status
Simulation time 959292020 ps
CPU time 74.9 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:08:25 PM PST 23
Peak memory 218564 kb
Host smart-9642257e-2910-47fe-b7fa-3f218f07c4fa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150425950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.sram_ctrl_mem_partial_access.150425950
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.3026916198
Short name T449
Test name
Test status
Simulation time 85959161649 ps
CPU time 326.41 seconds
Started Dec 20 01:06:50 PM PST 23
Finished Dec 20 01:12:41 PM PST 23
Peak memory 202232 kb
Host smart-4d47f6cc-819a-44c9-b603-9163bf8d36b4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026916198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.3026916198
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.784846384
Short name T383
Test name
Test status
Simulation time 8426219684 ps
CPU time 942.8 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:22:52 PM PST 23
Peak memory 367900 kb
Host smart-21a17ece-65d2-4753-a3cb-74695bd9d005
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784846384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip
le_keys.784846384
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.948701113
Short name T877
Test name
Test status
Simulation time 8883590885 ps
CPU time 19.79 seconds
Started Dec 20 01:06:40 PM PST 23
Finished Dec 20 01:07:23 PM PST 23
Peak memory 202164 kb
Host smart-cac70661-3198-45b8-b2ec-a3ea8af4854d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948701113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s
ram_ctrl_partial_access.948701113
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.585112671
Short name T812
Test name
Test status
Simulation time 13913423079 ps
CPU time 332.86 seconds
Started Dec 20 01:06:44 PM PST 23
Finished Dec 20 01:12:43 PM PST 23
Peak memory 202220 kb
Host smart-e6ef7332-2307-451e-a957-7fddbb4aa686
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585112671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.sram_ctrl_partial_access_b2b.585112671
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.1266059623
Short name T331
Test name
Test status
Simulation time 1600754470 ps
CPU time 13.65 seconds
Started Dec 20 01:06:45 PM PST 23
Finished Dec 20 01:07:25 PM PST 23
Peak memory 202508 kb
Host smart-a551951c-d57c-4d9c-8a52-08cd5e510f9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266059623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1266059623
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3210101981
Short name T921
Test name
Test status
Simulation time 8996265449 ps
CPU time 383.87 seconds
Started Dec 20 01:06:41 PM PST 23
Finished Dec 20 01:13:30 PM PST 23
Peak memory 343204 kb
Host smart-678593ce-53dd-471c-929f-533f6f6294e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210101981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3210101981
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.1502356092
Short name T517
Test name
Test status
Simulation time 5334092973 ps
CPU time 23.23 seconds
Started Dec 20 01:06:47 PM PST 23
Finished Dec 20 01:07:38 PM PST 23
Peak memory 202212 kb
Host smart-4d3b7fb1-650b-4753-8e03-94b9d7a4fbbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502356092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1502356092
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.561732193
Short name T597
Test name
Test status
Simulation time 1666766818 ps
CPU time 1957.77 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:39:48 PM PST 23
Peak memory 472420 kb
Host smart-85216679-140c-448f-8d7a-b2de7bb340bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=561732193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.561732193
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.100827970
Short name T937
Test name
Test status
Simulation time 19256281840 ps
CPU time 214.29 seconds
Started Dec 20 01:06:34 PM PST 23
Finished Dec 20 01:10:16 PM PST 23
Peak memory 202248 kb
Host smart-e4197a81-0774-4f02-a10f-8d3de81a5d72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100827970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.sram_ctrl_stress_pipeline.100827970
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1667992256
Short name T493
Test name
Test status
Simulation time 1468540675 ps
CPU time 29.79 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:07:39 PM PST 23
Peak memory 218496 kb
Host smart-8429626b-47ba-4dbf-bedc-039d43b0f5d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667992256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1667992256
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1116701637
Short name T557
Test name
Test status
Simulation time 60888072267 ps
CPU time 1079.47 seconds
Started Dec 20 01:06:32 PM PST 23
Finished Dec 20 01:24:34 PM PST 23
Peak memory 380288 kb
Host smart-4501b71a-480c-4ba7-9f16-9a8b37cc9d0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116701637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.1116701637
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.4258803810
Short name T475
Test name
Test status
Simulation time 23096589 ps
CPU time 0.65 seconds
Started Dec 20 01:06:32 PM PST 23
Finished Dec 20 01:06:34 PM PST 23
Peak memory 201284 kb
Host smart-454438cc-5635-433b-b724-26fbbc0fbebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258803810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.4258803810
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.1647228385
Short name T816
Test name
Test status
Simulation time 540436925450 ps
CPU time 1152.97 seconds
Started Dec 20 01:06:32 PM PST 23
Finished Dec 20 01:25:48 PM PST 23
Peak memory 202320 kb
Host smart-2b159a17-39fa-43b8-8028-877781344ed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647228385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.1647228385
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.4050840091
Short name T536
Test name
Test status
Simulation time 93523214494 ps
CPU time 1126.37 seconds
Started Dec 20 01:06:34 PM PST 23
Finished Dec 20 01:25:28 PM PST 23
Peak memory 378144 kb
Host smart-b9555a4c-d690-4744-be3a-c6bc7d068e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050840091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.4050840091
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.3560242300
Short name T660
Test name
Test status
Simulation time 35868429717 ps
CPU time 181.23 seconds
Started Dec 20 01:06:33 PM PST 23
Finished Dec 20 01:09:40 PM PST 23
Peak memory 210500 kb
Host smart-53f80de6-c49e-4b51-b080-d6a4164b62cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560242300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.3560242300
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.2925949019
Short name T394
Test name
Test status
Simulation time 9141853954 ps
CPU time 71.5 seconds
Started Dec 20 01:06:33 PM PST 23
Finished Dec 20 01:07:50 PM PST 23
Peak memory 314660 kb
Host smart-04e5b972-4654-4e7c-b9b4-085309c09965
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925949019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.2925949019
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.274764548
Short name T435
Test name
Test status
Simulation time 48538241742 ps
CPU time 148.74 seconds
Started Dec 20 01:06:35 PM PST 23
Finished Dec 20 01:09:14 PM PST 23
Peak memory 214536 kb
Host smart-af55c2b3-525b-4ce6-ad24-eca841cc46b3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274764548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_mem_partial_access.274764548
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.1108688051
Short name T863
Test name
Test status
Simulation time 1979698439 ps
CPU time 128.49 seconds
Started Dec 20 01:06:33 PM PST 23
Finished Dec 20 01:08:48 PM PST 23
Peak memory 202136 kb
Host smart-87b8dc84-ce9c-4629-b842-1cfb805849fd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108688051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.1108688051
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.4251006607
Short name T385
Test name
Test status
Simulation time 8866528909 ps
CPU time 1146.18 seconds
Started Dec 20 01:06:34 PM PST 23
Finished Dec 20 01:25:48 PM PST 23
Peak memory 379256 kb
Host smart-6ca2619e-02ee-4b96-a3ec-5b15c5487f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251006607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.4251006607
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.2057940593
Short name T393
Test name
Test status
Simulation time 962281918 ps
CPU time 16.17 seconds
Started Dec 20 01:06:32 PM PST 23
Finished Dec 20 01:06:52 PM PST 23
Peak memory 202232 kb
Host smart-3e85006d-6575-4586-b037-97096bd1dd37
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057940593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.2057940593
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.748812713
Short name T697
Test name
Test status
Simulation time 28979917077 ps
CPU time 495.75 seconds
Started Dec 20 01:06:31 PM PST 23
Finished Dec 20 01:14:49 PM PST 23
Peak memory 202252 kb
Host smart-244976b4-1147-4911-9ed6-125844fabff1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748812713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.sram_ctrl_partial_access_b2b.748812713
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.2642821880
Short name T609
Test name
Test status
Simulation time 1527504454 ps
CPU time 13.97 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:07:24 PM PST 23
Peak memory 202488 kb
Host smart-84c0c335-6868-4bc3-b753-76d10a50374c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642821880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2642821880
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.1673505650
Short name T127
Test name
Test status
Simulation time 20981577129 ps
CPU time 939.19 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:22:49 PM PST 23
Peak memory 379132 kb
Host smart-0720858d-979f-4963-a1b8-65791f29344a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673505650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1673505650
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.96949372
Short name T307
Test name
Test status
Simulation time 2864764525 ps
CPU time 32.9 seconds
Started Dec 20 01:07:00 PM PST 23
Finished Dec 20 01:07:56 PM PST 23
Peak memory 229788 kb
Host smart-da2b56c6-b352-4ae8-a30e-a19af6d16912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96949372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.96949372
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.1059628069
Short name T636
Test name
Test status
Simulation time 212828464043 ps
CPU time 4036.51 seconds
Started Dec 20 01:06:32 PM PST 23
Finished Dec 20 02:13:52 PM PST 23
Peak memory 381292 kb
Host smart-e96ed151-b48a-40ab-a9ad-1399b911fc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059628069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.1059628069
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1587104806
Short name T803
Test name
Test status
Simulation time 507149663 ps
CPU time 1458.72 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:31:29 PM PST 23
Peak memory 436096 kb
Host smart-07f5aa8e-d737-45d1-8c24-7c710eca7a98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1587104806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1587104806
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1723328088
Short name T373
Test name
Test status
Simulation time 3017395535 ps
CPU time 255.65 seconds
Started Dec 20 01:06:44 PM PST 23
Finished Dec 20 01:11:26 PM PST 23
Peak memory 202268 kb
Host smart-89270fe3-d517-4ee1-96c8-2ac201ef4492
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723328088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.1723328088
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.974461641
Short name T955
Test name
Test status
Simulation time 1505282174 ps
CPU time 43.77 seconds
Started Dec 20 01:06:35 PM PST 23
Finished Dec 20 01:07:25 PM PST 23
Peak memory 273552 kb
Host smart-686b70bf-a26b-49b1-a42b-273052651a6f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974461641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_throughput_w_partial_write.974461641
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2630309384
Short name T607
Test name
Test status
Simulation time 5742359621 ps
CPU time 615.98 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:17:33 PM PST 23
Peak memory 371904 kb
Host smart-6699258a-320c-48f2-8af9-cbbe4476a693
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630309384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.2630309384
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.4042494942
Short name T22
Test name
Test status
Simulation time 64234648 ps
CPU time 0.64 seconds
Started Dec 20 01:06:52 PM PST 23
Finished Dec 20 01:07:16 PM PST 23
Peak memory 201928 kb
Host smart-5443fe2f-0f53-4508-9b19-ef25937459bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042494942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.4042494942
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.435165906
Short name T931
Test name
Test status
Simulation time 144749247167 ps
CPU time 564.22 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:16:34 PM PST 23
Peak memory 202284 kb
Host smart-796367ff-66f9-44d0-952e-a9516cb0dc0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435165906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.
435165906
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.649749795
Short name T837
Test name
Test status
Simulation time 85278764040 ps
CPU time 897.38 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:22:13 PM PST 23
Peak memory 373004 kb
Host smart-eafdca56-5b60-4cdf-8b24-6ff15324e53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649749795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executabl
e.649749795
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.3464209345
Short name T651
Test name
Test status
Simulation time 23260241172 ps
CPU time 145.33 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:09:42 PM PST 23
Peak memory 214364 kb
Host smart-fe1511a4-fb69-4162-8952-9c2cc471bf2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464209345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.3464209345
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.251838964
Short name T864
Test name
Test status
Simulation time 3306679068 ps
CPU time 71 seconds
Started Dec 20 01:06:56 PM PST 23
Finished Dec 20 01:08:32 PM PST 23
Peak memory 309356 kb
Host smart-f5cfe493-f263-4ee7-ad37-28dfe51c7b4b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251838964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.sram_ctrl_max_throughput.251838964
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1039532684
Short name T302
Test name
Test status
Simulation time 1834661304 ps
CPU time 75.55 seconds
Started Dec 20 01:06:52 PM PST 23
Finished Dec 20 01:08:31 PM PST 23
Peak memory 218516 kb
Host smart-b89e6a5b-87fc-4b1f-8ba2-0b1ed3155c8a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039532684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.1039532684
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.998851576
Short name T593
Test name
Test status
Simulation time 68877114409 ps
CPU time 154.31 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:09:53 PM PST 23
Peak memory 202344 kb
Host smart-1aaf57b4-551c-4275-b323-c448de68b873
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998851576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl
_mem_walk.998851576
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.619405209
Short name T321
Test name
Test status
Simulation time 4166993700 ps
CPU time 178.3 seconds
Started Dec 20 01:06:34 PM PST 23
Finished Dec 20 01:09:40 PM PST 23
Peak memory 374840 kb
Host smart-d8f2ccba-9a90-478e-8db2-3cf835f88219
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619405209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip
le_keys.619405209
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.2969760525
Short name T389
Test name
Test status
Simulation time 4297835790 ps
CPU time 18.3 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:07:28 PM PST 23
Peak memory 239088 kb
Host smart-5ad3ca2f-d05c-4c2c-8ce8-cb341bcbcefb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969760525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.2969760525
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2573891288
Short name T774
Test name
Test status
Simulation time 9529153670 ps
CPU time 616.45 seconds
Started Dec 20 01:06:43 PM PST 23
Finished Dec 20 01:17:26 PM PST 23
Peak memory 202240 kb
Host smart-d29f77b9-7628-4a31-95c4-4254e2adc785
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573891288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.2573891288
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.3448673906
Short name T556
Test name
Test status
Simulation time 1405044961 ps
CPU time 6.65 seconds
Started Dec 20 01:06:57 PM PST 23
Finished Dec 20 01:07:27 PM PST 23
Peak memory 202496 kb
Host smart-63384640-c450-4d4d-90ff-464362edd9f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448673906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3448673906
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.4164103749
Short name T418
Test name
Test status
Simulation time 10113703441 ps
CPU time 1073.57 seconds
Started Dec 20 01:06:52 PM PST 23
Finished Dec 20 01:25:09 PM PST 23
Peak memory 380160 kb
Host smart-600833e3-1e78-4907-bbe2-3c2f78138a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164103749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.4164103749
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.951667527
Short name T916
Test name
Test status
Simulation time 2335595715 ps
CPU time 89.87 seconds
Started Dec 20 01:06:42 PM PST 23
Finished Dec 20 01:08:39 PM PST 23
Peak memory 329104 kb
Host smart-30c5651c-2be6-438a-ac74-f007045916ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951667527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.951667527
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2933607368
Short name T809
Test name
Test status
Simulation time 179098929 ps
CPU time 2414.12 seconds
Started Dec 20 01:06:53 PM PST 23
Finished Dec 20 01:47:31 PM PST 23
Peak memory 610892 kb
Host smart-dbb151f6-ac51-4bc5-b066-cd0bc7b5b08a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2933607368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2933607368
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3560380216
Short name T396
Test name
Test status
Simulation time 2003093782 ps
CPU time 153.46 seconds
Started Dec 20 01:06:39 PM PST 23
Finished Dec 20 01:09:35 PM PST 23
Peak memory 210380 kb
Host smart-ff75096e-6b9b-4ba6-9b41-c97cbe1fedbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560380216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.3560380216
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2530884981
Short name T953
Test name
Test status
Simulation time 2785420025 ps
CPU time 28.31 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:07:45 PM PST 23
Peak memory 210408 kb
Host smart-5946d059-c507-4372-8c8e-5e78d82b9bc4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530884981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2530884981
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.746666877
Short name T80
Test name
Test status
Simulation time 33615990233 ps
CPU time 84.76 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:08:46 PM PST 23
Peak memory 203620 kb
Host smart-28b9b6e3-8a08-4017-a5b1-4a9d7e0cfa5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746666877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.sram_ctrl_access_during_key_req.746666877
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.237777277
Short name T350
Test name
Test status
Simulation time 13545799 ps
CPU time 0.67 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:07:21 PM PST 23
Peak memory 201384 kb
Host smart-d1f4ab42-c52f-4f69-906a-3a0b2b7ba871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237777277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.237777277
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.367776078
Short name T938
Test name
Test status
Simulation time 46190753206 ps
CPU time 1083.1 seconds
Started Dec 20 01:06:52 PM PST 23
Finished Dec 20 01:25:20 PM PST 23
Peak memory 202136 kb
Host smart-4b05c62f-dc86-4338-a150-b70490d7190f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367776078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.
367776078
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.4088806009
Short name T794
Test name
Test status
Simulation time 24458178635 ps
CPU time 1100.47 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:25:39 PM PST 23
Peak memory 380164 kb
Host smart-9cf7b2a3-c3a8-4507-b948-7b745041cec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088806009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.4088806009
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.643353752
Short name T883
Test name
Test status
Simulation time 22994176573 ps
CPU time 60.7 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:08:22 PM PST 23
Peak memory 210500 kb
Host smart-1a440670-f3b0-4c7d-b8fd-fc6e9a08532d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643353752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc
alation.643353752
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.2748479541
Short name T41
Test name
Test status
Simulation time 5141337799 ps
CPU time 26.59 seconds
Started Dec 20 01:06:56 PM PST 23
Finished Dec 20 01:07:47 PM PST 23
Peak memory 214980 kb
Host smart-36af2b3f-ba46-497f-adc2-c8af6adf5a97
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748479541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.2748479541
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2642480522
Short name T599
Test name
Test status
Simulation time 4847553638 ps
CPU time 131.92 seconds
Started Dec 20 01:06:48 PM PST 23
Finished Dec 20 01:09:27 PM PST 23
Peak memory 211272 kb
Host smart-7d42530b-932b-4501-93f9-fd22d7a16119
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642480522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.2642480522
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.1321530558
Short name T993
Test name
Test status
Simulation time 14070495633 ps
CPU time 245.81 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:11:23 PM PST 23
Peak memory 202204 kb
Host smart-0c5d7ccd-4189-406e-bc75-c121842fbabd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321530558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.1321530558
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.1076984144
Short name T344
Test name
Test status
Simulation time 48590230207 ps
CPU time 260.39 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:11:36 PM PST 23
Peak memory 368712 kb
Host smart-74eeef1a-7fb0-43d1-9194-37823891c58b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076984144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.1076984144
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.1821135677
Short name T445
Test name
Test status
Simulation time 895334478 ps
CPU time 22.41 seconds
Started Dec 20 01:06:53 PM PST 23
Finished Dec 20 01:07:38 PM PST 23
Peak memory 243044 kb
Host smart-1d8d8802-f5d7-4d54-9a96-250e0d6b3772
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821135677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.1821135677
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3879460121
Short name T446
Test name
Test status
Simulation time 19170277879 ps
CPU time 442.37 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:14:38 PM PST 23
Peak memory 210392 kb
Host smart-e12c4cd0-98eb-4296-95f9-2e870590f5b5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879460121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.3879460121
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.415657883
Short name T602
Test name
Test status
Simulation time 4178143388 ps
CPU time 14.39 seconds
Started Dec 20 01:06:57 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 202564 kb
Host smart-1f4e4d48-d821-4d82-8916-378e84089d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415657883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.415657883
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.3741822224
Short name T923
Test name
Test status
Simulation time 22698316312 ps
CPU time 751.5 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:19:50 PM PST 23
Peak memory 371940 kb
Host smart-d1148e1b-4e4f-4f24-878c-912497ad88d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741822224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3741822224
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.852570800
Short name T629
Test name
Test status
Simulation time 352199287 ps
CPU time 14.37 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 202220 kb
Host smart-ab1e58ba-68e8-4cfe-a04f-a210593dd467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852570800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.852570800
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.3059233257
Short name T26
Test name
Test status
Simulation time 512486667060 ps
CPU time 2022.9 seconds
Started Dec 20 01:07:00 PM PST 23
Finished Dec 20 01:41:07 PM PST 23
Peak memory 376104 kb
Host smart-6724b668-839d-4502-9b8a-5cbbd2ab0ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059233257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.3059233257
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2147663675
Short name T358
Test name
Test status
Simulation time 2439024102 ps
CPU time 981.57 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:23:43 PM PST 23
Peak memory 426632 kb
Host smart-65b3e520-8d20-4103-bf44-06ac39cdc3fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2147663675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2147663675
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.525276102
Short name T982
Test name
Test status
Simulation time 10821355784 ps
CPU time 200.79 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:10:36 PM PST 23
Peak memory 202164 kb
Host smart-ade3778e-b4d0-4eb9-b268-abee448d8b99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525276102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_stress_pipeline.525276102
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3805678971
Short name T627
Test name
Test status
Simulation time 7097860065 ps
CPU time 162.73 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:10:04 PM PST 23
Peak memory 365800 kb
Host smart-f1d74fb1-7f55-4404-b958-0e44d5d0c6d6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805678971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3805678971
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2803623106
Short name T758
Test name
Test status
Simulation time 15532057390 ps
CPU time 679.99 seconds
Started Dec 20 01:07:07 PM PST 23
Finished Dec 20 01:18:50 PM PST 23
Peak memory 351504 kb
Host smart-de98ac44-b185-4438-8ec2-da927e0d1775
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803623106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.2803623106
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.2048092261
Short name T850
Test name
Test status
Simulation time 20957518 ps
CPU time 0.65 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:07:20 PM PST 23
Peak memory 201900 kb
Host smart-a0459e5f-0f55-44f5-8dc5-ee22a568e411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048092261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.2048092261
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.1761955539
Short name T135
Test name
Test status
Simulation time 60044525280 ps
CPU time 1292.02 seconds
Started Dec 20 01:07:07 PM PST 23
Finished Dec 20 01:29:02 PM PST 23
Peak memory 202092 kb
Host smart-8910163b-978b-4148-97dc-22db15c6a89f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761955539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.1761955539
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.856185251
Short name T366
Test name
Test status
Simulation time 29835170492 ps
CPU time 784.74 seconds
Started Dec 20 01:07:03 PM PST 23
Finished Dec 20 01:20:32 PM PST 23
Peak memory 371968 kb
Host smart-3d341604-666e-4864-9653-693f79f97808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856185251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executabl
e.856185251
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.2442351130
Short name T30
Test name
Test status
Simulation time 50627797595 ps
CPU time 144.26 seconds
Started Dec 20 01:06:57 PM PST 23
Finished Dec 20 01:09:45 PM PST 23
Peak memory 210388 kb
Host smart-0213a4a1-dd69-4f42-ae09-962098335430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442351130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.2442351130
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.1833201809
Short name T933
Test name
Test status
Simulation time 1472236029 ps
CPU time 61.98 seconds
Started Dec 20 01:07:07 PM PST 23
Finished Dec 20 01:08:32 PM PST 23
Peak memory 289076 kb
Host smart-bb45b37a-0458-4e1f-a05e-02e8118f69ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833201809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.1833201809
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2904409486
Short name T703
Test name
Test status
Simulation time 2453035379 ps
CPU time 77.96 seconds
Started Dec 20 01:07:08 PM PST 23
Finished Dec 20 01:08:48 PM PST 23
Peak memory 211228 kb
Host smart-f5c714f0-613b-4795-9315-3a2a2a2c4660
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904409486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.2904409486
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.3838217448
Short name T708
Test name
Test status
Simulation time 21999869727 ps
CPU time 303.74 seconds
Started Dec 20 01:07:00 PM PST 23
Finished Dec 20 01:12:27 PM PST 23
Peak memory 202296 kb
Host smart-08761611-0d4d-4a23-bdda-af828323382f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838217448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.3838217448
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.3009073378
Short name T417
Test name
Test status
Simulation time 21355296782 ps
CPU time 984.42 seconds
Started Dec 20 01:07:03 PM PST 23
Finished Dec 20 01:23:52 PM PST 23
Peak memory 380304 kb
Host smart-a2e4c2a2-2318-4bdd-800f-5e2ecee46686
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009073378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.3009073378
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.2795714531
Short name T881
Test name
Test status
Simulation time 398556589 ps
CPU time 17.91 seconds
Started Dec 20 01:07:04 PM PST 23
Finished Dec 20 01:07:46 PM PST 23
Peak memory 223100 kb
Host smart-eb89d21f-5cdc-45b2-9d21-2fae5295c8e2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795714531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.2795714531
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1482490980
Short name T909
Test name
Test status
Simulation time 15030413328 ps
CPU time 363.66 seconds
Started Dec 20 01:07:02 PM PST 23
Finished Dec 20 01:13:31 PM PST 23
Peak memory 202176 kb
Host smart-92076129-4ea1-4b9b-82bf-0e4a9aaf3d3d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482490980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.1482490980
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.3883557336
Short name T784
Test name
Test status
Simulation time 355435488 ps
CPU time 13.94 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:07:29 PM PST 23
Peak memory 202532 kb
Host smart-979e7cee-854a-4eb6-92b7-63820168fb35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883557336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3883557336
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3136124240
Short name T893
Test name
Test status
Simulation time 32733603641 ps
CPU time 869.82 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:21:47 PM PST 23
Peak memory 375072 kb
Host smart-160e699f-7435-479a-ac13-a0c74f715a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136124240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3136124240
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.2097942024
Short name T326
Test name
Test status
Simulation time 4864984559 ps
CPU time 31.53 seconds
Started Dec 20 01:06:57 PM PST 23
Finished Dec 20 01:07:52 PM PST 23
Peak memory 223552 kb
Host smart-8dbfd1d3-33aa-4f3b-9847-330c307fca33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097942024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2097942024
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.4242172814
Short name T547
Test name
Test status
Simulation time 139554708490 ps
CPU time 913.34 seconds
Started Dec 20 01:06:56 PM PST 23
Finished Dec 20 01:22:34 PM PST 23
Peak memory 349200 kb
Host smart-7b7185d8-bf91-4ff2-b94c-95474667730c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242172814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.4242172814
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1338508240
Short name T567
Test name
Test status
Simulation time 1437895757 ps
CPU time 4738.2 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 02:26:16 PM PST 23
Peak memory 698316 kb
Host smart-6a75eb5b-6d75-49c1-9e07-bb1a089278b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1338508240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1338508240
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4071541461
Short name T825
Test name
Test status
Simulation time 2784565708 ps
CPU time 194.19 seconds
Started Dec 20 01:06:57 PM PST 23
Finished Dec 20 01:10:35 PM PST 23
Peak memory 202252 kb
Host smart-a7acc1cb-8f05-4634-a047-cda484b7baa0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071541461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.4071541461
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4256104769
Short name T713
Test name
Test status
Simulation time 3042203708 ps
CPU time 58.05 seconds
Started Dec 20 01:07:08 PM PST 23
Finished Dec 20 01:08:28 PM PST 23
Peak memory 288304 kb
Host smart-2053570b-8e9d-4fcc-bcd6-305b57756ab7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256104769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.4256104769
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3027500309
Short name T925
Test name
Test status
Simulation time 37003689831 ps
CPU time 1178.56 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:26:55 PM PST 23
Peak memory 380036 kb
Host smart-b451dc5c-a415-427a-9a7c-2bbc724c697d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027500309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.3027500309
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.720585564
Short name T747
Test name
Test status
Simulation time 10665817 ps
CPU time 0.64 seconds
Started Dec 20 01:07:04 PM PST 23
Finished Dec 20 01:07:28 PM PST 23
Peak memory 201464 kb
Host smart-843ca945-1b3a-4930-9a79-e26a05e2115a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720585564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.720585564
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.4289760846
Short name T772
Test name
Test status
Simulation time 33147190708 ps
CPU time 2129.62 seconds
Started Dec 20 01:06:51 PM PST 23
Finished Dec 20 01:42:45 PM PST 23
Peak memory 202180 kb
Host smart-0a9d7b6f-7985-4f15-b754-857bc21d5588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289760846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.4289760846
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.1320104450
Short name T984
Test name
Test status
Simulation time 30157633082 ps
CPU time 1071.99 seconds
Started Dec 20 01:07:00 PM PST 23
Finished Dec 20 01:25:16 PM PST 23
Peak memory 379092 kb
Host smart-326829e4-4e39-431c-815b-a87152fa1af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320104450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.1320104450
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.3690102754
Short name T551
Test name
Test status
Simulation time 10567993547 ps
CPU time 165.47 seconds
Started Dec 20 01:06:54 PM PST 23
Finished Dec 20 01:10:03 PM PST 23
Peak memory 210496 kb
Host smart-12096308-93ff-4cb7-ae3f-35ae18d9adeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690102754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.3690102754
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.1015360963
Short name T277
Test name
Test status
Simulation time 2638437138 ps
CPU time 128.57 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:09:27 PM PST 23
Peak memory 365740 kb
Host smart-6e74afe0-9c0e-4388-b6c8-ec8fef08f7e2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015360963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.1015360963
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4201893870
Short name T488
Test name
Test status
Simulation time 5562936929 ps
CPU time 71.43 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:08:32 PM PST 23
Peak memory 218544 kb
Host smart-8039a02d-0067-4c07-b47a-ddebf867fc72
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201893870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.4201893870
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.1057463216
Short name T530
Test name
Test status
Simulation time 11608669412 ps
CPU time 128.2 seconds
Started Dec 20 01:06:56 PM PST 23
Finished Dec 20 01:09:29 PM PST 23
Peak memory 202276 kb
Host smart-6c3e4318-c30f-46ea-a1da-3f208725a8c0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057463216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.1057463216
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.3281608322
Short name T579
Test name
Test status
Simulation time 15602998885 ps
CPU time 771.38 seconds
Started Dec 20 01:06:50 PM PST 23
Finished Dec 20 01:20:06 PM PST 23
Peak memory 377096 kb
Host smart-9db99ab1-5c7e-402d-bc8f-de3a3eb36c02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281608322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.3281608322
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.940063731
Short name T692
Test name
Test status
Simulation time 4412731670 ps
CPU time 122.47 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:09:23 PM PST 23
Peak memory 367920 kb
Host smart-54f5e8d2-10f8-4c8d-bc7e-737585aa7d26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940063731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s
ram_ctrl_partial_access.940063731
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2743322263
Short name T130
Test name
Test status
Simulation time 41215521145 ps
CPU time 289.8 seconds
Started Dec 20 01:06:56 PM PST 23
Finished Dec 20 01:12:11 PM PST 23
Peak memory 202196 kb
Host smart-f0e3cd96-0d97-488a-b413-c600b7702fa4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743322263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.2743322263
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.3619385357
Short name T308
Test name
Test status
Simulation time 1409264653 ps
CPU time 5.9 seconds
Started Dec 20 01:06:57 PM PST 23
Finished Dec 20 01:07:27 PM PST 23
Peak memory 202472 kb
Host smart-4b1b2918-1744-41e7-a1d2-53afc49fe56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619385357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3619385357
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.3627720183
Short name T832
Test name
Test status
Simulation time 16856560691 ps
CPU time 1112.92 seconds
Started Dec 20 01:06:55 PM PST 23
Finished Dec 20 01:25:51 PM PST 23
Peak memory 375112 kb
Host smart-a47d0fa7-334a-487d-8472-6a5cc8a08007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627720183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3627720183
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.4082836316
Short name T857
Test name
Test status
Simulation time 1131607979 ps
CPU time 22.09 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:07:43 PM PST 23
Peak memory 202164 kb
Host smart-0fc44e61-176e-48c2-a608-be966f63e728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082836316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.4082836316
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.825409410
Short name T341
Test name
Test status
Simulation time 393040831 ps
CPU time 1789.58 seconds
Started Dec 20 01:07:04 PM PST 23
Finished Dec 20 01:37:17 PM PST 23
Peak memory 473292 kb
Host smart-863ade3c-9990-475e-b3b5-887a9149bcdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=825409410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.825409410
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3626382184
Short name T858
Test name
Test status
Simulation time 17696198914 ps
CPU time 315.53 seconds
Started Dec 20 01:06:56 PM PST 23
Finished Dec 20 01:12:36 PM PST 23
Peak memory 202160 kb
Host smart-a87b2202-ce15-4bf9-9f57-261b2561b25b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626382184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3626382184
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3200748659
Short name T935
Test name
Test status
Simulation time 1557026754 ps
CPU time 80.4 seconds
Started Dec 20 01:07:00 PM PST 23
Finished Dec 20 01:08:44 PM PST 23
Peak memory 312812 kb
Host smart-a930d419-dca8-4107-b98d-14d7a6fb8a91
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200748659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3200748659
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.453339136
Short name T895
Test name
Test status
Simulation time 27868035319 ps
CPU time 1230.65 seconds
Started Dec 20 01:07:20 PM PST 23
Finished Dec 20 01:28:03 PM PST 23
Peak memory 381260 kb
Host smart-4420e7dd-c566-4a62-be5c-355ccb1f3240
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453339136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.sram_ctrl_access_during_key_req.453339136
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.562312385
Short name T236
Test name
Test status
Simulation time 18261276 ps
CPU time 0.64 seconds
Started Dec 20 01:07:19 PM PST 23
Finished Dec 20 01:07:33 PM PST 23
Peak memory 201848 kb
Host smart-cca8dc11-df75-49e4-8394-2819ab783e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562312385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.562312385
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.3645251431
Short name T958
Test name
Test status
Simulation time 116253822870 ps
CPU time 2400.91 seconds
Started Dec 20 01:07:03 PM PST 23
Finished Dec 20 01:47:28 PM PST 23
Peak memory 202272 kb
Host smart-1d65f0a4-044a-4afa-aea9-919736fdd899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645251431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.3645251431
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.1871677574
Short name T51
Test name
Test status
Simulation time 39493917954 ps
CPU time 308.93 seconds
Started Dec 20 01:07:20 PM PST 23
Finished Dec 20 01:12:42 PM PST 23
Peak memory 337152 kb
Host smart-5ec28413-be03-429b-b782-89b8c399416b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871677574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.1871677574
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.4156688270
Short name T399
Test name
Test status
Simulation time 18953545472 ps
CPU time 115.52 seconds
Started Dec 20 01:07:20 PM PST 23
Finished Dec 20 01:09:28 PM PST 23
Peak memory 210468 kb
Host smart-5a485909-6d45-45b7-a64c-99a52ac39d3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156688270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.4156688270
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.984480032
Short name T924
Test name
Test status
Simulation time 743149491 ps
CPU time 43.35 seconds
Started Dec 20 01:07:17 PM PST 23
Finished Dec 20 01:08:15 PM PST 23
Peak memory 273744 kb
Host smart-424c8006-45c6-4998-9778-44062db0b2f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984480032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.sram_ctrl_max_throughput.984480032
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2669865021
Short name T83
Test name
Test status
Simulation time 4570310672 ps
CPU time 145.83 seconds
Started Dec 20 01:07:21 PM PST 23
Finished Dec 20 01:09:59 PM PST 23
Peak memory 214696 kb
Host smart-0a4dd9e6-fc00-4a8d-aeef-9d652fafc573
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669865021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2669865021
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.1860733288
Short name T464
Test name
Test status
Simulation time 17250867472 ps
CPU time 154.3 seconds
Started Dec 20 01:07:17 PM PST 23
Finished Dec 20 01:10:06 PM PST 23
Peak memory 202268 kb
Host smart-b36e625f-debd-4beb-9859-5496f18b96e2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860733288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.1860733288
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.2162648813
Short name T537
Test name
Test status
Simulation time 6995587911 ps
CPU time 442.07 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:14:43 PM PST 23
Peak memory 375128 kb
Host smart-d7c269c3-716d-44d2-859e-b6fdb8ba4d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162648813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.2162648813
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.2799957558
Short name T657
Test name
Test status
Simulation time 1441654930 ps
CPU time 13.81 seconds
Started Dec 20 01:06:57 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 210300 kb
Host smart-6484eac7-3331-408d-97f5-eb826fa6a000
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799957558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.2799957558
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3170303070
Short name T539
Test name
Test status
Simulation time 63701151274 ps
CPU time 413.92 seconds
Started Dec 20 01:07:04 PM PST 23
Finished Dec 20 01:14:22 PM PST 23
Peak memory 202184 kb
Host smart-d13cad8b-cdd2-448e-9630-0721100c9a31
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170303070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.3170303070
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.1781427322
Short name T35
Test name
Test status
Simulation time 1469784790 ps
CPU time 6.6 seconds
Started Dec 20 01:07:19 PM PST 23
Finished Dec 20 01:07:39 PM PST 23
Peak memory 202420 kb
Host smart-10084178-af12-4414-9e6c-1c8124c04f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781427322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1781427322
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.1571295388
Short name T975
Test name
Test status
Simulation time 28740137875 ps
CPU time 812.03 seconds
Started Dec 20 01:07:20 PM PST 23
Finished Dec 20 01:21:05 PM PST 23
Peak memory 378036 kb
Host smart-f273d015-49da-4552-84de-7f804a140269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571295388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1571295388
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.3846115429
Short name T528
Test name
Test status
Simulation time 2791177409 ps
CPU time 28.4 seconds
Started Dec 20 01:06:58 PM PST 23
Finished Dec 20 01:07:49 PM PST 23
Peak memory 202160 kb
Host smart-3874aa66-0f76-43fc-afbd-b1b851395cf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846115429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3846115429
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.2439401743
Short name T316
Test name
Test status
Simulation time 156699395319 ps
CPU time 3738.98 seconds
Started Dec 20 01:07:19 PM PST 23
Finished Dec 20 02:09:52 PM PST 23
Peak memory 368596 kb
Host smart-78e8f813-b639-491c-ac5a-e4f4eb70a34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439401743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.2439401743
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2244304365
Short name T653
Test name
Test status
Simulation time 274820103 ps
CPU time 2065.74 seconds
Started Dec 20 01:07:19 PM PST 23
Finished Dec 20 01:41:58 PM PST 23
Peak memory 571812 kb
Host smart-ac6f424c-4d2c-424a-97c6-ece78a066963
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2244304365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.2244304365
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3233490910
Short name T337
Test name
Test status
Simulation time 34073122614 ps
CPU time 289.05 seconds
Started Dec 20 01:07:03 PM PST 23
Finished Dec 20 01:12:16 PM PST 23
Peak memory 202256 kb
Host smart-bf428bc4-195f-413c-93e9-e4e125117398
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233490910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.3233490910
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3228605171
Short name T267
Test name
Test status
Simulation time 3162184970 ps
CPU time 115.25 seconds
Started Dec 20 01:07:22 PM PST 23
Finished Dec 20 01:09:29 PM PST 23
Peak memory 337300 kb
Host smart-c13f5c8a-2100-4075-b173-97e929377cd1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228605171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3228605171
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1619768988
Short name T992
Test name
Test status
Simulation time 25082061947 ps
CPU time 560.07 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:14:57 PM PST 23
Peak memory 362692 kb
Host smart-d713e0c9-19dd-46dc-96c9-d427316d167a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619768988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1619768988
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.3574519921
Short name T716
Test name
Test status
Simulation time 15039979 ps
CPU time 0.65 seconds
Started Dec 20 01:05:22 PM PST 23
Finished Dec 20 01:05:42 PM PST 23
Peak memory 201896 kb
Host smart-8feca4b8-1892-447a-b334-0ca3dc85416f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574519921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.3574519921
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.2406857257
Short name T142
Test name
Test status
Simulation time 104612790365 ps
CPU time 1695.33 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:33:52 PM PST 23
Peak memory 202304 kb
Host smart-7635bf02-7a57-4f2e-a718-021f9994f404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406857257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
2406857257
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.2036601290
Short name T929
Test name
Test status
Simulation time 40391041560 ps
CPU time 430.19 seconds
Started Dec 20 01:05:02 PM PST 23
Finished Dec 20 01:12:43 PM PST 23
Peak memory 373016 kb
Host smart-4024c0c1-8a19-4d56-a199-609e497fdd4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036601290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.2036601290
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.1671287035
Short name T677
Test name
Test status
Simulation time 17991071246 ps
CPU time 261.51 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:10:01 PM PST 23
Peak memory 202204 kb
Host smart-2ba2aa43-3fe8-4048-a3ab-86c5c15d03d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671287035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.1671287035
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.577559479
Short name T455
Test name
Test status
Simulation time 3155832084 ps
CPU time 128.68 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:07:32 PM PST 23
Peak memory 356776 kb
Host smart-f80fe2a1-6657-406c-9f7c-6227e205f5fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577559479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.sram_ctrl_max_throughput.577559479
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2698399892
Short name T642
Test name
Test status
Simulation time 6451291104 ps
CPU time 136.64 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:07:39 PM PST 23
Peak memory 211272 kb
Host smart-4fb3519c-e4d6-4957-a6b6-1a9ee0fab325
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698399892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2698399892
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.1269842255
Short name T299
Test name
Test status
Simulation time 10341010978 ps
CPU time 151.57 seconds
Started Dec 20 01:05:05 PM PST 23
Finished Dec 20 01:08:01 PM PST 23
Peak memory 202296 kb
Host smart-bca2a497-93c6-4624-96b3-e50c79801f22
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269842255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.1269842255
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.3349623224
Short name T950
Test name
Test status
Simulation time 774810906 ps
CPU time 55.34 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:06:28 PM PST 23
Peak memory 285952 kb
Host smart-ea1ab512-6699-4f55-a536-47e6cd117b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349623224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.3349623224
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.2720631756
Short name T591
Test name
Test status
Simulation time 1071453161 ps
CPU time 20.12 seconds
Started Dec 20 01:05:00 PM PST 23
Finished Dec 20 01:05:46 PM PST 23
Peak memory 247100 kb
Host smart-8b505992-0924-4798-8e1c-f314b4a0a4bb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720631756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.2720631756
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.23134584
Short name T926
Test name
Test status
Simulation time 5882389207 ps
CPU time 371.4 seconds
Started Dec 20 01:05:03 PM PST 23
Finished Dec 20 01:11:40 PM PST 23
Peak memory 202192 kb
Host smart-6e911ee8-0dad-4aaf-9ab7-3c795851c80b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23134584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_partial_access_b2b.23134584
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.374743956
Short name T272
Test name
Test status
Simulation time 3361676188 ps
CPU time 6.89 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:05:44 PM PST 23
Peak memory 202568 kb
Host smart-445096f6-95ee-4b02-9c1f-3c4f4ea4c538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374743956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.374743956
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.4104884923
Short name T729
Test name
Test status
Simulation time 6424629380 ps
CPU time 696.48 seconds
Started Dec 20 01:05:02 PM PST 23
Finished Dec 20 01:17:05 PM PST 23
Peak memory 343872 kb
Host smart-ca1ed1ca-f40c-41c4-8e31-03aeec303a86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104884923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.4104884923
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.2108380837
Short name T404
Test name
Test status
Simulation time 2976346417 ps
CPU time 11.96 seconds
Started Dec 20 01:05:16 PM PST 23
Finished Dec 20 01:05:49 PM PST 23
Peak memory 203636 kb
Host smart-ee5cb150-0914-48dd-9d72-0de330e487f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108380837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2108380837
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.67156539
Short name T757
Test name
Test status
Simulation time 20123622843 ps
CPU time 1869.89 seconds
Started Dec 20 01:05:03 PM PST 23
Finished Dec 20 01:36:39 PM PST 23
Peak memory 381280 kb
Host smart-57152167-1364-4873-ac54-03c514369cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67156539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_stress_all.67156539
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.733544886
Short name T252
Test name
Test status
Simulation time 303286981 ps
CPU time 1635.59 seconds
Started Dec 20 01:04:54 PM PST 23
Finished Dec 20 01:32:35 PM PST 23
Peak memory 611972 kb
Host smart-05c5b99a-5ef7-4cf6-8161-e97ffac08836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=733544886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.733544886
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.844016809
Short name T611
Test name
Test status
Simulation time 52094736508 ps
CPU time 393.91 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:12:07 PM PST 23
Peak memory 202132 kb
Host smart-85a132bc-589e-484d-a625-62ef4c650231
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844016809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
sram_ctrl_stress_pipeline.844016809
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2254788155
Short name T675
Test name
Test status
Simulation time 754314821 ps
CPU time 50.91 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:06:34 PM PST 23
Peak memory 274344 kb
Host smart-9c4cae81-2d86-47b5-adb4-acb4d5b2d27f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254788155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2254788155
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3572147017
Short name T291
Test name
Test status
Simulation time 23774732978 ps
CPU time 670.33 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:16:47 PM PST 23
Peak memory 364668 kb
Host smart-41e53852-db1c-4f93-bf2e-d01ef45a7269
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572147017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.3572147017
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.226158713
Short name T983
Test name
Test status
Simulation time 175764023 ps
CPU time 0.67 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:05:46 PM PST 23
Peak memory 201504 kb
Host smart-1f1c03c5-a9c0-4c66-b910-92778a9c7650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226158713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.226158713
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.1244642104
Short name T534
Test name
Test status
Simulation time 112715684145 ps
CPU time 2445.68 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:46:11 PM PST 23
Peak memory 202240 kb
Host smart-4dd6a5aa-c29a-4334-95be-432e9f984c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244642104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
1244642104
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.4207157787
Short name T463
Test name
Test status
Simulation time 13594356055 ps
CPU time 603.68 seconds
Started Dec 20 01:05:06 PM PST 23
Finished Dec 20 01:15:34 PM PST 23
Peak memory 372896 kb
Host smart-d464204f-db1e-4470-b260-60494bd9a3c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207157787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.4207157787
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.921665849
Short name T117
Test name
Test status
Simulation time 5322935094 ps
CPU time 27.31 seconds
Started Dec 20 01:05:00 PM PST 23
Finished Dec 20 01:05:54 PM PST 23
Peak memory 213220 kb
Host smart-475f33fd-ef04-43ff-8b5e-7d7a2cce1c9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921665849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca
lation.921665849
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.195393277
Short name T643
Test name
Test status
Simulation time 738119279 ps
CPU time 77.15 seconds
Started Dec 20 01:05:04 PM PST 23
Finished Dec 20 01:06:47 PM PST 23
Peak memory 313684 kb
Host smart-462b325c-8e29-4d78-a0b1-734a57d5c00a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195393277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.sram_ctrl_max_throughput.195393277
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2637245058
Short name T817
Test name
Test status
Simulation time 5118352240 ps
CPU time 78.22 seconds
Started Dec 20 01:05:02 PM PST 23
Finished Dec 20 01:06:46 PM PST 23
Peak memory 211108 kb
Host smart-55bf899d-bc35-4917-9cbc-131d8e684a01
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637245058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.2637245058
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.2413725433
Short name T103
Test name
Test status
Simulation time 10764467074 ps
CPU time 151.73 seconds
Started Dec 20 01:05:03 PM PST 23
Finished Dec 20 01:08:01 PM PST 23
Peak memory 202228 kb
Host smart-ae08d47c-1581-4d27-99ca-96fe8672b0a4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413725433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.2413725433
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.4126986038
Short name T761
Test name
Test status
Simulation time 118714221208 ps
CPU time 1389.65 seconds
Started Dec 20 01:05:04 PM PST 23
Finished Dec 20 01:28:39 PM PST 23
Peak memory 378152 kb
Host smart-49ce7574-ed49-4519-a30a-a311ac421be3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126986038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.4126986038
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.1234926190
Short name T655
Test name
Test status
Simulation time 353007179 ps
CPU time 7.15 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:05:32 PM PST 23
Peak memory 202172 kb
Host smart-e77b055b-e179-4a2a-abbe-e672412c873f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234926190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.1234926190
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2417274145
Short name T292
Test name
Test status
Simulation time 41175447717 ps
CPU time 509.86 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:14:12 PM PST 23
Peak memory 202256 kb
Host smart-22922b7f-e39e-4ebf-98f9-d865e183dcc5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417274145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.2417274145
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.1976685290
Short name T978
Test name
Test status
Simulation time 379973411 ps
CPU time 6.5 seconds
Started Dec 20 01:05:04 PM PST 23
Finished Dec 20 01:05:40 PM PST 23
Peak memory 202452 kb
Host smart-60e0e0f9-ff83-4b01-bde0-f189e3ba1264
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976685290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1976685290
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.371036110
Short name T52
Test name
Test status
Simulation time 19394059539 ps
CPU time 1316.11 seconds
Started Dec 20 01:05:12 PM PST 23
Finished Dec 20 01:27:32 PM PST 23
Peak memory 377980 kb
Host smart-d7cdc1fc-496e-459f-8c46-074908332c6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371036110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.371036110
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.581025704
Short name T951
Test name
Test status
Simulation time 819162899 ps
CPU time 37.66 seconds
Started Dec 20 01:04:54 PM PST 23
Finished Dec 20 01:05:56 PM PST 23
Peak memory 278896 kb
Host smart-df3b1c32-aa40-4435-9ffa-e09889cf718a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581025704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.581025704
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.632131559
Short name T674
Test name
Test status
Simulation time 1229658728 ps
CPU time 3255.42 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:59:54 PM PST 23
Peak memory 654784 kb
Host smart-d6d82903-1904-4b34-94f5-85a534cf613f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=632131559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.632131559
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.596207888
Short name T99
Test name
Test status
Simulation time 17984725610 ps
CPU time 262.25 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:10:02 PM PST 23
Peak memory 202332 kb
Host smart-b60a9e7b-33bc-4fef-8d16-bded4ed269bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596207888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_stress_pipeline.596207888
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4147754243
Short name T145
Test name
Test status
Simulation time 9766400226 ps
CPU time 33.69 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:06:06 PM PST 23
Peak memory 226464 kb
Host smart-fa34573d-39d3-4d9e-b2c6-2413e07031ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147754243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.4147754243
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.206768031
Short name T309
Test name
Test status
Simulation time 52150388531 ps
CPU time 977.43 seconds
Started Dec 20 01:05:10 PM PST 23
Finished Dec 20 01:21:52 PM PST 23
Peak memory 378956 kb
Host smart-a0fdf7de-d535-4de9-9402-0c1878b006bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206768031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_access_during_key_req.206768031
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.2717188196
Short name T20
Test name
Test status
Simulation time 47405693 ps
CPU time 0.63 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:05:39 PM PST 23
Peak memory 201956 kb
Host smart-bdb66475-ebb3-4888-8c01-f093dc5ac084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717188196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.2717188196
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.1692266082
Short name T737
Test name
Test status
Simulation time 632079107733 ps
CPU time 2380.37 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:45:17 PM PST 23
Peak memory 202216 kb
Host smart-41c9cedc-4f89-4925-93fd-04db2532ec8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692266082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
1692266082
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.54464971
Short name T395
Test name
Test status
Simulation time 72978553697 ps
CPU time 396.37 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:12:13 PM PST 23
Peak memory 210192 kb
Host smart-75718606-6b83-4b08-8657-07ddea619994
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54464971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escal
ation.54464971
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.1910253446
Short name T364
Test name
Test status
Simulation time 4613245867 ps
CPU time 94.98 seconds
Started Dec 20 01:05:15 PM PST 23
Finished Dec 20 01:07:12 PM PST 23
Peak memory 325016 kb
Host smart-071e35bc-ecea-4970-8836-5594d0a4b2af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910253446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.1910253446
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2277070553
Short name T495
Test name
Test status
Simulation time 5151316956 ps
CPU time 147.59 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:08:13 PM PST 23
Peak memory 214600 kb
Host smart-e5658cc0-e684-4396-85df-c1aeaef1df6c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277070553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.2277070553
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.4187226043
Short name T664
Test name
Test status
Simulation time 14510030538 ps
CPU time 284.19 seconds
Started Dec 20 01:05:12 PM PST 23
Finished Dec 20 01:10:20 PM PST 23
Peak memory 202176 kb
Host smart-65b0edd0-d6a4-4eb9-9531-d4332d37a9bb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187226043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.4187226043
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.1763608705
Short name T261
Test name
Test status
Simulation time 5049416658 ps
CPU time 409.27 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:12:34 PM PST 23
Peak memory 330076 kb
Host smart-c7be8351-e4e6-4a6c-8853-8186a2405dc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763608705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.1763608705
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1549080351
Short name T695
Test name
Test status
Simulation time 1767255212 ps
CPU time 36.64 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 01:05:59 PM PST 23
Peak memory 202204 kb
Host smart-91278dfe-8aab-439f-81f5-453577956f6f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549080351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1549080351
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2565675840
Short name T442
Test name
Test status
Simulation time 54808153588 ps
CPU time 367.84 seconds
Started Dec 20 01:05:26 PM PST 23
Finished Dec 20 01:11:52 PM PST 23
Peak memory 202152 kb
Host smart-8815cce8-4293-4dc7-b33d-0144d1059823
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565675840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.2565675840
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.462692565
Short name T583
Test name
Test status
Simulation time 346665378 ps
CPU time 13.1 seconds
Started Dec 20 01:05:05 PM PST 23
Finished Dec 20 01:05:43 PM PST 23
Peak memory 202480 kb
Host smart-7a62eee5-3c7d-46d9-b99d-e9f228f663bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462692565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.462692565
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.2970380881
Short name T769
Test name
Test status
Simulation time 16250652909 ps
CPU time 1178.38 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:25:23 PM PST 23
Peak memory 378024 kb
Host smart-47227b3d-6351-4d3c-b854-303d4c830284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970380881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2970380881
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.3449501208
Short name T919
Test name
Test status
Simulation time 6093029400 ps
CPU time 24.12 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:06:08 PM PST 23
Peak memory 271336 kb
Host smart-da9ee257-654a-4598-99be-c59336be14d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449501208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3449501208
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.3045617276
Short name T377
Test name
Test status
Simulation time 55935859101 ps
CPU time 2486.09 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:47:08 PM PST 23
Peak memory 381220 kb
Host smart-ea98cd10-79b0-4d4f-8d66-6d056bc38a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045617276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.3045617276
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2255990145
Short name T315
Test name
Test status
Simulation time 1783862401 ps
CPU time 1331.67 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:28:00 PM PST 23
Peak memory 417276 kb
Host smart-bc70aa7b-91f0-43a6-a797-de962e2e130d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2255990145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2255990145
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2075229221
Short name T496
Test name
Test status
Simulation time 3759245516 ps
CPU time 284.5 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:10:27 PM PST 23
Peak memory 202196 kb
Host smart-8512c7f9-e0e0-4d73-a533-0212361f8dab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075229221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.2075229221
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3236653222
Short name T844
Test name
Test status
Simulation time 724857753 ps
CPU time 52.45 seconds
Started Dec 20 01:05:12 PM PST 23
Finished Dec 20 01:06:28 PM PST 23
Peak memory 275168 kb
Host smart-4cb6bdb5-3e0e-4c57-8562-d9b682b8068f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236653222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3236653222
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.162672505
Short name T841
Test name
Test status
Simulation time 3783968059 ps
CPU time 141.06 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:08:06 PM PST 23
Peak memory 249792 kb
Host smart-ae4238fc-0b5c-49c1-8600-7456ca3477a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162672505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_access_during_key_req.162672505
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.3450252967
Short name T541
Test name
Test status
Simulation time 15161177 ps
CPU time 0.66 seconds
Started Dec 20 01:05:17 PM PST 23
Finished Dec 20 01:05:39 PM PST 23
Peak memory 201996 kb
Host smart-96793bc6-4566-4158-92a2-480126ac9e0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450252967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.3450252967
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.271726566
Short name T598
Test name
Test status
Simulation time 96740600811 ps
CPU time 2157.19 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:41:30 PM PST 23
Peak memory 202360 kb
Host smart-5d2c1b45-0b6f-49dd-8caa-b92a4ed00366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271726566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.271726566
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.3952339177
Short name T989
Test name
Test status
Simulation time 58468317397 ps
CPU time 112.36 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:07:35 PM PST 23
Peak memory 210204 kb
Host smart-5a5c66ac-a392-4758-b489-c766868939ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952339177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.3952339177
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2493330908
Short name T879
Test name
Test status
Simulation time 2707903923 ps
CPU time 44.3 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:06:29 PM PST 23
Peak memory 267644 kb
Host smart-d909acce-66c9-420b-875a-a9cfe22d2772
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493330908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2493330908
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1180010393
Short name T479
Test name
Test status
Simulation time 2479212094 ps
CPU time 77.78 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:07:03 PM PST 23
Peak memory 211652 kb
Host smart-e40dfe8a-f125-489c-bc8d-c91869662136
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180010393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1180010393
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.3342378363
Short name T759
Test name
Test status
Simulation time 14504127420 ps
CPU time 280.71 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:10:17 PM PST 23
Peak memory 202176 kb
Host smart-9ecb69b3-d033-45e2-8a26-98623a512dc0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342378363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.3342378363
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.1345738986
Short name T659
Test name
Test status
Simulation time 119702773022 ps
CPU time 843.79 seconds
Started Dec 20 01:05:32 PM PST 23
Finished Dec 20 01:19:52 PM PST 23
Peak memory 378048 kb
Host smart-18269079-8343-4f6e-a078-b4abf2c835e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345738986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.1345738986
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.4057797949
Short name T845
Test name
Test status
Simulation time 861639390 ps
CPU time 189.93 seconds
Started Dec 20 01:05:29 PM PST 23
Finished Dec 20 01:08:57 PM PST 23
Peak memory 375064 kb
Host smart-90b33526-cd8f-4c25-a65c-9f6be0586587
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057797949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.4057797949
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.51460135
Short name T287
Test name
Test status
Simulation time 25272978087 ps
CPU time 573.6 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:15:18 PM PST 23
Peak memory 202212 kb
Host smart-b0adadc2-b58d-49e3-ac56-b797152ac1a8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51460135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_partial_access_b2b.51460135
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.1626264516
Short name T618
Test name
Test status
Simulation time 1537123335 ps
CPU time 13.41 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:05:58 PM PST 23
Peak memory 202512 kb
Host smart-e41a8188-b92c-471c-9423-5dff6d41751f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626264516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1626264516
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.1492937148
Short name T458
Test name
Test status
Simulation time 5054812876 ps
CPU time 886.35 seconds
Started Dec 20 01:05:20 PM PST 23
Finished Dec 20 01:20:26 PM PST 23
Peak memory 378116 kb
Host smart-bd84e21d-01b6-4c8a-83d2-3725e2f6e07b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492937148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1492937148
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.2281611763
Short name T269
Test name
Test status
Simulation time 1494884237 ps
CPU time 14.33 seconds
Started Dec 20 01:05:13 PM PST 23
Finished Dec 20 01:05:50 PM PST 23
Peak memory 202000 kb
Host smart-27cff2b1-2f79-498e-aa62-a12414616780
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281611763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2281611763
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.244559295
Short name T440
Test name
Test status
Simulation time 1088729572 ps
CPU time 2686.46 seconds
Started Dec 20 01:05:27 PM PST 23
Finished Dec 20 01:50:32 PM PST 23
Peak memory 775696 kb
Host smart-3fde935e-994e-429f-939e-c313ce62d246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=244559295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.244559295
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2269499906
Short name T957
Test name
Test status
Simulation time 4862951887 ps
CPU time 357.87 seconds
Started Dec 20 01:05:23 PM PST 23
Finished Dec 20 01:11:41 PM PST 23
Peak memory 202252 kb
Host smart-600b8562-29c7-4b67-8ff1-237abee5e8b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269499906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2269499906
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.336883772
Short name T619
Test name
Test status
Simulation time 3126151326 ps
CPU time 175.36 seconds
Started Dec 20 01:05:19 PM PST 23
Finished Dec 20 01:08:34 PM PST 23
Peak memory 365892 kb
Host smart-223afe7d-42bd-4532-934e-f9c519380d67
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336883772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_throughput_w_partial_write.336883772
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3223584146
Short name T540
Test name
Test status
Simulation time 35164343223 ps
CPU time 1286.27 seconds
Started Dec 20 01:05:06 PM PST 23
Finished Dec 20 01:26:57 PM PST 23
Peak memory 376956 kb
Host smart-71750041-5211-4362-955f-6c56564572f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223584146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.3223584146
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1719239934
Short name T573
Test name
Test status
Simulation time 22406726 ps
CPU time 0.62 seconds
Started Dec 20 01:05:08 PM PST 23
Finished Dec 20 01:05:34 PM PST 23
Peak memory 201764 kb
Host smart-ae3ab09c-2d50-49b7-a30d-0b46a9379475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719239934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1719239934
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.3158462543
Short name T450
Test name
Test status
Simulation time 168291279915 ps
CPU time 1716.84 seconds
Started Dec 20 01:05:25 PM PST 23
Finished Dec 20 01:34:22 PM PST 23
Peak memory 202204 kb
Host smart-b2ba4d69-a6a4-4953-a2e5-acaed9330697
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158462543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
3158462543
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.754912787
Short name T683
Test name
Test status
Simulation time 36875010167 ps
CPU time 195.07 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:08:52 PM PST 23
Peak memory 210412 kb
Host smart-2ea8d21f-25be-4f8a-8838-66d16f1f1568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754912787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca
lation.754912787
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.1090486924
Short name T717
Test name
Test status
Simulation time 3611308686 ps
CPU time 121.04 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:07:26 PM PST 23
Peak memory 359216 kb
Host smart-dce3a965-8ada-4645-bfb3-2d7a4bb382d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090486924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.1090486924
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2638651841
Short name T566
Test name
Test status
Simulation time 11863465295 ps
CPU time 83.46 seconds
Started Dec 20 01:05:14 PM PST 23
Finished Dec 20 01:07:00 PM PST 23
Peak memory 218504 kb
Host smart-8a2e2301-9259-485f-a7f9-28add2606e62
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638651841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.2638651841
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.2596827516
Short name T728
Test name
Test status
Simulation time 3730707876 ps
CPU time 122.23 seconds
Started Dec 20 01:04:58 PM PST 23
Finished Dec 20 01:07:27 PM PST 23
Peak memory 202188 kb
Host smart-d9f80e65-e0c4-4a33-be24-a0891245d74d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596827516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.2596827516
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.1090262183
Short name T748
Test name
Test status
Simulation time 17922149147 ps
CPU time 637.67 seconds
Started Dec 20 01:05:03 PM PST 23
Finished Dec 20 01:16:07 PM PST 23
Peak memory 380232 kb
Host smart-5126eac0-9a05-4281-adfa-f2d578c2ea63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090262183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.1090262183
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.2312799516
Short name T509
Test name
Test status
Simulation time 5836386430 ps
CPU time 30.81 seconds
Started Dec 20 01:05:00 PM PST 23
Finished Dec 20 01:05:57 PM PST 23
Peak memory 202216 kb
Host smart-9b430bca-9432-4d5a-856d-f6a5ec5f44c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312799516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.2312799516
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3676697789
Short name T682
Test name
Test status
Simulation time 200259321404 ps
CPU time 318.46 seconds
Started Dec 20 01:05:24 PM PST 23
Finished Dec 20 01:11:01 PM PST 23
Peak memory 202308 kb
Host smart-d186907c-f2d4-4cc6-917b-f26cbfe73db6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676697789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.3676697789
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.2310759726
Short name T712
Test name
Test status
Simulation time 353925912 ps
CPU time 13.39 seconds
Started Dec 20 01:05:16 PM PST 23
Finished Dec 20 01:05:51 PM PST 23
Peak memory 202292 kb
Host smart-96029b9c-53d2-4418-9f04-6c7894ef04ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310759726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2310759726
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.898526337
Short name T294
Test name
Test status
Simulation time 3852213260 ps
CPU time 627.63 seconds
Started Dec 20 01:05:00 PM PST 23
Finished Dec 20 01:15:55 PM PST 23
Peak memory 371976 kb
Host smart-fad24c18-02b0-4bc9-afbd-f78cafe13709
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898526337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.898526337
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1090995168
Short name T543
Test name
Test status
Simulation time 1835952275 ps
CPU time 20.16 seconds
Started Dec 20 01:05:36 PM PST 23
Finished Dec 20 01:06:11 PM PST 23
Peak memory 201912 kb
Host smart-54fdc8aa-99e2-4fc4-b0ff-4c21259d0a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090995168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1090995168
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.576208574
Short name T608
Test name
Test status
Simulation time 569834437 ps
CPU time 3805.3 seconds
Started Dec 20 01:04:56 PM PST 23
Finished Dec 20 02:08:48 PM PST 23
Peak memory 707252 kb
Host smart-764b7ec5-ea6c-4d42-a65a-2171e3327a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=576208574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.576208574
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2239248798
Short name T577
Test name
Test status
Simulation time 5114078813 ps
CPU time 279.85 seconds
Started Dec 20 01:04:59 PM PST 23
Finished Dec 20 01:10:05 PM PST 23
Peak memory 202264 kb
Host smart-f64d2b99-db98-4e1c-868a-1761981d9437
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239248798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.2239248798
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3014174150
Short name T428
Test name
Test status
Simulation time 3258548431 ps
CPU time 31.01 seconds
Started Dec 20 01:05:10 PM PST 23
Finished Dec 20 01:06:05 PM PST 23
Peak memory 225332 kb
Host smart-607ca3c6-f61d-4e5d-89b8-b4e2843e0697
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014174150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3014174150
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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