Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14947369

1

T1

13520

T2

14790

T3

5060

full_word

132133964

1

T1

134975

T2

147580

T3

10408

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	147081023	1			T1	148495		T2	162370		T3	15468
auto[TlIntgErrCmd]	106	1			T50	2		T51	11		T52	2
auto[TlIntgErrData]	90	1			T50	4		T51	5		T52	4
auto[TlIntgErrBoth]	114	1			T50	4		T51	4		T52	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71117256

1

T1

74486

T2

81116

T3

2950

auto[1]

75964077

1

T1

74009

T2

81254

T3

12518

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7365965	1			T1	6887		T2	7416		T3	1055
auto[TlIntgErrNone]	partial	auto[1]	7581127	1			T1	6633		T2	7374		T3	4005
auto[TlIntgErrNone]	full_word	auto[0]	63751149	1			T1	67599		T2	73700		T3	1895
auto[TlIntgErrNone]	full_word	auto[1]	68382782	1			T1	67376		T2	73880		T3	8513
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T50	1		T51	6		T52	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T50	1		T51	2		T52	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T51	3		T122	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T117	1		T124	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T50	3		T51	3		T57	3
auto[TlIntgErrData]	partial	auto[1]	36	1			T51	2		T52	3		T63	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T50	1		T63	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T52	1		T117	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T50	1		T51	1		T52	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T50	1		T51	1		T52	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T126	1		T127	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T50	2		T51	2		T57	1