Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	646333	1			T15	519		T16	15178		T17	4328
auto[1]	10787966	1			T1	2434		T2	47035		T9	14978
auto[2]	498905	1			T15	370		T16	10987		T17	3407
auto[3]	10634034	1			T1	2412		T2	46851		T9	15101

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13557360	1			T1	3446		T2	78301		T9	144
auto[1]	2111978	1			T1	625		T2	7534		T9	1412
auto[2]	2143585	1			T1	667		T2	7366		T9	2635
auto[3]	4754315	1			T1	108		T2	685		T9	25888

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9120963

1

T1

4846

T2

93882

T9

30076

auto[1]

13446275

1

T2

4

T9

3

T10

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	257591	1			T15	431		T17	1		T137	22
auto[0]	auto[0]	auto[1]	26938	1			T15	51		T17	44		T138	2
auto[0]	auto[0]	auto[2]	26762	1			T15	33		T17	52		T138	2
auto[0]	auto[0]	auto[3]	74366	1			T15	4		T17	4228		T138	9
auto[0]	auto[1]	auto[0]	2965646	1			T1	1723		T2	39199		T9	9
auto[0]	auto[1]	auto[1]	315411	1			T1	463		T2	3626		T9	98
auto[0]	auto[1]	auto[2]	354020	1			T1	189		T2	3856		T9	1378
auto[0]	auto[1]	auto[3]	640484	1			T1	59		T2	353		T9	13491
auto[0]	auto[2]	auto[0]	191643	1			T15	285		T17	4		T137	11
auto[0]	auto[2]	auto[1]	24778	1			T15	35		T17	396		T138	2
auto[0]	auto[2]	auto[2]	17713	1			T15	46		T17	27		T137	94
auto[0]	auto[2]	auto[3]	54867	1			T15	4		T17	2980		T138	1
auto[0]	auto[3]	auto[0]	2893105	1			T1	1723		T2	39100		T9	135
auto[0]	auto[3]	auto[1]	340233	1			T1	162		T2	3908		T9	1314
auto[0]	auto[3]	auto[2]	351085	1			T1	478		T2	3508		T9	1257
auto[0]	auto[3]	auto[3]	586321	1			T1	49		T2	332		T9	12394
auto[1]	auto[0]	auto[0]	8645	1			T16	478		T133	1		T136	708
auto[1]	auto[0]	auto[1]	38766	1			T16	2295		T136	3023		T139	1539
auto[1]	auto[0]	auto[2]	38537	1			T16	2233		T118	1		T136	3048
auto[1]	auto[0]	auto[3]	174728	1			T16	10172		T17	3		T140	1
auto[1]	auto[1]	auto[0]	3616395	1			T10	1		T19	106036		T101	90553
auto[1]	auto[1]	auto[1]	680306	1			T19	10784		T101	8917		T16	2248
auto[1]	auto[1]	auto[2]	653319	1			T2	1		T19	10367		T20	1
auto[1]	auto[1]	auto[3]	1562385	1			T9	2		T19	1037		T101	880
auto[1]	auto[2]	auto[0]	7838	1			T16	470		T118	1		T136	648
auto[1]	auto[2]	auto[1]	35365	1			T16	2103		T136	2939		T139	966
auto[1]	auto[2]	auto[2]	30247	1			T16	1529		T136	2637		T139	1690
auto[1]	auto[2]	auto[3]	136454	1			T16	6885		T136	11910		T139	7592
auto[1]	auto[3]	auto[0]	3616497	1			T2	2		T13	1		T19	106174
auto[1]	auto[3]	auto[1]	650181	1			T19	10659		T101	8987		T16	222
auto[1]	auto[3]	auto[2]	671902	1			T2	1		T19	10609		T101	9099
auto[1]	auto[3]	auto[3]	1524710	1			T9	1		T19	1061		T101	893