Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1006204639	145126	0	0
ctrl_regwen_rd_A	1006204639	8103	0	0
exec_rd_A	1006204639	6517	0	0
exec_regwen_rd_A	1006204639	7775	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006204639	145126	0	0
T3	157217	4217	0	0
T4	69788	0	0	0
T8	1250	0	0	0
T9	94555	0	0	0
T10	76620	0	0	0
T11	140812	0	0	0
T12	100110	0	0	0
T13	337799	0	0	0
T14	89741	2505	0	0
T18	278629	0	0	0
T27	0	9687	0	0
T50	0	3	0	0
T51	0	4	0	0
T52	0	3	0	0
T53	0	102	0	0
T54	0	41	0	0
T55	0	3	0	0
T56	0	19	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006204639	8103	0	0
T14	89741	274	0	0
T15	120588	0	0	0
T19	489501	0	0	0
T20	777541	0	0	0
T21	688365	0	0	0
T33	34129	0	0	0
T60	0	124	0	0
T66	1340	33	0	0
T67	0	7	0	0
T71	0	65	0	0
T83	0	5	0	0
T101	469325	0	0	0
T102	76444	0	0	0
T103	369956	0	0	0
T104	0	3	0	0
T115	0	5	0	0
T116	0	67	0	0
T117	0	11	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006204639	6517	0	0
T14	89741	183	0	0
T15	120588	0	0	0
T19	489501	0	0	0
T20	777541	0	0	0
T21	688365	0	0	0
T33	34129	0	0	0
T60	0	119	0	0
T66	1340	18	0	0
T67	0	6	0	0
T71	0	50	0	0
T83	0	8	0	0
T101	469325	0	0	0
T102	76444	0	0	0
T103	369956	0	0	0
T104	0	3	0	0
T115	0	4	0	0
T116	0	17	0	0
T117	0	15	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006204639	7775	0	0
T14	89741	289	0	0
T15	120588	0	0	0
T19	489501	0	0	0
T20	777541	0	0	0
T21	688365	0	0	0
T33	34129	0	0	0
T60	0	172	0	0
T66	1340	9	0	0
T67	0	9	0	0
T71	0	29	0	0
T83	0	2	0	0
T101	469325	0	0	0
T102	76444	0	0	0
T103	369956	0	0	0
T104	0	1	0	0
T115	0	5	0	0
T116	0	23	0	0
T117	0	16	0	0