| T276 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2694970619 |
|
|
Dec 27 12:45:36 PM PST 23 |
Dec 27 01:57:50 PM PST 23 |
6751917860 ps |
| T277 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3412768539 |
|
|
Dec 27 12:44:24 PM PST 23 |
Dec 27 12:49:35 PM PST 23 |
25332310487 ps |
| T278 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.348567733 |
|
|
Dec 27 12:45:01 PM PST 23 |
Dec 27 01:00:10 PM PST 23 |
892869358 ps |
| T279 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3355288097 |
|
|
Dec 27 12:44:42 PM PST 23 |
Dec 27 12:50:22 PM PST 23 |
3834229857 ps |
| T280 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2496325571 |
|
|
Dec 27 12:45:50 PM PST 23 |
Dec 27 12:46:41 PM PST 23 |
2836124106 ps |
| T281 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1925022185 |
|
|
Dec 27 12:45:52 PM PST 23 |
Dec 27 12:46:00 PM PST 23 |
13005921 ps |
| T282 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2282320364 |
|
|
Dec 27 12:45:08 PM PST 23 |
Dec 27 12:52:58 PM PST 23 |
252481685408 ps |
| T283 |
/workspace/coverage/default/37.sram_ctrl_partial_access.3326415669 |
|
|
Dec 27 12:45:11 PM PST 23 |
Dec 27 12:47:25 PM PST 23 |
2654169307 ps |
| T284 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3903094393 |
|
|
Dec 27 12:44:23 PM PST 23 |
Dec 27 12:58:48 PM PST 23 |
4775474763 ps |
| T125 |
/workspace/coverage/default/13.sram_ctrl_regwen.558936621 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 01:00:24 PM PST 23 |
53461928729 ps |
| T285 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4158411102 |
|
|
Dec 27 12:44:21 PM PST 23 |
Dec 27 12:47:25 PM PST 23 |
3117686806 ps |
| T286 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3583179082 |
|
|
Dec 27 12:45:17 PM PST 23 |
Dec 27 01:21:15 PM PST 23 |
964288838 ps |
| T287 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.553251263 |
|
|
Dec 27 12:44:55 PM PST 23 |
Dec 27 12:45:30 PM PST 23 |
1379730726 ps |
| T288 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.595936836 |
|
|
Dec 27 12:44:56 PM PST 23 |
Dec 27 12:46:22 PM PST 23 |
1567681656 ps |
| T289 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.894976122 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 12:51:19 PM PST 23 |
14217826065 ps |
| T290 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3793324423 |
|
|
Dec 27 12:44:58 PM PST 23 |
Dec 27 12:51:46 PM PST 23 |
6070163231 ps |
| T291 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2678074430 |
|
|
Dec 27 12:45:20 PM PST 23 |
Dec 27 12:46:24 PM PST 23 |
811897145 ps |
| T292 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2297013640 |
|
|
Dec 27 12:44:25 PM PST 23 |
Dec 27 12:46:53 PM PST 23 |
7184992536 ps |
| T293 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1878460661 |
|
|
Dec 27 12:45:29 PM PST 23 |
Dec 27 01:07:47 PM PST 23 |
51939590100 ps |
| T294 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3407230704 |
|
|
Dec 27 12:44:34 PM PST 23 |
Dec 27 12:50:05 PM PST 23 |
50506402793 ps |
| T295 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2124835689 |
|
|
Dec 27 12:45:00 PM PST 23 |
Dec 27 12:45:15 PM PST 23 |
3347430792 ps |
| T296 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3598663609 |
|
|
Dec 27 12:45:26 PM PST 23 |
Dec 27 12:46:57 PM PST 23 |
2618524923 ps |
| T297 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.4001567483 |
|
|
Dec 27 12:45:43 PM PST 23 |
Dec 27 12:51:36 PM PST 23 |
32130378021 ps |
| T298 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.3711839081 |
|
|
Dec 27 12:45:22 PM PST 23 |
Dec 27 12:46:48 PM PST 23 |
775282528 ps |
| T299 |
/workspace/coverage/default/6.sram_ctrl_executable.451514136 |
|
|
Dec 27 12:44:36 PM PST 23 |
Dec 27 12:54:19 PM PST 23 |
13483497746 ps |
| T126 |
/workspace/coverage/default/18.sram_ctrl_executable.1120707125 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 01:01:13 PM PST 23 |
23515077660 ps |
| T300 |
/workspace/coverage/default/20.sram_ctrl_bijection.2619431256 |
|
|
Dec 27 12:44:26 PM PST 23 |
Dec 27 01:19:58 PM PST 23 |
403363695351 ps |
| T119 |
/workspace/coverage/default/12.sram_ctrl_regwen.3095586421 |
|
|
Dec 27 12:44:36 PM PST 23 |
Dec 27 01:02:27 PM PST 23 |
7648549700 ps |
| T301 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.4228018197 |
|
|
Dec 27 12:44:54 PM PST 23 |
Dec 27 12:45:47 PM PST 23 |
1694181679 ps |
| T302 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.558327497 |
|
|
Dec 27 12:44:30 PM PST 23 |
Dec 27 12:44:46 PM PST 23 |
492821156 ps |
| T303 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1590233031 |
|
|
Dec 27 12:44:30 PM PST 23 |
Dec 27 12:45:10 PM PST 23 |
725597912 ps |
| T304 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1539672756 |
|
|
Dec 27 12:44:19 PM PST 23 |
Dec 27 12:44:29 PM PST 23 |
11277216 ps |
| T305 |
/workspace/coverage/default/16.sram_ctrl_alert_test.1248915276 |
|
|
Dec 27 12:44:40 PM PST 23 |
Dec 27 12:44:47 PM PST 23 |
20428838 ps |
| T306 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2829740831 |
|
|
Dec 27 12:45:44 PM PST 23 |
Dec 27 12:45:53 PM PST 23 |
25616060 ps |
| T307 |
/workspace/coverage/default/30.sram_ctrl_partial_access.3762811044 |
|
|
Dec 27 12:45:07 PM PST 23 |
Dec 27 12:45:21 PM PST 23 |
520479322 ps |
| T308 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3178914857 |
|
|
Dec 27 12:44:45 PM PST 23 |
Dec 27 12:46:04 PM PST 23 |
1197039572 ps |
| T309 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2459363746 |
|
|
Dec 27 12:44:42 PM PST 23 |
Dec 27 12:52:27 PM PST 23 |
2938228125 ps |
| T24 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3656620646 |
|
|
Dec 27 12:44:24 PM PST 23 |
Dec 27 12:44:36 PM PST 23 |
511786127 ps |
| T39 |
/workspace/coverage/default/27.sram_ctrl_bijection.4043569179 |
|
|
Dec 27 12:45:10 PM PST 23 |
Dec 27 01:02:12 PM PST 23 |
14762713866 ps |
| T40 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.582891419 |
|
|
Dec 27 12:44:45 PM PST 23 |
Dec 27 12:45:42 PM PST 23 |
763813094 ps |
| T41 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2481962702 |
|
|
Dec 27 12:45:19 PM PST 23 |
Dec 27 12:48:30 PM PST 23 |
13368331005 ps |
| T42 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.4265762550 |
|
|
Dec 27 12:44:30 PM PST 23 |
Dec 27 01:02:33 PM PST 23 |
12296377113 ps |
| T43 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3465865685 |
|
|
Dec 27 12:44:50 PM PST 23 |
Dec 27 12:45:09 PM PST 23 |
369822881 ps |
| T44 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.509764148 |
|
|
Dec 27 12:44:20 PM PST 23 |
Dec 27 12:57:48 PM PST 23 |
20978261736 ps |
| T45 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.416580344 |
|
|
Dec 27 12:44:50 PM PST 23 |
Dec 27 12:50:25 PM PST 23 |
13923487757 ps |
| T46 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2136606525 |
|
|
Dec 27 12:45:55 PM PST 23 |
Dec 27 12:51:20 PM PST 23 |
53017993212 ps |
| T47 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1025399201 |
|
|
Dec 27 12:44:59 PM PST 23 |
Dec 27 12:46:24 PM PST 23 |
4797235586 ps |
| T310 |
/workspace/coverage/default/46.sram_ctrl_executable.3961146136 |
|
|
Dec 27 12:45:43 PM PST 23 |
Dec 27 12:58:42 PM PST 23 |
53048934553 ps |
| T311 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3504004981 |
|
|
Dec 27 12:44:34 PM PST 23 |
Dec 27 01:02:36 PM PST 23 |
9773043644 ps |
| T312 |
/workspace/coverage/default/46.sram_ctrl_bijection.1963747813 |
|
|
Dec 27 12:45:39 PM PST 23 |
Dec 27 01:17:39 PM PST 23 |
307210437046 ps |
| T313 |
/workspace/coverage/default/29.sram_ctrl_smoke.2068325789 |
|
|
Dec 27 12:45:03 PM PST 23 |
Dec 27 12:45:43 PM PST 23 |
3505463700 ps |
| T314 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2505982733 |
|
|
Dec 27 12:44:41 PM PST 23 |
Dec 27 12:59:03 PM PST 23 |
30600290892 ps |
| T315 |
/workspace/coverage/default/0.sram_ctrl_regwen.4185326964 |
|
|
Dec 27 12:44:24 PM PST 23 |
Dec 27 12:46:05 PM PST 23 |
3049757090 ps |
| T316 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3467484785 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 12:47:56 PM PST 23 |
5781750167 ps |
| T317 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.259912619 |
|
|
Dec 27 12:45:40 PM PST 23 |
Dec 27 12:52:03 PM PST 23 |
4584867332 ps |
| T318 |
/workspace/coverage/default/43.sram_ctrl_alert_test.658962690 |
|
|
Dec 27 12:45:33 PM PST 23 |
Dec 27 12:45:42 PM PST 23 |
37943403 ps |
| T319 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.157806254 |
|
|
Dec 27 12:44:59 PM PST 23 |
Dec 27 01:58:12 PM PST 23 |
6801462251 ps |
| T320 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2862144079 |
|
|
Dec 27 12:44:29 PM PST 23 |
Dec 27 12:46:29 PM PST 23 |
809783313 ps |
| T321 |
/workspace/coverage/default/31.sram_ctrl_bijection.1645669127 |
|
|
Dec 27 12:45:16 PM PST 23 |
Dec 27 12:59:26 PM PST 23 |
50567248415 ps |
| T322 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.335680707 |
|
|
Dec 27 12:45:31 PM PST 23 |
Dec 27 12:47:10 PM PST 23 |
3158367449 ps |
| T122 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1975069278 |
|
|
Dec 27 12:45:03 PM PST 23 |
Dec 27 01:24:07 PM PST 23 |
42793152983 ps |
| T323 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2228126221 |
|
|
Dec 27 12:44:46 PM PST 23 |
Dec 27 12:47:15 PM PST 23 |
3052111150 ps |
| T324 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.343507287 |
|
|
Dec 27 12:45:20 PM PST 23 |
Dec 27 12:47:44 PM PST 23 |
10676970568 ps |
| T325 |
/workspace/coverage/default/3.sram_ctrl_bijection.4218705960 |
|
|
Dec 27 12:44:24 PM PST 23 |
Dec 27 01:28:02 PM PST 23 |
119829416757 ps |
| T123 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1417842385 |
|
|
Dec 27 12:44:53 PM PST 23 |
Dec 27 02:35:48 PM PST 23 |
1013746143139 ps |
| T326 |
/workspace/coverage/default/40.sram_ctrl_bijection.2645413260 |
|
|
Dec 27 12:45:37 PM PST 23 |
Dec 27 01:27:51 PM PST 23 |
145553428876 ps |
| T327 |
/workspace/coverage/default/34.sram_ctrl_alert_test.4268090722 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 12:45:43 PM PST 23 |
24244096 ps |
| T328 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3596894519 |
|
|
Dec 27 12:44:11 PM PST 23 |
Dec 27 12:49:07 PM PST 23 |
9490075301 ps |
| T329 |
/workspace/coverage/default/0.sram_ctrl_smoke.804477768 |
|
|
Dec 27 12:44:06 PM PST 23 |
Dec 27 12:44:51 PM PST 23 |
3251710913 ps |
| T330 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.4123838927 |
|
|
Dec 27 12:45:12 PM PST 23 |
Dec 27 12:46:38 PM PST 23 |
10459381826 ps |
| T331 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2152262194 |
|
|
Dec 27 12:44:27 PM PST 23 |
Dec 27 12:47:16 PM PST 23 |
18771962470 ps |
| T332 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2973498590 |
|
|
Dec 27 12:45:52 PM PST 23 |
Dec 27 12:47:04 PM PST 23 |
4560485166 ps |
| T333 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3851122356 |
|
|
Dec 27 12:44:49 PM PST 23 |
Dec 27 12:45:29 PM PST 23 |
2882666623 ps |
| T334 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.4196247663 |
|
|
Dec 27 12:45:08 PM PST 23 |
Dec 27 12:57:28 PM PST 23 |
4010558741 ps |
| T335 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3535045283 |
|
|
Dec 27 12:45:20 PM PST 23 |
Dec 27 01:05:41 PM PST 23 |
23088481194 ps |
| T336 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3307131328 |
|
|
Dec 27 12:44:52 PM PST 23 |
Dec 27 01:01:19 PM PST 23 |
13733953359 ps |
| T337 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3137626821 |
|
|
Dec 27 12:45:28 PM PST 23 |
Dec 27 12:51:19 PM PST 23 |
4589715029 ps |
| T338 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2269496417 |
|
|
Dec 27 12:44:48 PM PST 23 |
Dec 27 12:49:06 PM PST 23 |
16522257132 ps |
| T339 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3711375685 |
|
|
Dec 27 12:45:09 PM PST 23 |
Dec 27 12:45:21 PM PST 23 |
680028707 ps |
| T340 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3304921326 |
|
|
Dec 27 12:44:14 PM PST 23 |
Dec 27 12:44:25 PM PST 23 |
47066514 ps |
| T341 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2045939117 |
|
|
Dec 27 12:44:55 PM PST 23 |
Dec 27 12:45:45 PM PST 23 |
881687155 ps |
| T342 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1777344551 |
|
|
Dec 27 12:45:35 PM PST 23 |
Dec 27 01:56:13 PM PST 23 |
1622724955 ps |
| T25 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.2565391798 |
|
|
Dec 27 12:44:29 PM PST 23 |
Dec 27 12:44:42 PM PST 23 |
3719646230 ps |
| T343 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3241659177 |
|
|
Dec 27 12:45:28 PM PST 23 |
Dec 27 12:45:36 PM PST 23 |
10786223 ps |
| T344 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.127367620 |
|
|
Dec 27 12:45:08 PM PST 23 |
Dec 27 12:54:13 PM PST 23 |
43584675501 ps |
| T345 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3757360536 |
|
|
Dec 27 12:45:18 PM PST 23 |
Dec 27 12:50:49 PM PST 23 |
6257819439 ps |
| T346 |
/workspace/coverage/default/38.sram_ctrl_partial_access.3991148267 |
|
|
Dec 27 12:45:44 PM PST 23 |
Dec 27 12:46:07 PM PST 23 |
999235274 ps |
| T347 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4285675195 |
|
|
Dec 27 12:44:09 PM PST 23 |
Dec 27 01:34:23 PM PST 23 |
588934317 ps |
| T348 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.3493655733 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 12:46:07 PM PST 23 |
2737124832 ps |
| T349 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4038170503 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 12:46:14 PM PST 23 |
1328168229 ps |
| T350 |
/workspace/coverage/default/32.sram_ctrl_smoke.2103587874 |
|
|
Dec 27 12:45:09 PM PST 23 |
Dec 27 12:45:43 PM PST 23 |
1743831460 ps |
| T351 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2045530120 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 12:47:11 PM PST 23 |
18839966750 ps |
| T352 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3836278708 |
|
|
Dec 27 12:44:19 PM PST 23 |
Dec 27 12:45:02 PM PST 23 |
2741625799 ps |
| T353 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.287934574 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 12:45:07 PM PST 23 |
737213931 ps |
| T354 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.122574920 |
|
|
Dec 27 12:44:42 PM PST 23 |
Dec 27 12:46:54 PM PST 23 |
46157091608 ps |
| T355 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1661618363 |
|
|
Dec 27 12:45:01 PM PST 23 |
Dec 27 12:45:39 PM PST 23 |
1260838005 ps |
| T356 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3686246539 |
|
|
Dec 27 12:44:46 PM PST 23 |
Dec 27 12:45:20 PM PST 23 |
2684717332 ps |
| T124 |
/workspace/coverage/default/20.sram_ctrl_regwen.1008414196 |
|
|
Dec 27 12:44:57 PM PST 23 |
Dec 27 01:16:26 PM PST 23 |
24692219068 ps |
| T357 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3157225199 |
|
|
Dec 27 12:45:18 PM PST 23 |
Dec 27 12:51:59 PM PST 23 |
10465832248 ps |
| T117 |
/workspace/coverage/default/24.sram_ctrl_executable.3922557054 |
|
|
Dec 27 12:45:10 PM PST 23 |
Dec 27 12:48:41 PM PST 23 |
9749159858 ps |
| T358 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1935338067 |
|
|
Dec 27 12:44:55 PM PST 23 |
Dec 27 12:45:12 PM PST 23 |
2358956546 ps |
| T359 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3677842709 |
|
|
Dec 27 12:44:43 PM PST 23 |
Dec 27 01:12:33 PM PST 23 |
109224216457 ps |
| T360 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1474607654 |
|
|
Dec 27 12:44:57 PM PST 23 |
Dec 27 02:13:24 PM PST 23 |
10924894598 ps |
| T361 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.974788226 |
|
|
Dec 27 12:45:02 PM PST 23 |
Dec 27 12:46:03 PM PST 23 |
3014862321 ps |
| T362 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1061451698 |
|
|
Dec 27 12:45:07 PM PST 23 |
Dec 27 12:46:57 PM PST 23 |
17104102715 ps |
| T363 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3664418923 |
|
|
Dec 27 12:44:33 PM PST 23 |
Dec 27 12:45:55 PM PST 23 |
3799557140 ps |
| T364 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2375543862 |
|
|
Dec 27 12:45:14 PM PST 23 |
Dec 27 01:04:32 PM PST 23 |
10407637732 ps |
| T365 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.667064604 |
|
|
Dec 27 12:45:17 PM PST 23 |
Dec 27 12:49:33 PM PST 23 |
16425340690 ps |
| T366 |
/workspace/coverage/default/40.sram_ctrl_alert_test.1944982561 |
|
|
Dec 27 12:45:23 PM PST 23 |
Dec 27 12:45:32 PM PST 23 |
184624410 ps |
| T367 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1007739048 |
|
|
Dec 27 12:45:33 PM PST 23 |
Dec 27 12:45:56 PM PST 23 |
718355783 ps |
| T368 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3758771179 |
|
|
Dec 27 12:45:20 PM PST 23 |
Dec 27 12:47:29 PM PST 23 |
22202539718 ps |
| T369 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2592011424 |
|
|
Dec 27 12:45:02 PM PST 23 |
Dec 27 12:45:35 PM PST 23 |
2684927200 ps |
| T370 |
/workspace/coverage/default/2.sram_ctrl_alert_test.2015046752 |
|
|
Dec 27 12:44:27 PM PST 23 |
Dec 27 12:44:37 PM PST 23 |
23065268 ps |
| T371 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3622038048 |
|
|
Dec 27 12:44:46 PM PST 23 |
Dec 27 01:00:31 PM PST 23 |
20704560354 ps |
| T372 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3482537005 |
|
|
Dec 27 12:45:40 PM PST 23 |
Dec 27 01:44:27 PM PST 23 |
5227334202 ps |
| T373 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2355982516 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 12:46:27 PM PST 23 |
3186317497 ps |
| T374 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2784151312 |
|
|
Dec 27 12:45:04 PM PST 23 |
Dec 27 02:25:56 PM PST 23 |
2226210980 ps |
| T375 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2501429590 |
|
|
Dec 27 12:45:05 PM PST 23 |
Dec 27 12:49:16 PM PST 23 |
8219269927 ps |
| T376 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.224856340 |
|
|
Dec 27 12:44:21 PM PST 23 |
Dec 27 12:44:37 PM PST 23 |
2814281425 ps |
| T118 |
/workspace/coverage/default/41.sram_ctrl_regwen.1966386328 |
|
|
Dec 27 12:45:36 PM PST 23 |
Dec 27 01:07:55 PM PST 23 |
89239284067 ps |
| T377 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.2707998946 |
|
|
Dec 27 12:45:42 PM PST 23 |
Dec 27 12:47:05 PM PST 23 |
6074584080 ps |
| T378 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.721958015 |
|
|
Dec 27 12:44:22 PM PST 23 |
Dec 27 01:12:34 PM PST 23 |
423248841 ps |
| T379 |
/workspace/coverage/default/25.sram_ctrl_bijection.2819424810 |
|
|
Dec 27 12:44:43 PM PST 23 |
Dec 27 01:04:43 PM PST 23 |
138433936166 ps |
| T380 |
/workspace/coverage/default/34.sram_ctrl_regwen.3651707952 |
|
|
Dec 27 12:45:16 PM PST 23 |
Dec 27 12:53:24 PM PST 23 |
111272300685 ps |
| T381 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2524430275 |
|
|
Dec 27 12:44:43 PM PST 23 |
Dec 27 12:52:44 PM PST 23 |
15129418444 ps |
| T382 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.144717842 |
|
|
Dec 27 12:44:13 PM PST 23 |
Dec 27 12:44:37 PM PST 23 |
1867745417 ps |
| T383 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3012933666 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 12:44:41 PM PST 23 |
14299707 ps |
| T384 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.398061209 |
|
|
Dec 27 12:45:14 PM PST 23 |
Dec 27 01:04:46 PM PST 23 |
394268856 ps |
| T385 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.336545757 |
|
|
Dec 27 12:44:12 PM PST 23 |
Dec 27 01:41:18 PM PST 23 |
1917554911 ps |
| T386 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1488989147 |
|
|
Dec 27 12:45:09 PM PST 23 |
Dec 27 12:47:49 PM PST 23 |
4563555669 ps |
| T387 |
/workspace/coverage/default/46.sram_ctrl_partial_access.37497382 |
|
|
Dec 27 12:45:25 PM PST 23 |
Dec 27 12:47:22 PM PST 23 |
1086327985 ps |
| T388 |
/workspace/coverage/default/40.sram_ctrl_executable.555213065 |
|
|
Dec 27 12:45:15 PM PST 23 |
Dec 27 12:48:56 PM PST 23 |
1755187527 ps |
| T389 |
/workspace/coverage/default/43.sram_ctrl_bijection.2700621655 |
|
|
Dec 27 12:45:40 PM PST 23 |
Dec 27 01:28:09 PM PST 23 |
607021092461 ps |
| T390 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.764000163 |
|
|
Dec 27 12:45:31 PM PST 23 |
Dec 27 12:45:45 PM PST 23 |
373615350 ps |
| T391 |
/workspace/coverage/default/14.sram_ctrl_executable.1739998752 |
|
|
Dec 27 12:45:05 PM PST 23 |
Dec 27 12:50:18 PM PST 23 |
30242344238 ps |
| T392 |
/workspace/coverage/default/22.sram_ctrl_bijection.4045177168 |
|
|
Dec 27 12:44:30 PM PST 23 |
Dec 27 01:14:36 PM PST 23 |
957500571412 ps |
| T393 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.819825437 |
|
|
Dec 27 12:44:55 PM PST 23 |
Dec 27 12:45:41 PM PST 23 |
2939491884 ps |
| T394 |
/workspace/coverage/default/8.sram_ctrl_bijection.3192257304 |
|
|
Dec 27 12:44:14 PM PST 23 |
Dec 27 01:21:25 PM PST 23 |
126068773838 ps |
| T395 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2936152754 |
|
|
Dec 27 12:45:18 PM PST 23 |
Dec 27 12:45:27 PM PST 23 |
18860218 ps |
| T396 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1912404984 |
|
|
Dec 27 12:45:00 PM PST 23 |
Dec 27 01:04:21 PM PST 23 |
15499275391 ps |
| T397 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3954271906 |
|
|
Dec 27 12:45:29 PM PST 23 |
Dec 27 12:48:07 PM PST 23 |
10184610851 ps |
| T398 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3870942184 |
|
|
Dec 27 12:45:29 PM PST 23 |
Dec 27 12:45:41 PM PST 23 |
390564457 ps |
| T399 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2985432011 |
|
|
Dec 27 12:44:29 PM PST 23 |
Dec 27 12:45:47 PM PST 23 |
4049815404 ps |
| T400 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.124578064 |
|
|
Dec 27 12:44:51 PM PST 23 |
Dec 27 01:21:15 PM PST 23 |
52934602239 ps |
| T401 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.818325344 |
|
|
Dec 27 12:45:31 PM PST 23 |
Dec 27 12:46:14 PM PST 23 |
801531808 ps |
| T402 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1645678344 |
|
|
Dec 27 12:44:09 PM PST 23 |
Dec 27 12:44:27 PM PST 23 |
1403551962 ps |
| T403 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.1683798988 |
|
|
Dec 27 12:45:08 PM PST 23 |
Dec 27 12:48:59 PM PST 23 |
2726762199 ps |
| T404 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1660325506 |
|
|
Dec 27 12:44:51 PM PST 23 |
Dec 27 12:46:49 PM PST 23 |
18495814735 ps |
| T405 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.658324180 |
|
|
Dec 27 12:44:54 PM PST 23 |
Dec 27 12:47:02 PM PST 23 |
7897016596 ps |
| T406 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2266749389 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 12:49:41 PM PST 23 |
49281470952 ps |
| T407 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3688366363 |
|
|
Dec 27 12:45:23 PM PST 23 |
Dec 27 12:53:33 PM PST 23 |
15062272466 ps |
| T408 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1548938312 |
|
|
Dec 27 12:44:44 PM PST 23 |
Dec 27 12:45:12 PM PST 23 |
515370189 ps |
| T409 |
/workspace/coverage/default/49.sram_ctrl_executable.2301160767 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 12:49:45 PM PST 23 |
3329055264 ps |
| T410 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1001601917 |
|
|
Dec 27 12:45:33 PM PST 23 |
Dec 27 12:53:06 PM PST 23 |
6161166832 ps |
| T411 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3725069881 |
|
|
Dec 27 12:44:53 PM PST 23 |
Dec 27 12:46:43 PM PST 23 |
38901566727 ps |
| T412 |
/workspace/coverage/default/1.sram_ctrl_alert_test.979858587 |
|
|
Dec 27 12:44:50 PM PST 23 |
Dec 27 12:44:58 PM PST 23 |
50328878 ps |
| T413 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3383724070 |
|
|
Dec 27 12:44:22 PM PST 23 |
Dec 27 12:45:04 PM PST 23 |
2103607261 ps |
| T414 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1689540520 |
|
|
Dec 27 12:45:21 PM PST 23 |
Dec 27 12:50:29 PM PST 23 |
41265313360 ps |
| T415 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1557927102 |
|
|
Dec 27 12:45:00 PM PST 23 |
Dec 27 01:08:20 PM PST 23 |
41917943382 ps |
| T416 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2125727662 |
|
|
Dec 27 12:45:07 PM PST 23 |
Dec 27 12:51:10 PM PST 23 |
30546841460 ps |
| T417 |
/workspace/coverage/default/19.sram_ctrl_smoke.1878954820 |
|
|
Dec 27 12:45:06 PM PST 23 |
Dec 27 12:46:10 PM PST 23 |
10005148233 ps |
| T418 |
/workspace/coverage/default/43.sram_ctrl_smoke.350493544 |
|
|
Dec 27 12:45:35 PM PST 23 |
Dec 27 12:46:21 PM PST 23 |
726975998 ps |
| T419 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1550894590 |
|
|
Dec 27 12:45:36 PM PST 23 |
Dec 27 12:55:01 PM PST 23 |
34522346104 ps |
| T420 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1249364287 |
|
|
Dec 27 12:45:21 PM PST 23 |
Dec 27 12:46:00 PM PST 23 |
5259186843 ps |
| T421 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2658784558 |
|
|
Dec 27 12:45:14 PM PST 23 |
Dec 27 12:47:33 PM PST 23 |
1040943350 ps |
| T422 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3099488848 |
|
|
Dec 27 12:44:17 PM PST 23 |
Dec 27 12:44:41 PM PST 23 |
1258988175 ps |
| T423 |
/workspace/coverage/default/18.sram_ctrl_bijection.3263930636 |
|
|
Dec 27 12:44:44 PM PST 23 |
Dec 27 01:03:42 PM PST 23 |
32152402120 ps |
| T424 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3595954610 |
|
|
Dec 27 12:44:27 PM PST 23 |
Dec 27 02:12:58 PM PST 23 |
7654793032 ps |
| T425 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.1093104476 |
|
|
Dec 27 12:44:52 PM PST 23 |
Dec 27 12:46:43 PM PST 23 |
9153901239 ps |
| T426 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.779925977 |
|
|
Dec 27 12:44:34 PM PST 23 |
Dec 27 12:45:38 PM PST 23 |
3042392758 ps |
| T427 |
/workspace/coverage/default/34.sram_ctrl_smoke.1901497039 |
|
|
Dec 27 12:45:06 PM PST 23 |
Dec 27 12:46:53 PM PST 23 |
15900218622 ps |
| T428 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2083604985 |
|
|
Dec 27 12:45:16 PM PST 23 |
Dec 27 01:07:08 PM PST 23 |
20381301376 ps |
| T429 |
/workspace/coverage/default/44.sram_ctrl_partial_access.844287469 |
|
|
Dec 27 12:45:27 PM PST 23 |
Dec 27 12:46:19 PM PST 23 |
3089681173 ps |
| T430 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3290977576 |
|
|
Dec 27 12:44:39 PM PST 23 |
Dec 27 02:15:34 PM PST 23 |
129714229110 ps |
| T431 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2128785203 |
|
|
Dec 27 12:44:49 PM PST 23 |
Dec 27 12:51:13 PM PST 23 |
35184394717 ps |
| T432 |
/workspace/coverage/default/38.sram_ctrl_smoke.42515451 |
|
|
Dec 27 12:45:46 PM PST 23 |
Dec 27 12:48:35 PM PST 23 |
1174974352 ps |
| T433 |
/workspace/coverage/default/40.sram_ctrl_smoke.3736619777 |
|
|
Dec 27 12:45:15 PM PST 23 |
Dec 27 12:45:58 PM PST 23 |
1596139292 ps |
| T434 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.359527666 |
|
|
Dec 27 12:45:35 PM PST 23 |
Dec 27 12:52:35 PM PST 23 |
37775833347 ps |
| T435 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.910225541 |
|
|
Dec 27 12:45:17 PM PST 23 |
Dec 27 12:52:12 PM PST 23 |
17028849168 ps |
| T436 |
/workspace/coverage/default/29.sram_ctrl_partial_access.3257685688 |
|
|
Dec 27 12:45:11 PM PST 23 |
Dec 27 12:45:37 PM PST 23 |
964648211 ps |
| T437 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1425866576 |
|
|
Dec 27 12:44:41 PM PST 23 |
Dec 27 12:46:50 PM PST 23 |
2059987917 ps |
| T438 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.959683552 |
|
|
Dec 27 12:45:09 PM PST 23 |
Dec 27 12:45:21 PM PST 23 |
364613501 ps |
| T439 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1015660967 |
|
|
Dec 27 12:44:26 PM PST 23 |
Dec 27 12:51:49 PM PST 23 |
15037258171 ps |
| T440 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.806254048 |
|
|
Dec 27 12:45:19 PM PST 23 |
Dec 27 12:48:55 PM PST 23 |
29105089214 ps |
| T441 |
/workspace/coverage/default/21.sram_ctrl_smoke.4012429079 |
|
|
Dec 27 12:45:01 PM PST 23 |
Dec 27 12:45:33 PM PST 23 |
6654945359 ps |
| T442 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2910753399 |
|
|
Dec 27 12:44:25 PM PST 23 |
Dec 27 01:50:16 PM PST 23 |
2555040156 ps |
| T443 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.4215504009 |
|
|
Dec 27 12:45:21 PM PST 23 |
Dec 27 12:48:38 PM PST 23 |
37845666420 ps |
| T444 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3882500874 |
|
|
Dec 27 12:44:35 PM PST 23 |
Dec 27 12:47:24 PM PST 23 |
10768323086 ps |
| T445 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1206070086 |
|
|
Dec 27 12:44:53 PM PST 23 |
Dec 27 01:11:47 PM PST 23 |
49543519459 ps |
| T446 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.4151216145 |
|
|
Dec 27 12:45:13 PM PST 23 |
Dec 27 12:45:49 PM PST 23 |
695297577 ps |
| T447 |
/workspace/coverage/default/33.sram_ctrl_bijection.2385673247 |
|
|
Dec 27 12:45:23 PM PST 23 |
Dec 27 01:21:42 PM PST 23 |
133764952290 ps |
| T448 |
/workspace/coverage/default/15.sram_ctrl_regwen.2160056100 |
|
|
Dec 27 12:44:34 PM PST 23 |
Dec 27 01:04:57 PM PST 23 |
8108278065 ps |
| T449 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.986989154 |
|
|
Dec 27 12:44:16 PM PST 23 |
Dec 27 12:46:12 PM PST 23 |
7647419184 ps |
| T450 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3380233038 |
|
|
Dec 27 12:44:25 PM PST 23 |
Dec 27 12:48:32 PM PST 23 |
15761162154 ps |
| T451 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1263606587 |
|
|
Dec 27 12:44:14 PM PST 23 |
Dec 27 02:48:09 PM PST 23 |
322199082454 ps |
| T452 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3122505421 |
|
|
Dec 27 12:45:31 PM PST 23 |
Dec 27 12:46:24 PM PST 23 |
5440705845 ps |
| T453 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1509079597 |
|
|
Dec 27 12:44:37 PM PST 23 |
Dec 27 12:44:58 PM PST 23 |
1405709534 ps |
| T454 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4181505424 |
|
|
Dec 27 12:44:53 PM PST 23 |
Dec 27 12:46:26 PM PST 23 |
5043905659 ps |
| T455 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3035080644 |
|
|
Dec 27 12:44:57 PM PST 23 |
Dec 27 01:36:11 PM PST 23 |
1675136743 ps |
| T456 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2684359724 |
|
|
Dec 27 12:44:54 PM PST 23 |
Dec 27 12:46:53 PM PST 23 |
9907518479 ps |
| T457 |
/workspace/coverage/default/15.sram_ctrl_alert_test.3491607276 |
|
|
Dec 27 12:44:22 PM PST 23 |
Dec 27 12:44:32 PM PST 23 |
38427059 ps |
| T458 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2182271096 |
|
|
Dec 27 12:45:32 PM PST 23 |
Dec 27 12:47:04 PM PST 23 |
92620861399 ps |
| T459 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3705729648 |
|
|
Dec 27 12:45:36 PM PST 23 |
Dec 27 01:01:33 PM PST 23 |
73327151385 ps |
| T460 |
/workspace/coverage/default/30.sram_ctrl_executable.2896577908 |
|
|
Dec 27 12:45:14 PM PST 23 |
Dec 27 12:59:57 PM PST 23 |
68240878145 ps |
| T461 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.255671855 |
|
|
Dec 27 12:44:25 PM PST 23 |
Dec 27 12:46:36 PM PST 23 |
46960665524 ps |
| T462 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3070989204 |
|
|
Dec 27 12:45:05 PM PST 23 |
Dec 27 12:45:17 PM PST 23 |
1345626628 ps |
| T26 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.4089603100 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 12:44:44 PM PST 23 |
225646445 ps |
| T463 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.65227840 |
|
|
Dec 27 12:45:50 PM PST 23 |
Dec 27 12:50:18 PM PST 23 |
15665705329 ps |
| T464 |
/workspace/coverage/default/33.sram_ctrl_regwen.359835592 |
|
|
Dec 27 12:45:32 PM PST 23 |
Dec 27 12:55:07 PM PST 23 |
9024806910 ps |
| T465 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1013987154 |
|
|
Dec 27 12:44:48 PM PST 23 |
Dec 27 01:47:22 PM PST 23 |
1089655407 ps |
| T466 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3596433264 |
|
|
Dec 27 12:45:04 PM PST 23 |
Dec 27 12:45:26 PM PST 23 |
535604777 ps |
| T467 |
/workspace/coverage/default/9.sram_ctrl_stress_all.542965654 |
|
|
Dec 27 12:44:56 PM PST 23 |
Dec 27 02:04:57 PM PST 23 |
397818708953 ps |
| T468 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2284838917 |
|
|
Dec 27 12:44:26 PM PST 23 |
Dec 27 01:03:27 PM PST 23 |
64154677252 ps |
| T469 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1904920959 |
|
|
Dec 27 12:44:30 PM PST 23 |
Dec 27 02:07:07 PM PST 23 |
2762265538 ps |
| T470 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1806676709 |
|
|
Dec 27 12:45:40 PM PST 23 |
Dec 27 12:48:28 PM PST 23 |
21138821561 ps |
| T471 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.221658915 |
|
|
Dec 27 12:45:33 PM PST 23 |
Dec 27 12:45:54 PM PST 23 |
1351566596 ps |
| T472 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.560408552 |
|
|
Dec 27 12:45:09 PM PST 23 |
Dec 27 12:46:29 PM PST 23 |
1971989682 ps |
| T473 |
/workspace/coverage/default/5.sram_ctrl_executable.2730831696 |
|
|
Dec 27 12:45:07 PM PST 23 |
Dec 27 12:52:19 PM PST 23 |
4290290100 ps |
| T474 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1447470865 |
|
|
Dec 27 12:44:16 PM PST 23 |
Dec 27 12:47:15 PM PST 23 |
2604469353 ps |
| T475 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3465023825 |
|
|
Dec 27 12:44:45 PM PST 23 |
Dec 27 12:47:02 PM PST 23 |
1554664849 ps |
| T476 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1577015620 |
|
|
Dec 27 12:44:54 PM PST 23 |
Dec 27 01:10:54 PM PST 23 |
27124413605 ps |
| T477 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.2265966345 |
|
|
Dec 27 12:44:31 PM PST 23 |
Dec 27 01:05:24 PM PST 23 |
14102426309 ps |
| T478 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2583094349 |
|
|
Dec 27 12:45:20 PM PST 23 |
Dec 27 12:47:25 PM PST 23 |
3190660356 ps |
| T479 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2775386276 |
|
|
Dec 27 12:44:13 PM PST 23 |
Dec 27 12:46:24 PM PST 23 |
12451719252 ps |
| T480 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.886008481 |
|
|
Dec 27 12:44:51 PM PST 23 |
Dec 27 01:52:29 PM PST 23 |
1247762356 ps |
| T481 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2186211930 |
|
|
Dec 27 12:45:29 PM PST 23 |
Dec 27 01:03:53 PM PST 23 |
100600959440 ps |
| T482 |
/workspace/coverage/default/5.sram_ctrl_regwen.3767564910 |
|
|
Dec 27 12:45:01 PM PST 23 |
Dec 27 12:47:16 PM PST 23 |
1219329524 ps |
| T483 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1659818908 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 12:51:46 PM PST 23 |
15531389476 ps |
| T484 |
/workspace/coverage/default/32.sram_ctrl_regwen.2074791375 |
|
|
Dec 27 12:45:33 PM PST 23 |
Dec 27 01:11:16 PM PST 23 |
100348652107 ps |
| T485 |
/workspace/coverage/default/7.sram_ctrl_bijection.1880601721 |
|
|
Dec 27 12:44:52 PM PST 23 |
Dec 27 01:01:12 PM PST 23 |
221456386822 ps |
| T486 |
/workspace/coverage/default/26.sram_ctrl_regwen.3187107753 |
|
|
Dec 27 12:45:02 PM PST 23 |
Dec 27 12:57:47 PM PST 23 |
28752147047 ps |
| T487 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.945623350 |
|
|
Dec 27 12:45:35 PM PST 23 |
Dec 27 01:02:16 PM PST 23 |
8149261936 ps |
| T488 |
/workspace/coverage/default/41.sram_ctrl_bijection.317422862 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 01:21:41 PM PST 23 |
473749868854 ps |
| T489 |
/workspace/coverage/default/26.sram_ctrl_stress_all.3841972006 |
|
|
Dec 27 12:44:57 PM PST 23 |
Dec 27 01:48:00 PM PST 23 |
538313556738 ps |
| T490 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3438430591 |
|
|
Dec 27 12:45:00 PM PST 23 |
Dec 27 12:45:40 PM PST 23 |
7521612752 ps |
| T120 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2876449275 |
|
|
Dec 27 12:45:34 PM PST 23 |
Dec 27 01:24:01 PM PST 23 |
204794726836 ps |
| T491 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1930423271 |
|
|
Dec 27 12:44:42 PM PST 23 |
Dec 27 01:03:14 PM PST 23 |
31438298367 ps |
| T492 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1261737973 |
|
|
Dec 27 12:45:14 PM PST 23 |
Dec 27 12:50:45 PM PST 23 |
29532457812 ps |
| T493 |
/workspace/coverage/default/1.sram_ctrl_smoke.429038186 |
|
|
Dec 27 12:44:33 PM PST 23 |
Dec 27 12:45:19 PM PST 23 |
749255193 ps |
| T494 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.658110152 |
|
|
Dec 27 12:45:18 PM PST 23 |
Dec 27 12:47:55 PM PST 23 |
19048532670 ps |
| T495 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4009084615 |
|
|
Dec 27 12:45:38 PM PST 23 |
Dec 27 12:48:33 PM PST 23 |
812962208 ps |
| T496 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.551118629 |
|
|
Dec 27 12:44:48 PM PST 23 |
Dec 27 12:45:26 PM PST 23 |
716815455 ps |
| T497 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3026473880 |
|
|
Dec 27 12:44:49 PM PST 23 |
Dec 27 12:51:49 PM PST 23 |
16457735799 ps |
| T498 |
/workspace/coverage/default/48.sram_ctrl_regwen.256091041 |
|
|
Dec 27 12:45:31 PM PST 23 |
Dec 27 01:00:56 PM PST 23 |
5113560254 ps |
| T499 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.2429395081 |
|
|
Dec 27 12:45:18 PM PST 23 |
Dec 27 12:46:08 PM PST 23 |
2922323707 ps |
| T121 |
/workspace/coverage/default/1.sram_ctrl_regwen.2610364875 |
|
|
Dec 27 12:44:33 PM PST 23 |
Dec 27 01:18:25 PM PST 23 |
22195010192 ps |
| T500 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2885731403 |
|
|
Dec 27 12:44:49 PM PST 23 |
Dec 27 12:48:58 PM PST 23 |
9270399855 ps |
| T501 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1437104083 |
|
|
Dec 27 12:45:42 PM PST 23 |
Dec 27 12:46:20 PM PST 23 |
726884090 ps |
| T502 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2809811432 |
|
|
Dec 27 12:44:50 PM PST 23 |
Dec 27 12:46:07 PM PST 23 |
50738493689 ps |
| T503 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1360949725 |
|
|
Dec 27 12:44:40 PM PST 23 |
Dec 27 12:46:07 PM PST 23 |
10870650907 ps |