SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
99.67 | 100.00 | 98.27 | 100.00 | 100.00 | 99.71 | 99.70 | 100.00 |
T754 | /workspace/coverage/default/46.sram_ctrl_alert_test.1762960266 | Dec 27 12:45:21 PM PST 23 | Dec 27 12:45:30 PM PST 23 | 84910467 ps | ||
T755 | /workspace/coverage/default/29.sram_ctrl_stress_all.3180375620 | Dec 27 12:45:00 PM PST 23 | Dec 27 01:43:50 PM PST 23 | 285583830170 ps | ||
T756 | /workspace/coverage/default/22.sram_ctrl_regwen.3726843224 | Dec 27 12:44:55 PM PST 23 | Dec 27 01:14:57 PM PST 23 | 81695015510 ps | ||
T757 | /workspace/coverage/default/21.sram_ctrl_bijection.3691061110 | Dec 27 12:45:04 PM PST 23 | Dec 27 01:17:16 PM PST 23 | 82891890018 ps | ||
T758 | /workspace/coverage/default/13.sram_ctrl_executable.669858042 | Dec 27 12:44:34 PM PST 23 | Dec 27 12:46:52 PM PST 23 | 3369712982 ps | ||
T759 | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3334600918 | Dec 27 12:44:34 PM PST 23 | Dec 27 12:50:06 PM PST 23 | 26442419923 ps | ||
T760 | /workspace/coverage/default/24.sram_ctrl_alert_test.292343226 | Dec 27 12:44:48 PM PST 23 | Dec 27 12:44:55 PM PST 23 | 12661303 ps | ||
T761 | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2708940754 | Dec 27 12:44:53 PM PST 23 | Dec 27 12:46:12 PM PST 23 | 1922544592 ps | ||
T762 | /workspace/coverage/default/42.sram_ctrl_regwen.46290062 | Dec 27 12:45:58 PM PST 23 | Dec 27 01:11:30 PM PST 23 | 14515646822 ps | ||
T763 | /workspace/coverage/default/19.sram_ctrl_executable.3883543957 | Dec 27 12:44:45 PM PST 23 | Dec 27 12:52:42 PM PST 23 | 8439942621 ps | ||
T764 | /workspace/coverage/default/22.sram_ctrl_partial_access.3726473391 | Dec 27 12:45:02 PM PST 23 | Dec 27 12:46:11 PM PST 23 | 1153320666 ps | ||
T765 | /workspace/coverage/default/21.sram_ctrl_alert_test.1543371081 | Dec 27 12:44:45 PM PST 23 | Dec 27 12:44:51 PM PST 23 | 24143050 ps | ||
T766 | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3030078117 | Dec 27 12:44:38 PM PST 23 | Dec 27 12:44:52 PM PST 23 | 1058048187 ps | ||
T767 | /workspace/coverage/default/39.sram_ctrl_executable.4262107223 | Dec 27 12:45:30 PM PST 23 | Dec 27 12:51:49 PM PST 23 | 10000619071 ps | ||
T768 | /workspace/coverage/default/48.sram_ctrl_ram_cfg.3374505429 | Dec 27 12:45:33 PM PST 23 | Dec 27 12:45:54 PM PST 23 | 1397611606 ps | ||
T769 | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.124803744 | Dec 27 12:45:21 PM PST 23 | Dec 27 01:21:17 PM PST 23 | 6677203714 ps | ||
T770 | /workspace/coverage/default/30.sram_ctrl_alert_test.3418876639 | Dec 27 12:45:04 PM PST 23 | Dec 27 12:45:12 PM PST 23 | 17116981 ps | ||
T771 | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1844087603 | Dec 27 12:45:39 PM PST 23 | Dec 27 12:52:00 PM PST 23 | 5682898449 ps | ||
T772 | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3312187471 | Dec 27 12:45:55 PM PST 23 | Dec 27 12:46:42 PM PST 23 | 734323392 ps | ||
T773 | /workspace/coverage/default/31.sram_ctrl_mem_walk.2627547393 | Dec 27 12:45:09 PM PST 23 | Dec 27 12:49:50 PM PST 23 | 26534266870 ps | ||
T774 | /workspace/coverage/default/48.sram_ctrl_max_throughput.3689005476 | Dec 27 12:45:29 PM PST 23 | Dec 27 12:46:33 PM PST 23 | 727517350 ps | ||
T775 | /workspace/coverage/default/27.sram_ctrl_alert_test.1525818045 | Dec 27 12:45:02 PM PST 23 | Dec 27 12:45:09 PM PST 23 | 24274879 ps | ||
T776 | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.4090113050 | Dec 27 12:44:34 PM PST 23 | Dec 27 12:51:00 PM PST 23 | 5001089984 ps | ||
T777 | /workspace/coverage/default/27.sram_ctrl_multiple_keys.3035859122 | Dec 27 12:45:08 PM PST 23 | Dec 27 12:56:14 PM PST 23 | 9184467463 ps | ||
T778 | /workspace/coverage/default/26.sram_ctrl_smoke.521602580 | Dec 27 12:45:13 PM PST 23 | Dec 27 12:46:47 PM PST 23 | 6140654977 ps | ||
T779 | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.130400660 | Dec 27 12:45:25 PM PST 23 | Dec 27 12:55:54 PM PST 23 | 135537579916 ps | ||
T780 | /workspace/coverage/default/4.sram_ctrl_regwen.681070009 | Dec 27 12:45:05 PM PST 23 | Dec 27 12:53:12 PM PST 23 | 25325167723 ps | ||
T781 | /workspace/coverage/default/41.sram_ctrl_alert_test.3774230592 | Dec 27 12:45:21 PM PST 23 | Dec 27 12:45:31 PM PST 23 | 31985204 ps | ||
T782 | /workspace/coverage/default/18.sram_ctrl_partial_access.1719047720 | Dec 27 12:45:17 PM PST 23 | Dec 27 12:45:48 PM PST 23 | 4993848209 ps | ||
T783 | /workspace/coverage/default/17.sram_ctrl_ram_cfg.884124696 | Dec 27 12:44:48 PM PST 23 | Dec 27 12:45:00 PM PST 23 | 4789343030 ps | ||
T784 | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1921623507 | Dec 27 12:45:27 PM PST 23 | Dec 27 01:09:48 PM PST 23 | 6518574618 ps | ||
T785 | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.517620531 | Dec 27 12:45:12 PM PST 23 | Dec 27 12:45:50 PM PST 23 | 1409182480 ps | ||
T37 | /workspace/coverage/default/0.sram_ctrl_sec_cm.3782452828 | Dec 27 12:44:33 PM PST 23 | Dec 27 12:44:44 PM PST 23 | 327819750 ps | ||
T786 | /workspace/coverage/default/3.sram_ctrl_max_throughput.3741402444 | Dec 27 12:44:49 PM PST 23 | Dec 27 12:46:24 PM PST 23 | 1493266203 ps | ||
T787 | /workspace/coverage/default/0.sram_ctrl_max_throughput.2441557702 | Dec 27 12:44:23 PM PST 23 | Dec 27 12:45:48 PM PST 23 | 745086899 ps | ||
T788 | /workspace/coverage/default/37.sram_ctrl_smoke.497866888 | Dec 27 12:45:40 PM PST 23 | Dec 27 12:46:17 PM PST 23 | 1044295518 ps | ||
T789 | /workspace/coverage/default/28.sram_ctrl_regwen.4009786541 | Dec 27 12:45:06 PM PST 23 | Dec 27 12:58:49 PM PST 23 | 36094350566 ps | ||
T790 | /workspace/coverage/default/23.sram_ctrl_smoke.1023704842 | Dec 27 12:45:01 PM PST 23 | Dec 27 12:45:59 PM PST 23 | 2880303516 ps | ||
T791 | /workspace/coverage/default/42.sram_ctrl_alert_test.1032352619 | Dec 27 12:45:22 PM PST 23 | Dec 27 12:45:32 PM PST 23 | 32711245 ps | ||
T792 | /workspace/coverage/default/0.sram_ctrl_ram_cfg.745524202 | Dec 27 12:44:09 PM PST 23 | Dec 27 12:44:35 PM PST 23 | 1412334986 ps | ||
T793 | /workspace/coverage/default/16.sram_ctrl_smoke.1617866092 | Dec 27 12:44:53 PM PST 23 | Dec 27 12:45:21 PM PST 23 | 999552130 ps | ||
T794 | /workspace/coverage/default/49.sram_ctrl_stress_all.3332939857 | Dec 27 12:45:54 PM PST 23 | Dec 27 01:29:05 PM PST 23 | 60746670789 ps | ||
T795 | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3714175986 | Dec 27 12:45:40 PM PST 23 | Dec 27 12:52:44 PM PST 23 | 11463226934 ps | ||
T796 | /workspace/coverage/default/45.sram_ctrl_smoke.383929492 | Dec 27 12:45:34 PM PST 23 | Dec 27 12:46:02 PM PST 23 | 1112988951 ps | ||
T797 | /workspace/coverage/default/17.sram_ctrl_partial_access.2548854138 | Dec 27 12:44:32 PM PST 23 | Dec 27 12:46:12 PM PST 23 | 5714179990 ps | ||
T798 | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.613197654 | Dec 27 12:45:07 PM PST 23 | Dec 27 12:50:25 PM PST 23 | 65051416318 ps | ||
T799 | /workspace/coverage/default/22.sram_ctrl_ram_cfg.2246802534 | Dec 27 12:44:47 PM PST 23 | Dec 27 12:44:59 PM PST 23 | 1539417892 ps | ||
T800 | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1382439679 | Dec 27 12:44:57 PM PST 23 | Dec 27 12:51:32 PM PST 23 | 22620619529 ps | ||
T801 | /workspace/coverage/default/45.sram_ctrl_bijection.717659000 | Dec 27 12:45:33 PM PST 23 | Dec 27 12:56:52 PM PST 23 | 164169887071 ps | ||
T802 | /workspace/coverage/default/18.sram_ctrl_smoke.3148745864 | Dec 27 12:44:59 PM PST 23 | Dec 27 12:45:20 PM PST 23 | 1265358927 ps | ||
T803 | /workspace/coverage/default/3.sram_ctrl_alert_test.3644351109 | Dec 27 12:44:23 PM PST 23 | Dec 27 12:44:33 PM PST 23 | 36472215 ps | ||
T804 | /workspace/coverage/default/25.sram_ctrl_max_throughput.2792610010 | Dec 27 12:44:57 PM PST 23 | Dec 27 12:45:49 PM PST 23 | 721692594 ps | ||
T805 | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1829756780 | Dec 27 12:44:15 PM PST 23 | Dec 27 12:46:05 PM PST 23 | 15342089041 ps | ||
T806 | /workspace/coverage/default/38.sram_ctrl_executable.3301312656 | Dec 27 12:45:38 PM PST 23 | Dec 27 01:11:09 PM PST 23 | 105101280510 ps | ||
T807 | /workspace/coverage/default/7.sram_ctrl_regwen.2921958398 | Dec 27 12:44:22 PM PST 23 | Dec 27 12:45:24 PM PST 23 | 9455569855 ps | ||
T808 | /workspace/coverage/default/29.sram_ctrl_ram_cfg.2274662170 | Dec 27 12:44:50 PM PST 23 | Dec 27 12:45:03 PM PST 23 | 1412850786 ps | ||
T809 | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.409493396 | Dec 27 12:45:08 PM PST 23 | Dec 27 12:47:38 PM PST 23 | 3129168198 ps | ||
T810 | /workspace/coverage/default/13.sram_ctrl_smoke.3337438971 | Dec 27 12:44:36 PM PST 23 | Dec 27 12:45:06 PM PST 23 | 1421826706 ps | ||
T811 | /workspace/coverage/default/42.sram_ctrl_mem_walk.1503632258 | Dec 27 12:45:32 PM PST 23 | Dec 27 12:50:30 PM PST 23 | 57444852539 ps | ||
T812 | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4099726546 | Dec 27 12:45:03 PM PST 23 | Dec 27 01:08:10 PM PST 23 | 8883011871 ps | ||
T813 | /workspace/coverage/default/26.sram_ctrl_mem_walk.63097409 | Dec 27 12:44:54 PM PST 23 | Dec 27 12:49:37 PM PST 23 | 13810769393 ps | ||
T814 | /workspace/coverage/default/31.sram_ctrl_executable.1288440858 | Dec 27 12:45:29 PM PST 23 | Dec 27 12:57:54 PM PST 23 | 13714324094 ps | ||
T815 | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2459269362 | Dec 27 12:45:12 PM PST 23 | Dec 27 12:49:48 PM PST 23 | 8688199187 ps | ||
T816 | /workspace/coverage/default/34.sram_ctrl_ram_cfg.1730182998 | Dec 27 12:45:18 PM PST 23 | Dec 27 12:45:40 PM PST 23 | 355798368 ps | ||
T817 | /workspace/coverage/default/48.sram_ctrl_bijection.2975826572 | Dec 27 12:45:44 PM PST 23 | Dec 27 01:09:45 PM PST 23 | 83327915790 ps | ||
T818 | /workspace/coverage/default/0.sram_ctrl_mem_walk.67723935 | Dec 27 12:44:33 PM PST 23 | Dec 27 12:49:46 PM PST 23 | 55096451611 ps | ||
T819 | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.689783817 | Dec 27 12:45:09 PM PST 23 | Dec 27 12:49:10 PM PST 23 | 3325873159 ps | ||
T820 | /workspace/coverage/default/4.sram_ctrl_partial_access.2858932030 | Dec 27 12:44:32 PM PST 23 | Dec 27 12:45:00 PM PST 23 | 4218777661 ps | ||
T821 | /workspace/coverage/default/15.sram_ctrl_smoke.1770519994 | Dec 27 12:44:26 PM PST 23 | Dec 27 12:45:04 PM PST 23 | 1668896820 ps | ||
T822 | /workspace/coverage/default/7.sram_ctrl_lc_escalation.265485374 | Dec 27 12:44:47 PM PST 23 | Dec 27 12:46:04 PM PST 23 | 22454217295 ps | ||
T823 | /workspace/coverage/default/35.sram_ctrl_ram_cfg.3496124005 | Dec 27 12:45:34 PM PST 23 | Dec 27 12:45:48 PM PST 23 | 1410181653 ps | ||
T824 | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4240601842 | Dec 27 12:44:59 PM PST 23 | Dec 27 12:46:21 PM PST 23 | 3530775394 ps | ||
T825 | /workspace/coverage/default/15.sram_ctrl_mem_walk.1643764842 | Dec 27 12:44:41 PM PST 23 | Dec 27 12:48:59 PM PST 23 | 21899768686 ps | ||
T826 | /workspace/coverage/default/28.sram_ctrl_multiple_keys.1716781796 | Dec 27 12:44:59 PM PST 23 | Dec 27 12:53:43 PM PST 23 | 71604118430 ps | ||
T827 | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.977352368 | Dec 27 12:44:57 PM PST 23 | Dec 27 12:50:11 PM PST 23 | 9067759256 ps | ||
T828 | /workspace/coverage/default/45.sram_ctrl_mem_walk.429298072 | Dec 27 12:45:30 PM PST 23 | Dec 27 12:49:45 PM PST 23 | 20737023000 ps | ||
T829 | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2867810163 | Dec 27 12:46:59 PM PST 23 | Dec 27 12:47:24 PM PST 23 | 4800665843 ps | ||
T830 | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2550197031 | Dec 27 12:44:18 PM PST 23 | Dec 27 12:54:42 PM PST 23 | 10913207901 ps | ||
T831 | /workspace/coverage/default/16.sram_ctrl_mem_walk.4014349050 | Dec 27 12:44:34 PM PST 23 | Dec 27 12:49:46 PM PST 23 | 42165350815 ps | ||
T832 | /workspace/coverage/default/36.sram_ctrl_smoke.4184452375 | Dec 27 12:45:43 PM PST 23 | Dec 27 12:47:08 PM PST 23 | 2408524716 ps | ||
T833 | /workspace/coverage/default/4.sram_ctrl_smoke.533094210 | Dec 27 12:44:51 PM PST 23 | Dec 27 12:46:40 PM PST 23 | 9587080145 ps | ||
T834 | /workspace/coverage/default/46.sram_ctrl_smoke.3206819795 | Dec 27 12:45:21 PM PST 23 | Dec 27 12:46:12 PM PST 23 | 1814304192 ps | ||
T835 | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.767820603 | Dec 27 12:45:22 PM PST 23 | Dec 27 12:48:46 PM PST 23 | 12385434020 ps | ||
T836 | /workspace/coverage/default/7.sram_ctrl_executable.791706312 | Dec 27 12:44:49 PM PST 23 | Dec 27 12:56:59 PM PST 23 | 9806933750 ps | ||
T837 | /workspace/coverage/default/40.sram_ctrl_ram_cfg.4086858169 | Dec 27 12:45:17 PM PST 23 | Dec 27 12:45:30 PM PST 23 | 676839221 ps | ||
T838 | /workspace/coverage/default/33.sram_ctrl_mem_walk.4039038805 | Dec 27 12:45:36 PM PST 23 | Dec 27 12:50:14 PM PST 23 | 14224765217 ps | ||
T839 | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1586274918 | Dec 27 12:45:43 PM PST 23 | Dec 27 12:52:17 PM PST 23 | 32490741986 ps | ||
T840 | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1534621921 | Dec 27 12:44:50 PM PST 23 | Dec 27 12:48:45 PM PST 23 | 5731346914 ps | ||
T841 | /workspace/coverage/default/19.sram_ctrl_partial_access.2880547747 | Dec 27 12:44:41 PM PST 23 | Dec 27 12:46:25 PM PST 23 | 2065231167 ps | ||
T842 | /workspace/coverage/default/22.sram_ctrl_executable.1945458186 | Dec 27 12:45:08 PM PST 23 | Dec 27 12:52:52 PM PST 23 | 36003588347 ps | ||
T843 | /workspace/coverage/default/33.sram_ctrl_multiple_keys.3552076039 | Dec 27 12:45:17 PM PST 23 | Dec 27 12:57:33 PM PST 23 | 68518002186 ps | ||
T844 | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1662497597 | Dec 27 12:45:40 PM PST 23 | Dec 27 01:23:41 PM PST 23 | 318046069 ps | ||
T845 | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1203103023 | Dec 27 12:45:10 PM PST 23 | Dec 27 12:58:44 PM PST 23 | 30311419806 ps | ||
T846 | /workspace/coverage/default/31.sram_ctrl_alert_test.1993772903 | Dec 27 12:45:32 PM PST 23 | Dec 27 12:45:41 PM PST 23 | 13959264 ps | ||
T847 | /workspace/coverage/default/23.sram_ctrl_multiple_keys.1011571376 | Dec 27 12:44:50 PM PST 23 | Dec 27 12:56:32 PM PST 23 | 29368276446 ps | ||
T848 | /workspace/coverage/default/4.sram_ctrl_bijection.2699322184 | Dec 27 12:45:07 PM PST 23 | Dec 27 12:56:33 PM PST 23 | 43293133287 ps | ||
T849 | /workspace/coverage/default/35.sram_ctrl_smoke.3948318098 | Dec 27 12:45:33 PM PST 23 | Dec 27 12:46:01 PM PST 23 | 1900152752 ps | ||
T850 | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.597913719 | Dec 27 12:45:26 PM PST 23 | Dec 27 12:46:50 PM PST 23 | 9149109453 ps | ||
T851 | /workspace/coverage/default/39.sram_ctrl_partial_access.433889923 | Dec 27 12:45:17 PM PST 23 | Dec 27 12:45:56 PM PST 23 | 11276392668 ps | ||
T852 | /workspace/coverage/default/10.sram_ctrl_max_throughput.712016104 | Dec 27 12:44:46 PM PST 23 | Dec 27 12:45:22 PM PST 23 | 2826553571 ps | ||
T853 | /workspace/coverage/default/36.sram_ctrl_multiple_keys.1733175862 | Dec 27 12:45:10 PM PST 23 | Dec 27 12:50:11 PM PST 23 | 40730044525 ps | ||
T854 | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4288848365 | Dec 27 12:44:29 PM PST 23 | Dec 27 12:46:20 PM PST 23 | 3136279267 ps | ||
T855 | /workspace/coverage/default/31.sram_ctrl_ram_cfg.750526869 | Dec 27 12:45:03 PM PST 23 | Dec 27 12:45:15 PM PST 23 | 362376093 ps | ||
T856 | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1175725206 | Dec 27 12:44:55 PM PST 23 | Dec 27 12:49:50 PM PST 23 | 13048039264 ps | ||
T857 | /workspace/coverage/default/26.sram_ctrl_max_throughput.1228664076 | Dec 27 12:44:47 PM PST 23 | Dec 27 12:46:25 PM PST 23 | 1561621494 ps | ||
T858 | /workspace/coverage/default/31.sram_ctrl_stress_all.3525492016 | Dec 27 12:45:41 PM PST 23 | Dec 27 01:58:54 PM PST 23 | 587135004215 ps | ||
T859 | /workspace/coverage/default/46.sram_ctrl_regwen.1172112073 | Dec 27 12:45:18 PM PST 23 | Dec 27 12:53:21 PM PST 23 | 66063614097 ps | ||
T860 | /workspace/coverage/default/27.sram_ctrl_regwen.192120421 | Dec 27 12:44:56 PM PST 23 | Dec 27 12:58:12 PM PST 23 | 3373675764 ps | ||
T861 | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4147087387 | Dec 27 12:44:58 PM PST 23 | Dec 27 01:29:02 PM PST 23 | 2890469433 ps | ||
T862 | /workspace/coverage/default/9.sram_ctrl_executable.1010924123 | Dec 27 12:44:58 PM PST 23 | Dec 27 12:46:20 PM PST 23 | 2584335473 ps | ||
T863 | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3790193245 | Dec 27 12:45:43 PM PST 23 | Dec 27 12:47:05 PM PST 23 | 10624712717 ps | ||
T864 | /workspace/coverage/default/45.sram_ctrl_partial_access.3785614307 | Dec 27 12:45:47 PM PST 23 | Dec 27 12:46:18 PM PST 23 | 990069864 ps | ||
T865 | /workspace/coverage/default/49.sram_ctrl_regwen.873782492 | Dec 27 12:45:21 PM PST 23 | Dec 27 12:57:58 PM PST 23 | 15403370172 ps | ||
T866 | /workspace/coverage/default/34.sram_ctrl_multiple_keys.217001312 | Dec 27 12:45:10 PM PST 23 | Dec 27 12:46:15 PM PST 23 | 2483507201 ps | ||
T867 | /workspace/coverage/default/17.sram_ctrl_max_throughput.1199312218 | Dec 27 12:44:51 PM PST 23 | Dec 27 12:46:10 PM PST 23 | 803858285 ps | ||
T868 | /workspace/coverage/default/0.sram_ctrl_stress_all.1107471384 | Dec 27 12:44:54 PM PST 23 | Dec 27 02:25:27 PM PST 23 | 188928194423 ps | ||
T869 | /workspace/coverage/default/37.sram_ctrl_mem_walk.2084188023 | Dec 27 12:45:54 PM PST 23 | Dec 27 12:48:03 PM PST 23 | 3347966749 ps | ||
T870 | /workspace/coverage/default/18.sram_ctrl_max_throughput.3096425567 | Dec 27 12:44:58 PM PST 23 | Dec 27 12:47:14 PM PST 23 | 806202211 ps | ||
T871 | /workspace/coverage/default/24.sram_ctrl_regwen.302114974 | Dec 27 12:44:42 PM PST 23 | Dec 27 12:48:50 PM PST 23 | 936551229 ps | ||
T872 | /workspace/coverage/default/24.sram_ctrl_multiple_keys.2934730606 | Dec 27 12:44:45 PM PST 23 | Dec 27 12:57:56 PM PST 23 | 17851633839 ps | ||
T873 | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.321350068 | Dec 27 12:45:20 PM PST 23 | Dec 27 12:59:36 PM PST 23 | 11016878859 ps | ||
T874 | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2192778118 | Dec 27 12:44:38 PM PST 23 | Dec 27 12:46:09 PM PST 23 | 16348782481 ps | ||
T875 | /workspace/coverage/default/27.sram_ctrl_partial_access.2962019001 | Dec 27 12:44:56 PM PST 23 | Dec 27 12:45:40 PM PST 23 | 903187762 ps | ||
T876 | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1059907068 | Dec 27 12:44:33 PM PST 23 | Dec 27 12:49:39 PM PST 23 | 4350054532 ps | ||
T877 | /workspace/coverage/default/5.sram_ctrl_bijection.4095825685 | Dec 27 12:44:33 PM PST 23 | Dec 27 01:18:25 PM PST 23 | 488788494690 ps | ||
T878 | /workspace/coverage/default/2.sram_ctrl_partial_access.2922548991 | Dec 27 12:44:10 PM PST 23 | Dec 27 12:44:50 PM PST 23 | 582695159 ps | ||
T879 | /workspace/coverage/default/10.sram_ctrl_lc_escalation.1087610300 | Dec 27 12:44:39 PM PST 23 | Dec 27 12:46:21 PM PST 23 | 35406121419 ps | ||
T880 | /workspace/coverage/default/7.sram_ctrl_partial_access.2761628136 | Dec 27 12:44:38 PM PST 23 | Dec 27 12:45:09 PM PST 23 | 4593709733 ps | ||
T881 | /workspace/coverage/default/40.sram_ctrl_mem_walk.3180939990 | Dec 27 12:45:19 PM PST 23 | Dec 27 12:47:31 PM PST 23 | 3953426601 ps | ||
T882 | /workspace/coverage/default/10.sram_ctrl_alert_test.1400246347 | Dec 27 12:44:51 PM PST 23 | Dec 27 12:44:58 PM PST 23 | 11015436 ps | ||
T883 | /workspace/coverage/default/16.sram_ctrl_partial_access.3240563159 | Dec 27 12:44:23 PM PST 23 | Dec 27 12:46:37 PM PST 23 | 1774257813 ps | ||
T884 | /workspace/coverage/default/12.sram_ctrl_ram_cfg.3479914012 | Dec 27 12:44:26 PM PST 23 | Dec 27 12:44:41 PM PST 23 | 682203554 ps | ||
T885 | /workspace/coverage/default/47.sram_ctrl_smoke.1306045703 | Dec 27 12:45:49 PM PST 23 | Dec 27 12:47:45 PM PST 23 | 5337915907 ps | ||
T886 | /workspace/coverage/default/39.sram_ctrl_regwen.950674122 | Dec 27 12:45:48 PM PST 23 | Dec 27 01:13:31 PM PST 23 | 84695700053 ps | ||
T887 | /workspace/coverage/default/22.sram_ctrl_smoke.3785099976 | Dec 27 12:44:29 PM PST 23 | Dec 27 12:44:46 PM PST 23 | 411453230 ps | ||
T888 | /workspace/coverage/default/32.sram_ctrl_partial_access.510300857 | Dec 27 12:45:27 PM PST 23 | Dec 27 12:46:02 PM PST 23 | 5623223234 ps | ||
T889 | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1903743818 | Dec 27 12:45:36 PM PST 23 | Dec 27 12:47:01 PM PST 23 | 6720168610 ps | ||
T890 | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1181934150 | Dec 27 12:45:08 PM PST 23 | Dec 27 12:47:36 PM PST 23 | 1098062625 ps | ||
T891 | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.508502940 | Dec 27 12:44:32 PM PST 23 | Dec 27 12:49:28 PM PST 23 | 17307056090 ps | ||
T892 | /workspace/coverage/default/6.sram_ctrl_smoke.864288689 | Dec 27 12:44:13 PM PST 23 | Dec 27 12:46:34 PM PST 23 | 1325593314 ps | ||
T893 | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3954096053 | Dec 27 12:45:14 PM PST 23 | Dec 27 01:06:02 PM PST 23 | 9100030000 ps | ||
T81 | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2043656055 | Dec 27 12:44:57 PM PST 23 | Dec 27 12:47:17 PM PST 23 | 1570839520 ps | ||
T894 | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4070987501 | Dec 27 12:45:33 PM PST 23 | Dec 27 12:49:53 PM PST 23 | 182546918886 ps | ||
T895 | /workspace/coverage/default/10.sram_ctrl_ram_cfg.1494718447 | Dec 27 12:44:50 PM PST 23 | Dec 27 12:45:10 PM PST 23 | 1357426143 ps | ||
T896 | /workspace/coverage/default/22.sram_ctrl_max_throughput.3971362471 | Dec 27 12:45:13 PM PST 23 | Dec 27 12:46:24 PM PST 23 | 1613930977 ps | ||
T897 | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3509710863 | Dec 27 12:44:13 PM PST 23 | Dec 27 12:45:35 PM PST 23 | 774227648 ps | ||
T898 | /workspace/coverage/default/43.sram_ctrl_regwen.3471178905 | Dec 27 12:45:47 PM PST 23 | Dec 27 01:13:33 PM PST 23 | 69639728419 ps | ||
T899 | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.274385650 | Dec 27 12:45:06 PM PST 23 | Dec 27 12:47:48 PM PST 23 | 791805956 ps | ||
T900 | /workspace/coverage/default/11.sram_ctrl_bijection.1506877909 | Dec 27 12:45:07 PM PST 23 | Dec 27 12:59:15 PM PST 23 | 216460470046 ps | ||
T901 | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3684786581 | Dec 27 12:44:48 PM PST 23 | Dec 27 12:46:06 PM PST 23 | 967547216 ps | ||
T902 | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1200398792 | Dec 27 12:45:02 PM PST 23 | Dec 27 12:49:48 PM PST 23 | 14265841797 ps | ||
T903 | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1580123071 | Dec 27 12:45:18 PM PST 23 | Dec 27 12:47:12 PM PST 23 | 12158102919 ps | ||
T904 | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3059624049 | Dec 27 12:44:49 PM PST 23 | Dec 27 12:51:28 PM PST 23 | 22355104372 ps | ||
T905 | /workspace/coverage/default/30.sram_ctrl_lc_escalation.2497962771 | Dec 27 12:45:04 PM PST 23 | Dec 27 12:46:44 PM PST 23 | 42331828889 ps | ||
T906 | /workspace/coverage/default/11.sram_ctrl_regwen.326509445 | Dec 27 12:44:53 PM PST 23 | Dec 27 12:52:49 PM PST 23 | 7209091477 ps | ||
T907 | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.221807550 | Dec 27 12:45:22 PM PST 23 | Dec 27 02:25:23 PM PST 23 | 19473460139 ps | ||
T908 | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.21686135 | Dec 27 12:45:46 PM PST 23 | Dec 27 12:50:12 PM PST 23 | 54126943405 ps | ||
T38 | /workspace/coverage/default/1.sram_ctrl_sec_cm.566471931 | Dec 27 12:44:22 PM PST 23 | Dec 27 12:44:34 PM PST 23 | 373981015 ps | ||
T909 | /workspace/coverage/default/30.sram_ctrl_mem_walk.2748668659 | Dec 27 12:44:54 PM PST 23 | Dec 27 12:47:36 PM PST 23 | 47143857995 ps | ||
T910 | /workspace/coverage/default/1.sram_ctrl_max_throughput.2005068534 | Dec 27 12:44:11 PM PST 23 | Dec 27 12:45:39 PM PST 23 | 2003786358 ps | ||
T911 | /workspace/coverage/default/39.sram_ctrl_smoke.3436357733 | Dec 27 12:45:28 PM PST 23 | Dec 27 12:46:01 PM PST 23 | 3183011089 ps | ||
T912 | /workspace/coverage/default/48.sram_ctrl_stress_all.974253805 | Dec 27 12:45:36 PM PST 23 | Dec 27 01:05:07 PM PST 23 | 32704113574 ps | ||
T913 | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.282163630 | Dec 27 12:45:13 PM PST 23 | Dec 27 01:53:20 PM PST 23 | 1870851671 ps | ||
T914 | /workspace/coverage/default/49.sram_ctrl_max_throughput.171358386 | Dec 27 12:45:28 PM PST 23 | Dec 27 12:47:10 PM PST 23 | 3105013946 ps | ||
T915 | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.677050565 | Dec 27 12:44:31 PM PST 23 | Dec 27 12:45:53 PM PST 23 | 9234258905 ps | ||
T916 | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.468137362 | Dec 27 12:44:39 PM PST 23 | Dec 27 01:16:11 PM PST 23 | 25583152820 ps | ||
T917 | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.167685642 | Dec 27 12:45:39 PM PST 23 | Dec 27 01:21:37 PM PST 23 | 11750231662 ps | ||
T918 | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3934656449 | Dec 27 12:45:07 PM PST 23 | Dec 27 12:47:32 PM PST 23 | 6198534935 ps | ||
T919 | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.289992887 | Dec 27 12:44:42 PM PST 23 | Dec 27 12:49:46 PM PST 23 | 12591376998 ps | ||
T920 | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.755862316 | Dec 27 12:44:41 PM PST 23 | Dec 27 12:46:00 PM PST 23 | 6684416996 ps | ||
T921 | /workspace/coverage/default/19.sram_ctrl_regwen.2736256311 | Dec 27 12:44:32 PM PST 23 | Dec 27 01:03:06 PM PST 23 | 47925554947 ps | ||
T922 | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1922952504 | Dec 27 12:45:10 PM PST 23 | Dec 27 12:46:07 PM PST 23 | 769714776 ps | ||
T923 | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2945612535 | Dec 27 12:44:20 PM PST 23 | Dec 27 12:48:31 PM PST 23 | 86282462941 ps | ||
T924 | /workspace/coverage/default/3.sram_ctrl_mem_walk.2164151390 | Dec 27 12:44:28 PM PST 23 | Dec 27 12:46:38 PM PST 23 | 8232326271 ps | ||
T925 | /workspace/coverage/default/16.sram_ctrl_multiple_keys.96225875 | Dec 27 12:44:37 PM PST 23 | Dec 27 12:55:15 PM PST 23 | 101660545148 ps | ||
T926 | /workspace/coverage/default/15.sram_ctrl_ram_cfg.160852802 | Dec 27 12:44:56 PM PST 23 | Dec 27 12:45:10 PM PST 23 | 357593929 ps | ||
T927 | /workspace/coverage/default/3.sram_ctrl_executable.3808657840 | Dec 27 12:44:25 PM PST 23 | Dec 27 12:58:37 PM PST 23 | 33168981047 ps | ||
T928 | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4213230422 | Dec 27 12:45:39 PM PST 23 | Dec 27 12:48:40 PM PST 23 | 5128054497 ps | ||
T929 | /workspace/coverage/default/20.sram_ctrl_mem_walk.168376192 | Dec 27 12:44:41 PM PST 23 | Dec 27 12:47:01 PM PST 23 | 25489279550 ps | ||
T930 | /workspace/coverage/default/40.sram_ctrl_regwen.3327887488 | Dec 27 12:45:18 PM PST 23 | Dec 27 12:54:09 PM PST 23 | 36848155912 ps | ||
T931 | /workspace/coverage/default/34.sram_ctrl_max_throughput.3681649507 | Dec 27 12:45:34 PM PST 23 | Dec 27 12:48:17 PM PST 23 | 774369320 ps | ||
T932 | /workspace/coverage/default/1.sram_ctrl_mem_walk.198220058 | Dec 27 12:44:33 PM PST 23 | Dec 27 12:48:49 PM PST 23 | 9164136455 ps | ||
T933 | /workspace/coverage/default/44.sram_ctrl_max_throughput.4092613249 | Dec 27 12:45:24 PM PST 23 | Dec 27 12:46:51 PM PST 23 | 750840266 ps | ||
T934 | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3510343169 | Dec 27 12:45:37 PM PST 23 | Dec 27 12:50:49 PM PST 23 | 7882799365 ps | ||
T935 | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1855955531 | Dec 27 12:45:18 PM PST 23 | Dec 27 12:57:47 PM PST 23 | 7661089581 ps | ||
T936 | /workspace/coverage/default/5.sram_ctrl_alert_test.180194423 | Dec 27 12:44:23 PM PST 23 | Dec 27 12:44:33 PM PST 23 | 22692185 ps | ||
T937 | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1561180821 | Dec 27 12:44:42 PM PST 23 | Dec 27 12:46:55 PM PST 23 | 3104923835 ps | ||
T938 | /workspace/coverage/default/15.sram_ctrl_multiple_keys.2195466231 | Dec 27 12:44:17 PM PST 23 | Dec 27 01:05:11 PM PST 23 | 126881651373 ps | ||
T939 | /workspace/coverage/default/11.sram_ctrl_partial_access.1026716887 | Dec 27 12:44:32 PM PST 23 | Dec 27 12:45:04 PM PST 23 | 1694626085 ps | ||
T940 | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3761732625 | Dec 27 12:44:47 PM PST 23 | Dec 27 12:47:03 PM PST 23 | 3102529452 ps | ||
T941 | /workspace/coverage/default/42.sram_ctrl_bijection.3083258054 | Dec 27 12:45:21 PM PST 23 | Dec 27 01:04:00 PM PST 23 | 72797450494 ps | ||
T942 | /workspace/coverage/default/43.sram_ctrl_mem_walk.332001899 | Dec 27 12:45:21 PM PST 23 | Dec 27 12:49:37 PM PST 23 | 4065452913 ps | ||
T943 | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1951663735 | Dec 27 12:44:42 PM PST 23 | Dec 27 12:47:18 PM PST 23 | 13009534477 ps | ||
T944 | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1182528040 | Dec 27 12:45:04 PM PST 23 | Dec 27 01:29:39 PM PST 23 | 1484786452 ps | ||
T945 | /workspace/coverage/default/44.sram_ctrl_mem_walk.1154932788 | Dec 27 12:45:44 PM PST 23 | Dec 27 12:51:10 PM PST 23 | 86003687462 ps | ||
T946 | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4213933722 | Dec 27 12:44:14 PM PST 23 | Dec 27 12:46:53 PM PST 23 | 18280987910 ps | ||
T947 | /workspace/coverage/default/9.sram_ctrl_smoke.1617725538 | Dec 27 12:44:39 PM PST 23 | Dec 27 12:46:51 PM PST 23 | 7136848944 ps | ||
T948 | /workspace/coverage/default/17.sram_ctrl_alert_test.205645066 | Dec 27 12:44:25 PM PST 23 | Dec 27 12:44:35 PM PST 23 | 43819145 ps | ||
T949 | /workspace/coverage/default/21.sram_ctrl_executable.3056202185 | Dec 27 12:44:59 PM PST 23 | Dec 27 12:51:39 PM PST 23 | 49346898495 ps | ||
T950 | /workspace/coverage/default/31.sram_ctrl_smoke.3523382799 | Dec 27 12:45:01 PM PST 23 | Dec 27 12:46:56 PM PST 23 | 4898626875 ps | ||
T951 | /workspace/coverage/default/6.sram_ctrl_max_throughput.4285206441 | Dec 27 12:44:24 PM PST 23 | Dec 27 12:45:25 PM PST 23 | 1402399778 ps | ||
T952 | /workspace/coverage/default/48.sram_ctrl_smoke.2938076176 | Dec 27 12:45:40 PM PST 23 | Dec 27 12:46:17 PM PST 23 | 845314694 ps | ||
T953 | /workspace/coverage/default/30.sram_ctrl_smoke.2511238734 | Dec 27 12:45:23 PM PST 23 | Dec 27 12:45:55 PM PST 23 | 1420554795 ps | ||
T954 | /workspace/coverage/default/9.sram_ctrl_alert_test.1435121278 | Dec 27 12:44:43 PM PST 23 | Dec 27 12:44:49 PM PST 23 | 14952853 ps | ||
T955 | /workspace/coverage/default/12.sram_ctrl_stress_all.1120270046 | Dec 27 12:44:47 PM PST 23 | Dec 27 02:03:33 PM PST 23 | 683305247494 ps | ||
T956 | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1132084907 | Dec 27 12:44:31 PM PST 23 | Dec 27 12:55:46 PM PST 23 | 20103302492 ps | ||
T957 | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3974781558 | Dec 27 12:44:48 PM PST 23 | Dec 27 12:46:25 PM PST 23 | 3155555260 ps | ||
T958 | /workspace/coverage/default/28.sram_ctrl_mem_walk.4029865834 | Dec 27 12:45:12 PM PST 23 | Dec 27 12:50:13 PM PST 23 | 55080416425 ps | ||
T959 | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3713397957 | Dec 27 12:45:47 PM PST 23 | Dec 27 01:00:47 PM PST 23 | 8997804822 ps | ||
T960 | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1310941948 | Dec 27 12:44:22 PM PST 23 | Dec 27 12:45:48 PM PST 23 | 9422501643 ps | ||
T961 | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3898756100 | Dec 27 12:45:26 PM PST 23 | Dec 27 02:11:32 PM PST 23 | 1776530329 ps | ||
T962 | /workspace/coverage/default/8.sram_ctrl_regwen.2385478695 | Dec 27 12:44:28 PM PST 23 | Dec 27 12:55:06 PM PST 23 | 9175560578 ps | ||
T963 | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.662925771 | Dec 27 12:44:26 PM PST 23 | Dec 27 12:45:46 PM PST 23 | 3702836746 ps | ||
T964 | /workspace/coverage/default/14.sram_ctrl_partial_access.2090254628 | Dec 27 12:44:47 PM PST 23 | Dec 27 12:46:40 PM PST 23 | 895007652 ps | ||
T965 | /workspace/coverage/default/38.sram_ctrl_ram_cfg.1968717061 | Dec 27 12:45:19 PM PST 23 | Dec 27 12:45:35 PM PST 23 | 1411613212 ps | ||
T966 | /workspace/coverage/default/23.sram_ctrl_partial_access.2164554431 | Dec 27 12:44:39 PM PST 23 | Dec 27 12:45:52 PM PST 23 | 1930693118 ps | ||
T967 | /workspace/coverage/default/42.sram_ctrl_max_throughput.2874894870 | Dec 27 12:45:18 PM PST 23 | Dec 27 12:47:45 PM PST 23 | 783040415 ps | ||
T968 | /workspace/coverage/default/8.sram_ctrl_max_throughput.1790806492 | Dec 27 12:44:17 PM PST 23 | Dec 27 12:46:12 PM PST 23 | 3131996199 ps | ||
T969 | /workspace/coverage/default/35.sram_ctrl_stress_all.62822635 | Dec 27 12:45:22 PM PST 23 | Dec 27 01:27:31 PM PST 23 | 1673835839561 ps | ||
T970 | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2214635930 | Dec 27 12:44:21 PM PST 23 | Dec 27 12:47:49 PM PST 23 | 5235395041 ps | ||
T971 | /workspace/coverage/default/33.sram_ctrl_stress_all.3781491889 | Dec 27 12:45:09 PM PST 23 | Dec 27 02:21:39 PM PST 23 | 189035440885 ps | ||
T972 | /workspace/coverage/default/27.sram_ctrl_lc_escalation.272219944 | Dec 27 12:45:11 PM PST 23 | Dec 27 12:47:17 PM PST 23 | 12633452036 ps | ||
T973 | /workspace/coverage/default/20.sram_ctrl_stress_all.446954627 | Dec 27 12:44:54 PM PST 23 | Dec 27 01:28:56 PM PST 23 | 79076575397 ps | ||
T974 | /workspace/coverage/default/17.sram_ctrl_mem_walk.159508466 | Dec 27 12:44:36 PM PST 23 | Dec 27 12:48:46 PM PST 23 | 4027837353 ps | ||
T975 | /workspace/coverage/default/49.sram_ctrl_alert_test.1162924501 | Dec 27 12:45:39 PM PST 23 | Dec 27 12:45:48 PM PST 23 | 34414117 ps | ||
T976 | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2341511762 | Dec 27 12:44:28 PM PST 23 | Dec 27 12:51:42 PM PST 23 | 103433606993 ps | ||
T977 | /workspace/coverage/default/48.sram_ctrl_partial_access.1616694004 | Dec 27 12:45:45 PM PST 23 | Dec 27 12:46:07 PM PST 23 | 1275761448 ps | ||
T978 | /workspace/coverage/default/8.sram_ctrl_lc_escalation.3280419806 | Dec 27 12:44:11 PM PST 23 | Dec 27 12:45:34 PM PST 23 | 11631653585 ps | ||
T979 | /workspace/coverage/default/6.sram_ctrl_stress_all.583640082 | Dec 27 12:44:23 PM PST 23 | Dec 27 01:23:48 PM PST 23 | 471804781973 ps | ||
T980 | /workspace/coverage/default/28.sram_ctrl_partial_access.3311526411 | Dec 27 12:45:13 PM PST 23 | Dec 27 12:46:55 PM PST 23 | 1125466389 ps | ||
T981 | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1934257220 | Dec 27 12:45:39 PM PST 23 | Dec 27 12:50:48 PM PST 23 | 4805220833 ps | ||
T982 | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.585378237 | Dec 27 12:45:28 PM PST 23 | Dec 27 12:49:53 PM PST 23 | 3885469777 ps |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1751399663 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 6582133000 ps |
CPU time | 2774.68 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 01:31:14 PM PST 23 |
Peak memory | 565272 kb |
Host | smart-6634e12d-26d6-4dbf-b359-e00107ef915b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1751399663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1751399663 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.3786283771 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 7292156314 ps |
CPU time | 76.07 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 12:46:23 PM PST 23 |
Peak memory | 202140 kb |
Host | smart-5f8c0b68-b574-4b1d-ad7f-161919feb5f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786283771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.3786283771 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4230837992 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 22010600256 ps |
CPU time | 87.71 seconds |
Started | Dec 27 12:45:43 PM PST 23 |
Finished | Dec 27 12:47:19 PM PST 23 |
Peak memory | 218432 kb |
Host | smart-2a72ad5b-063e-4203-9ee7-e1a7787e604f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230837992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.4230837992 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4117111410 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 348185522 ps |
CPU time | 2.22 seconds |
Started | Dec 27 12:32:44 PM PST 23 |
Finished | Dec 27 12:33:22 PM PST 23 |
Peak memory | 202280 kb |
Host | smart-b8064c0f-aa54-4e50-8080-8b0f2ffdff7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117111410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.4117111410 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.3656620646 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 511786127 ps |
CPU time | 3.07 seconds |
Started | Dec 27 12:44:24 PM PST 23 |
Finished | Dec 27 12:44:36 PM PST 23 |
Peak memory | 221680 kb |
Host | smart-f79b8c5c-ae23-4cec-88d9-8b789da1ead5 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656620646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3656620646 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.1603481622 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 49524132595 ps |
CPU time | 1238.33 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 01:06:30 PM PST 23 |
Peak memory | 372952 kb |
Host | smart-4abf472c-af88-4a15-a528-a6795594dfa3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603481622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1603481622 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1456111259 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 95016763177 ps |
CPU time | 526.65 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:53:29 PM PST 23 |
Peak memory | 202104 kb |
Host | smart-2613f1b8-3b96-4bee-bb34-78c5c7f6dd3c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456111259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.1456111259 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1511769039 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 7390252680 ps |
CPU time | 57.31 seconds |
Started | Dec 27 12:33:01 PM PST 23 |
Finished | Dec 27 12:34:30 PM PST 23 |
Peak memory | 210552 kb |
Host | smart-816151f1-2699-4ae1-91c8-b1ee430213ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511769039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1511769039 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1736425478 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 286777938 ps |
CPU time | 2.46 seconds |
Started | Dec 27 12:32:19 PM PST 23 |
Finished | Dec 27 12:33:04 PM PST 23 |
Peak memory | 202232 kb |
Host | smart-de2fcd7a-2521-42e7-a263-6ffba6307c9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736425478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1736425478 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.3716989585 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 349522659 ps |
CPU time | 5.66 seconds |
Started | Dec 27 12:44:38 PM PST 23 |
Finished | Dec 27 12:44:51 PM PST 23 |
Peak memory | 202316 kb |
Host | smart-15120f8c-2899-4dc5-a18e-4506854cd586 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716989585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3716989585 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.1008414196 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 24692219068 ps |
CPU time | 1880.7 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 01:16:26 PM PST 23 |
Peak memory | 376936 kb |
Host | smart-44c255fb-a68c-4a8a-b337-0173f1c7c9fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008414196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1008414196 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2737192450 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 186762778 ps |
CPU time | 2.19 seconds |
Started | Dec 27 12:34:47 PM PST 23 |
Finished | Dec 27 12:35:10 PM PST 23 |
Peak memory | 202240 kb |
Host | smart-6058f485-a6a5-4b0b-ad94-359590d854d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737192450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2737192450 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.1975069278 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 42793152983 ps |
CPU time | 2336.74 seconds |
Started | Dec 27 12:45:03 PM PST 23 |
Finished | Dec 27 01:24:07 PM PST 23 |
Peak memory | 375864 kb |
Host | smart-36ec1859-7166-4e2c-9137-8ce2c9de9e2c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975069278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.1975069278 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3422000110 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 8728786157 ps |
CPU time | 1303.28 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 01:06:22 PM PST 23 |
Peak memory | 371776 kb |
Host | smart-ea0f50fa-c116-4e9e-a5df-14fd6e536805 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422000110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.3422000110 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.2083685193 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 74892308600 ps |
CPU time | 1102.61 seconds |
Started | Dec 27 12:44:06 PM PST 23 |
Finished | Dec 27 01:02:41 PM PST 23 |
Peak memory | 366676 kb |
Host | smart-d1416b04-a6ac-4fdb-81f7-b9fb83cdc7bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083685193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2083685193 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.954434544 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 12597998 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:44:29 PM PST 23 |
Finished | Dec 27 12:44:38 PM PST 23 |
Peak memory | 201324 kb |
Host | smart-25b19314-25ad-47b9-b806-a8f6a4976c15 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954434544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.954434544 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3033792522 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 224538076 ps |
CPU time | 1.89 seconds |
Started | Dec 27 12:32:12 PM PST 23 |
Finished | Dec 27 12:32:58 PM PST 23 |
Peak memory | 202284 kb |
Host | smart-ab012c1b-3160-4623-9f1f-1883b0e5cfa3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033792522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3033792522 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.472556511 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 734541175 ps |
CPU time | 4.57 seconds |
Started | Dec 27 12:33:13 PM PST 23 |
Finished | Dec 27 12:33:46 PM PST 23 |
Peak memory | 202288 kb |
Host | smart-5b62d7ff-783f-404a-a200-6cf5934b8a3e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472556511 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.472556511 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3256608578 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 687208278 ps |
CPU time | 2.39 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:33:32 PM PST 23 |
Peak memory | 202272 kb |
Host | smart-c1be9da6-19f1-4f10-b510-e1a3959e51a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256608578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.3256608578 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.767638080 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 13439017 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:32:11 PM PST 23 |
Finished | Dec 27 12:32:56 PM PST 23 |
Peak memory | 201248 kb |
Host | smart-67283038-4d57-47cf-9355-bc11d447ef31 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767638080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.767638080 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.5772230 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 152194101 ps |
CPU time | 1.34 seconds |
Started | Dec 27 12:33:29 PM PST 23 |
Finished | Dec 27 12:33:50 PM PST 23 |
Peak memory | 201840 kb |
Host | smart-b078ad59-ce25-4aa3-9377-6ae0ad694a2f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5772230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_csr_bit_bash.5772230 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1185756587 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 64025388 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:32:12 PM PST 23 |
Finished | Dec 27 12:32:57 PM PST 23 |
Peak memory | 201400 kb |
Host | smart-2e690c41-a9b1-4f2e-b8df-131185392070 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185756587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.1185756587 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2867415994 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 356817350 ps |
CPU time | 12.64 seconds |
Started | Dec 27 12:32:17 PM PST 23 |
Finished | Dec 27 12:33:13 PM PST 23 |
Peak memory | 210508 kb |
Host | smart-c226f0bf-38e7-4cb7-b50a-527307e7760b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867415994 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2867415994 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4275085290 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 13779583 ps |
CPU time | 0.61 seconds |
Started | Dec 27 12:32:40 PM PST 23 |
Finished | Dec 27 12:33:18 PM PST 23 |
Peak memory | 201160 kb |
Host | smart-bf965bc0-0857-4980-8ca2-ad2d0690f836 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275085290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.4275085290 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1932395615 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 8043029483 ps |
CPU time | 275.97 seconds |
Started | Dec 27 12:32:41 PM PST 23 |
Finished | Dec 27 12:37:54 PM PST 23 |
Peak memory | 202356 kb |
Host | smart-a330381c-5da2-4e3f-aa3a-7052f3f833a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932395615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1932395615 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.154535019 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 22341519 ps |
CPU time | 0.68 seconds |
Started | Dec 27 12:32:13 PM PST 23 |
Finished | Dec 27 12:32:57 PM PST 23 |
Peak memory | 201908 kb |
Host | smart-78b26e34-8193-4a26-b7d2-55a7f47a7387 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154535019 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.154535019 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2931315104 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 61579579 ps |
CPU time | 2.78 seconds |
Started | Dec 27 12:33:20 PM PST 23 |
Finished | Dec 27 12:33:48 PM PST 23 |
Peak memory | 202332 kb |
Host | smart-49453540-a796-4d24-9a01-35a2e7f4856c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931315104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.2931315104 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1406443083 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 25354693 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:32:30 PM PST 23 |
Finished | Dec 27 12:33:11 PM PST 23 |
Peak memory | 201984 kb |
Host | smart-2f722b3b-f084-4a6b-bed2-a4c95df43b86 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406443083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.1406443083 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.521827401 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 59742838 ps |
CPU time | 1.04 seconds |
Started | Dec 27 12:34:17 PM PST 23 |
Finished | Dec 27 12:34:34 PM PST 23 |
Peak memory | 202028 kb |
Host | smart-73072ac2-c4f0-4fd2-9702-b09e83058000 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521827401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.521827401 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.108494335 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 30868961 ps |
CPU time | 0.66 seconds |
Started | Dec 27 12:32:29 PM PST 23 |
Finished | Dec 27 12:33:10 PM PST 23 |
Peak memory | 201976 kb |
Host | smart-c69b7f22-c683-4f0c-ac43-a351a9e1b67b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108494335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_reset.108494335 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4144442484 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 14265712 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:32:24 PM PST 23 |
Finished | Dec 27 12:33:06 PM PST 23 |
Peak memory | 201240 kb |
Host | smart-499c76c0-c432-4a87-abc2-e296d6363fbd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144442484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.4144442484 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2135668668 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 32057283917 ps |
CPU time | 126.71 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:35:37 PM PST 23 |
Peak memory | 202360 kb |
Host | smart-31f19246-eb6d-4953-bfa3-cbaa62dec532 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135668668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.2135668668 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3203042784 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 21706630 ps |
CPU time | 0.71 seconds |
Started | Dec 27 12:33:00 PM PST 23 |
Finished | Dec 27 12:33:33 PM PST 23 |
Peak memory | 202112 kb |
Host | smart-9e3372d4-9417-4358-8970-099da118f92b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203042784 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3203042784 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2966447026 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 144403458 ps |
CPU time | 4.11 seconds |
Started | Dec 27 12:32:15 PM PST 23 |
Finished | Dec 27 12:33:07 PM PST 23 |
Peak memory | 202320 kb |
Host | smart-a8d6a54d-67fe-4bdd-a77f-cc677b78c346 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966447026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2966447026 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2671045425 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 896781883 ps |
CPU time | 2.07 seconds |
Started | Dec 27 12:32:54 PM PST 23 |
Finished | Dec 27 12:33:30 PM PST 23 |
Peak memory | 202308 kb |
Host | smart-89139d05-d43f-46a3-813b-5775f6e306b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671045425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.2671045425 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2815456430 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 360020982 ps |
CPU time | 13.32 seconds |
Started | Dec 27 12:33:05 PM PST 23 |
Finished | Dec 27 12:33:50 PM PST 23 |
Peak memory | 210652 kb |
Host | smart-22971673-8b4f-44a6-be09-0130c74c25ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815456430 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2815456430 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3180797406 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 14591271 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:32:40 PM PST 23 |
Finished | Dec 27 12:33:18 PM PST 23 |
Peak memory | 202176 kb |
Host | smart-9f0a897c-dfe4-46c7-b1a2-58353d0d0b0d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180797406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.3180797406 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.505985397 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 15784762328 ps |
CPU time | 61.66 seconds |
Started | Dec 27 12:33:12 PM PST 23 |
Finished | Dec 27 12:34:43 PM PST 23 |
Peak memory | 210552 kb |
Host | smart-12bb3e11-e804-4a96-9104-a8659d38b334 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505985397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.505985397 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.759831694 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 13674971 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:33:21 PM PST 23 |
Finished | Dec 27 12:33:47 PM PST 23 |
Peak memory | 202072 kb |
Host | smart-aff052aa-32ee-44f3-9e16-cb983adbf238 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759831694 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.759831694 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1769728108 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 466791040 ps |
CPU time | 4.14 seconds |
Started | Dec 27 12:32:30 PM PST 23 |
Finished | Dec 27 12:33:14 PM PST 23 |
Peak memory | 202408 kb |
Host | smart-659c2763-64bd-4922-a30a-238e1cfd7a85 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769728108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.1769728108 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3479260496 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 99457788 ps |
CPU time | 1.56 seconds |
Started | Dec 27 12:32:41 PM PST 23 |
Finished | Dec 27 12:33:20 PM PST 23 |
Peak memory | 210500 kb |
Host | smart-4b2b55db-9ca7-4ba1-a2b2-a44111eb6f7d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479260496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.3479260496 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1996999048 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 1547091478 ps |
CPU time | 4.8 seconds |
Started | Dec 27 12:33:11 PM PST 23 |
Finished | Dec 27 12:33:46 PM PST 23 |
Peak memory | 202436 kb |
Host | smart-75484a28-4e61-4c04-b540-96d5ff436de6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996999048 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1996999048 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3959133574 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 30588138 ps |
CPU time | 0.61 seconds |
Started | Dec 27 12:32:52 PM PST 23 |
Finished | Dec 27 12:33:34 PM PST 23 |
Peak memory | 201984 kb |
Host | smart-f3f749f7-4181-42c3-89c5-bfce34362d10 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959133574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.3959133574 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.443064663 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 87895665384 ps |
CPU time | 282.45 seconds |
Started | Dec 27 12:33:10 PM PST 23 |
Finished | Dec 27 12:38:23 PM PST 23 |
Peak memory | 202364 kb |
Host | smart-cab4005e-3c78-4094-9b1d-d2b577bd7f5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443064663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.443064663 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1627277896 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 33128468 ps |
CPU time | 0.72 seconds |
Started | Dec 27 12:35:09 PM PST 23 |
Finished | Dec 27 12:35:27 PM PST 23 |
Peak memory | 202104 kb |
Host | smart-e134ad19-94a3-422c-860b-d23711622b55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627277896 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1627277896 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4160760271 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 68593785 ps |
CPU time | 1.99 seconds |
Started | Dec 27 12:33:01 PM PST 23 |
Finished | Dec 27 12:33:36 PM PST 23 |
Peak memory | 202436 kb |
Host | smart-5fb1c97c-bcdf-41ff-b26a-288e60eea63f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160760271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.4160760271 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2664416328 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 117461030 ps |
CPU time | 1.5 seconds |
Started | Dec 27 12:33:07 PM PST 23 |
Finished | Dec 27 12:33:40 PM PST 23 |
Peak memory | 202348 kb |
Host | smart-42009dff-b86f-4ed6-b742-9f32454d384f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664416328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.2664416328 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1588475056 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 789220422 ps |
CPU time | 12.98 seconds |
Started | Dec 27 12:32:53 PM PST 23 |
Finished | Dec 27 12:33:40 PM PST 23 |
Peak memory | 210460 kb |
Host | smart-985bd2fc-4e0e-4d82-a859-d40c513e9d1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588475056 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1588475056 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3582402566 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 14208902 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:33:09 PM PST 23 |
Finished | Dec 27 12:33:40 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-3d64cde0-9bd0-4458-afc8-ee2f8db67f5d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582402566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.3582402566 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3154593471 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 29510113991 ps |
CPU time | 269.19 seconds |
Started | Dec 27 12:32:43 PM PST 23 |
Finished | Dec 27 12:37:49 PM PST 23 |
Peak memory | 202440 kb |
Host | smart-64f1a9cf-8922-436e-ab01-f8c65d87c7ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154593471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.3154593471 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3393420944 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 16183305 ps |
CPU time | 0.69 seconds |
Started | Dec 27 12:33:42 PM PST 23 |
Finished | Dec 27 12:33:58 PM PST 23 |
Peak memory | 202080 kb |
Host | smart-ed0aa28e-cfa7-450d-912a-29d165707fc2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393420944 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3393420944 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.823918461 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 71740663 ps |
CPU time | 2.12 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:33:32 PM PST 23 |
Peak memory | 202284 kb |
Host | smart-bb85cefc-b7e1-4c2e-8cf2-6c0fa4263179 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823918461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.823918461 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2930537233 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 139916886 ps |
CPU time | 1.51 seconds |
Started | Dec 27 12:32:56 PM PST 23 |
Finished | Dec 27 12:33:31 PM PST 23 |
Peak memory | 202324 kb |
Host | smart-6c6bba22-efb4-4e85-a1ac-51d2e7834e67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930537233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.2930537233 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1394235345 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 1436658160 ps |
CPU time | 13.04 seconds |
Started | Dec 27 12:33:23 PM PST 23 |
Finished | Dec 27 12:34:00 PM PST 23 |
Peak memory | 210600 kb |
Host | smart-5941ca00-86a7-42f9-b3d9-85630045a541 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394235345 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1394235345 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3882171617 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 20372792 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:32:35 PM PST 23 |
Finished | Dec 27 12:33:15 PM PST 23 |
Peak memory | 201188 kb |
Host | smart-cd92503b-1c85-443a-8984-0110cf96cb3a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882171617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.3882171617 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2026579507 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 3799238116 ps |
CPU time | 141.49 seconds |
Started | Dec 27 12:32:39 PM PST 23 |
Finished | Dec 27 12:35:39 PM PST 23 |
Peak memory | 202424 kb |
Host | smart-07399e22-3c8e-4722-93eb-f3bffefa5871 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026579507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2026579507 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2516140501 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 20362818 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:32:53 PM PST 23 |
Finished | Dec 27 12:33:28 PM PST 23 |
Peak memory | 201960 kb |
Host | smart-2cb3ddb4-2014-47dc-8686-dc4d2b5082a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516140501 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2516140501 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3003578946 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 582151528 ps |
CPU time | 3.58 seconds |
Started | Dec 27 12:32:54 PM PST 23 |
Finished | Dec 27 12:33:32 PM PST 23 |
Peak memory | 202312 kb |
Host | smart-36c71e32-e4ab-4afb-8161-fafefd70c8e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003578946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3003578946 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1776462894 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 289152891 ps |
CPU time | 1.5 seconds |
Started | Dec 27 12:32:19 PM PST 23 |
Finished | Dec 27 12:33:03 PM PST 23 |
Peak memory | 202476 kb |
Host | smart-b2b0fa4f-8cc0-4437-87b1-043cb03858c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776462894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.1776462894 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.217484765 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 361894251 ps |
CPU time | 12.88 seconds |
Started | Dec 27 12:33:44 PM PST 23 |
Finished | Dec 27 12:34:12 PM PST 23 |
Peak memory | 210492 kb |
Host | smart-09bc3df0-8683-4310-87d9-b5e9cbd2c538 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217484765 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.217484765 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3797808836 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 47066374 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:33:10 PM PST 23 |
Finished | Dec 27 12:33:41 PM PST 23 |
Peak memory | 201240 kb |
Host | smart-64f3db07-aa01-46a8-94ea-8b02c535ea4f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797808836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.3797808836 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1024652423 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 26410429786 ps |
CPU time | 51.72 seconds |
Started | Dec 27 12:32:19 PM PST 23 |
Finished | Dec 27 12:33:54 PM PST 23 |
Peak memory | 202412 kb |
Host | smart-336d201f-f7e8-486c-a88c-fea5db7ca1ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024652423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1024652423 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.612463002 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 33865205 ps |
CPU time | 0.69 seconds |
Started | Dec 27 12:33:16 PM PST 23 |
Finished | Dec 27 12:33:45 PM PST 23 |
Peak memory | 202116 kb |
Host | smart-ee00ca94-eb33-42bb-a368-0b7b40c08484 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612463002 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.612463002 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2767047142 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 77364400 ps |
CPU time | 2.55 seconds |
Started | Dec 27 12:33:13 PM PST 23 |
Finished | Dec 27 12:33:45 PM PST 23 |
Peak memory | 202284 kb |
Host | smart-92751459-f548-4592-a288-3f5737499285 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767047142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.2767047142 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.755657631 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 363487547 ps |
CPU time | 5.11 seconds |
Started | Dec 27 12:33:07 PM PST 23 |
Finished | Dec 27 12:33:44 PM PST 23 |
Peak memory | 210568 kb |
Host | smart-ec2fa180-0f40-450a-9345-1d03714de19d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755657631 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.755657631 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3999886779 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 15780578 ps |
CPU time | 0.66 seconds |
Started | Dec 27 12:33:09 PM PST 23 |
Finished | Dec 27 12:33:40 PM PST 23 |
Peak memory | 202100 kb |
Host | smart-85c6c840-505c-4b87-a4cb-eb2f2297ffe9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999886779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3999886779 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.613162331 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 3879431118 ps |
CPU time | 53.36 seconds |
Started | Dec 27 12:33:22 PM PST 23 |
Finished | Dec 27 12:34:40 PM PST 23 |
Peak memory | 202456 kb |
Host | smart-d62aaaeb-0220-4f86-82ca-ce33e42593fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613162331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.613162331 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2966640109 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 124199300 ps |
CPU time | 0.69 seconds |
Started | Dec 27 12:33:39 PM PST 23 |
Finished | Dec 27 12:33:55 PM PST 23 |
Peak memory | 201832 kb |
Host | smart-dd9a7077-b156-4e02-870b-e39ae5599d18 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966640109 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2966640109 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2211097211 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 36641714 ps |
CPU time | 3.45 seconds |
Started | Dec 27 12:33:11 PM PST 23 |
Finished | Dec 27 12:33:44 PM PST 23 |
Peak memory | 202264 kb |
Host | smart-fe19ed24-e062-4816-bf31-0f39d26948be |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211097211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.2211097211 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4115051370 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 135364500 ps |
CPU time | 1.52 seconds |
Started | Dec 27 12:33:03 PM PST 23 |
Finished | Dec 27 12:33:37 PM PST 23 |
Peak memory | 202276 kb |
Host | smart-017783fe-5fb8-4718-b4f6-50c36009e0c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115051370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.4115051370 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1499555300 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 2838697205 ps |
CPU time | 5.74 seconds |
Started | Dec 27 12:32:38 PM PST 23 |
Finished | Dec 27 12:33:22 PM PST 23 |
Peak memory | 202292 kb |
Host | smart-928391d7-fba0-4b4e-bfa7-abcb38ab3cce |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499555300 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1499555300 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1159248387 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 34498340 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:32:54 PM PST 23 |
Finished | Dec 27 12:33:29 PM PST 23 |
Peak memory | 201388 kb |
Host | smart-065d26bc-15fa-4e72-a08f-2014c9beaed9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159248387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1159248387 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1217446344 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 20145735683 ps |
CPU time | 105.92 seconds |
Started | Dec 27 12:33:10 PM PST 23 |
Finished | Dec 27 12:35:26 PM PST 23 |
Peak memory | 210612 kb |
Host | smart-9172859d-2d34-4a71-978b-0fe58b43bd33 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217446344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1217446344 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4011476609 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 58095345 ps |
CPU time | 0.66 seconds |
Started | Dec 27 12:32:18 PM PST 23 |
Finished | Dec 27 12:33:02 PM PST 23 |
Peak memory | 202036 kb |
Host | smart-ace7bb2e-2bfd-49b9-b3fc-a804758b0f5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011476609 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.4011476609 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1978696704 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 142813006 ps |
CPU time | 4.08 seconds |
Started | Dec 27 12:33:18 PM PST 23 |
Finished | Dec 27 12:33:49 PM PST 23 |
Peak memory | 202328 kb |
Host | smart-be0b8d45-c02e-4b1b-b7a2-13cf801e1492 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978696704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.1978696704 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3706204380 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 2812110300 ps |
CPU time | 5.21 seconds |
Started | Dec 27 12:32:51 PM PST 23 |
Finished | Dec 27 12:33:31 PM PST 23 |
Peak memory | 202404 kb |
Host | smart-535070f8-3b3f-4835-ac10-b95d21e86403 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706204380 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3706204380 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.656278784 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 40913214 ps |
CPU time | 0.66 seconds |
Started | Dec 27 12:32:48 PM PST 23 |
Finished | Dec 27 12:33:24 PM PST 23 |
Peak memory | 201428 kb |
Host | smart-4e88011e-61b8-42a4-88cf-a4e765117f71 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656278784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.656278784 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2679942790 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 27902330 ps |
CPU time | 0.88 seconds |
Started | Dec 27 12:33:00 PM PST 23 |
Finished | Dec 27 12:33:33 PM PST 23 |
Peak memory | 202256 kb |
Host | smart-49be1b98-1b04-433b-a635-e597edc66593 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679942790 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2679942790 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.462260641 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 807519682 ps |
CPU time | 3.85 seconds |
Started | Dec 27 12:32:47 PM PST 23 |
Finished | Dec 27 12:33:26 PM PST 23 |
Peak memory | 202304 kb |
Host | smart-e2a0abae-f721-491f-8989-ad453a46cd76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462260641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.462260641 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.787146997 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 270098740 ps |
CPU time | 2.2 seconds |
Started | Dec 27 12:32:30 PM PST 23 |
Finished | Dec 27 12:33:12 PM PST 23 |
Peak memory | 202256 kb |
Host | smart-50af64c5-41f7-497b-9815-0a611c37d405 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787146997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sram_ctrl_tl_intg_err.787146997 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1511912231 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 360967796 ps |
CPU time | 5.82 seconds |
Started | Dec 27 12:32:24 PM PST 23 |
Finished | Dec 27 12:33:11 PM PST 23 |
Peak memory | 210676 kb |
Host | smart-beea3a22-aa06-49a6-b168-8ec60d9d9cfa |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511912231 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1511912231 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1088957040 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 11644313 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:32:40 PM PST 23 |
Finished | Dec 27 12:33:18 PM PST 23 |
Peak memory | 201248 kb |
Host | smart-fc1dc89b-9a2f-4551-9292-11925e6430e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088957040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.1088957040 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1457569108 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 5824771854 ps |
CPU time | 59.16 seconds |
Started | Dec 27 12:32:53 PM PST 23 |
Finished | Dec 27 12:34:26 PM PST 23 |
Peak memory | 202416 kb |
Host | smart-eace7aa7-8281-4e8f-969e-abd6a7e322cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457569108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1457569108 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.753649946 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 39058304 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:32:56 PM PST 23 |
Finished | Dec 27 12:33:30 PM PST 23 |
Peak memory | 202156 kb |
Host | smart-c344a175-0250-4398-97c6-a820b898a11b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753649946 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.753649946 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.11392502 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 24468440 ps |
CPU time | 1.81 seconds |
Started | Dec 27 12:32:45 PM PST 23 |
Finished | Dec 27 12:33:23 PM PST 23 |
Peak memory | 202320 kb |
Host | smart-6a3b4e55-0be1-455e-9301-92160cc01aa8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11392502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST _SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.11392502 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.735656510 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 361046727 ps |
CPU time | 2.26 seconds |
Started | Dec 27 12:32:34 PM PST 23 |
Finished | Dec 27 12:33:16 PM PST 23 |
Peak memory | 202440 kb |
Host | smart-7dca4380-bf8a-4cba-a6d2-49ad8fb999a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735656510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.sram_ctrl_tl_intg_err.735656510 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3085852140 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1512188299 ps |
CPU time | 6.28 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:33:36 PM PST 23 |
Peak memory | 210572 kb |
Host | smart-d18853c7-a74f-49a5-a6a4-af4c9eff5ccf |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085852140 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3085852140 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1886448693 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 14222315 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:32:17 PM PST 23 |
Finished | Dec 27 12:33:01 PM PST 23 |
Peak memory | 201332 kb |
Host | smart-82bedbb2-b1ae-499d-a36f-bc873f543fec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886448693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.1886448693 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.404924892 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 7548101028 ps |
CPU time | 269.15 seconds |
Started | Dec 27 12:32:51 PM PST 23 |
Finished | Dec 27 12:37:55 PM PST 23 |
Peak memory | 202608 kb |
Host | smart-875b4e0e-c201-4603-9307-95004eaa6a54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404924892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.404924892 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.692359110 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 14523057 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:32:39 PM PST 23 |
Finished | Dec 27 12:33:17 PM PST 23 |
Peak memory | 202148 kb |
Host | smart-fa16f406-551e-474e-8b0d-d91e19062eb8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692359110 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.692359110 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2718191489 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 119725528 ps |
CPU time | 3.4 seconds |
Started | Dec 27 12:32:20 PM PST 23 |
Finished | Dec 27 12:33:06 PM PST 23 |
Peak memory | 202320 kb |
Host | smart-5bf718bd-bfeb-4107-8583-b43791247731 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718191489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.2718191489 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2164711224 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 728179905 ps |
CPU time | 2.39 seconds |
Started | Dec 27 12:32:52 PM PST 23 |
Finished | Dec 27 12:33:29 PM PST 23 |
Peak memory | 202428 kb |
Host | smart-e97e2a7e-5256-4464-9932-4739a5ec11b4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164711224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.2164711224 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.537706320 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 12994196 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:32:50 PM PST 23 |
Finished | Dec 27 12:33:25 PM PST 23 |
Peak memory | 201352 kb |
Host | smart-dcabfb98-3fc6-4cee-99cd-73e66773a5fd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537706320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.537706320 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3233937865 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 498718107 ps |
CPU time | 1.91 seconds |
Started | Dec 27 12:32:08 PM PST 23 |
Finished | Dec 27 12:32:55 PM PST 23 |
Peak memory | 201436 kb |
Host | smart-0806697f-a868-4f65-847f-7d8f9a0920b3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233937865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.3233937865 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2492793021 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 36081502 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:33:31 PM PST 23 |
Peak memory | 202176 kb |
Host | smart-93a8e0ce-46b7-4c34-8498-00dec767f28e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492793021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.2492793021 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1814951675 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 1423167420 ps |
CPU time | 5.37 seconds |
Started | Dec 27 12:32:10 PM PST 23 |
Finished | Dec 27 12:32:59 PM PST 23 |
Peak memory | 202312 kb |
Host | smart-097aa6ad-abab-4133-9a7c-04ebf71d3177 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814951675 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1814951675 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.140076441 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 42308981 ps |
CPU time | 0.61 seconds |
Started | Dec 27 12:32:35 PM PST 23 |
Finished | Dec 27 12:33:15 PM PST 23 |
Peak memory | 201100 kb |
Host | smart-501130f2-78d9-4134-bee5-31665702b3bf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140076441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_csr_rw.140076441 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.950199220 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 14761086314 ps |
CPU time | 61.21 seconds |
Started | Dec 27 12:32:18 PM PST 23 |
Finished | Dec 27 12:34:02 PM PST 23 |
Peak memory | 210608 kb |
Host | smart-0acd293e-3722-4976-95c6-9359804990ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950199220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.950199220 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3905254914 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 42884526 ps |
CPU time | 0.71 seconds |
Started | Dec 27 12:32:22 PM PST 23 |
Finished | Dec 27 12:33:05 PM PST 23 |
Peak memory | 202148 kb |
Host | smart-7bc29777-079d-4279-81ef-2abeb15572ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905254914 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3905254914 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.348664482 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 134899301 ps |
CPU time | 2.15 seconds |
Started | Dec 27 12:32:41 PM PST 23 |
Finished | Dec 27 12:33:20 PM PST 23 |
Peak memory | 202460 kb |
Host | smart-f4d75d05-589d-4f81-812e-b3d3ee9a313c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348664482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.348664482 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.373708116 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 190368209 ps |
CPU time | 1.49 seconds |
Started | Dec 27 12:32:32 PM PST 23 |
Finished | Dec 27 12:33:14 PM PST 23 |
Peak memory | 202308 kb |
Host | smart-1d0d3d60-10b7-465d-aeca-30c50723a739 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373708116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.sram_ctrl_tl_intg_err.373708116 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2573693135 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 28489601 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:32:23 PM PST 23 |
Finished | Dec 27 12:33:05 PM PST 23 |
Peak memory | 202028 kb |
Host | smart-cea745f7-5e29-4790-8a0e-eb069474409c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573693135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.2573693135 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2229261312 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 547882074 ps |
CPU time | 1.29 seconds |
Started | Dec 27 12:32:16 PM PST 23 |
Finished | Dec 27 12:33:01 PM PST 23 |
Peak memory | 202224 kb |
Host | smart-c2978ce9-3c09-4da4-857f-4b31e9a13259 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229261312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.2229261312 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.218113361 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 53400428 ps |
CPU time | 0.66 seconds |
Started | Dec 27 12:32:30 PM PST 23 |
Finished | Dec 27 12:33:10 PM PST 23 |
Peak memory | 201332 kb |
Host | smart-9ce0a195-072a-4dd0-91f8-304ea1fb56c4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218113361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.218113361 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3905479798 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 349139394 ps |
CPU time | 5.92 seconds |
Started | Dec 27 12:32:51 PM PST 23 |
Finished | Dec 27 12:33:31 PM PST 23 |
Peak memory | 202456 kb |
Host | smart-25c00d7b-3943-4a58-a117-d6764c036555 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905479798 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3905479798 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1414604546 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 12528619 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:33:00 PM PST 23 |
Finished | Dec 27 12:33:33 PM PST 23 |
Peak memory | 201200 kb |
Host | smart-efce5b30-1cf0-4333-9852-fa150c6c59fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414604546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.1414604546 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2905726676 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 7224891972 ps |
CPU time | 100.58 seconds |
Started | Dec 27 12:32:20 PM PST 23 |
Finished | Dec 27 12:34:43 PM PST 23 |
Peak memory | 210596 kb |
Host | smart-561e5425-d0c9-41d3-8419-e9f43be68059 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905726676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2905726676 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3565841526 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 14636702 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:33:06 PM PST 23 |
Finished | Dec 27 12:33:39 PM PST 23 |
Peak memory | 201420 kb |
Host | smart-908d6ace-f139-48ca-b8fb-944fea05e6df |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565841526 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3565841526 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2306337286 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 49511657 ps |
CPU time | 1.73 seconds |
Started | Dec 27 12:32:22 PM PST 23 |
Finished | Dec 27 12:33:06 PM PST 23 |
Peak memory | 210628 kb |
Host | smart-f47b6356-1e71-4d8c-8da3-67cd18621db4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306337286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2306337286 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2934123743 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 256482095 ps |
CPU time | 1.45 seconds |
Started | Dec 27 12:32:21 PM PST 23 |
Finished | Dec 27 12:33:05 PM PST 23 |
Peak memory | 202256 kb |
Host | smart-1cdbf438-5ba5-4044-8a31-9221762a3dc2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934123743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.2934123743 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1520341199 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 45555271 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:33:38 PM PST 23 |
Finished | Dec 27 12:33:54 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-766ceede-725c-4696-8a44-e15cc3c4f2ea |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520341199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.1520341199 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3662099092 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 545191837 ps |
CPU time | 1.89 seconds |
Started | Dec 27 12:32:27 PM PST 23 |
Finished | Dec 27 12:33:09 PM PST 23 |
Peak memory | 201880 kb |
Host | smart-eb144d83-c2d4-44f8-9de3-bf94f1e88ac1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662099092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.3662099092 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2310235443 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 20033959 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:32:29 PM PST 23 |
Finished | Dec 27 12:33:10 PM PST 23 |
Peak memory | 201356 kb |
Host | smart-1608ab79-c87b-4ee2-8a28-38d4054c1097 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310235443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.2310235443 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3189569290 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 353973478 ps |
CPU time | 5.94 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:33:36 PM PST 23 |
Peak memory | 210588 kb |
Host | smart-3393a9a2-91bc-4e02-b0aa-5604f8e32ee9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189569290 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3189569290 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.923848394 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 16539087 ps |
CPU time | 0.61 seconds |
Started | Dec 27 12:33:11 PM PST 23 |
Finished | Dec 27 12:33:42 PM PST 23 |
Peak memory | 201204 kb |
Host | smart-212e8ef7-469a-411e-870b-ed5441c405e7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923848394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_csr_rw.923848394 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1680584555 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 7114743846 ps |
CPU time | 261.87 seconds |
Started | Dec 27 12:33:22 PM PST 23 |
Finished | Dec 27 12:38:10 PM PST 23 |
Peak memory | 202516 kb |
Host | smart-3ab4392f-9888-47b7-82dd-8b692f1f592d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680584555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1680584555 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3673287340 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 13194333 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:33:09 PM PST 23 |
Finished | Dec 27 12:33:40 PM PST 23 |
Peak memory | 202052 kb |
Host | smart-336a432c-cb9b-4700-97fe-4a9f4ee142cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673287340 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3673287340 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2324426131 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2763397113 ps |
CPU time | 4.76 seconds |
Started | Dec 27 12:32:56 PM PST 23 |
Finished | Dec 27 12:33:34 PM PST 23 |
Peak memory | 202356 kb |
Host | smart-23508381-76da-4b61-9b5b-ac410e20514d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324426131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.2324426131 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3705539474 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 118775547 ps |
CPU time | 1.45 seconds |
Started | Dec 27 12:33:18 PM PST 23 |
Finished | Dec 27 12:33:46 PM PST 23 |
Peak memory | 202464 kb |
Host | smart-52811b0f-ab50-4698-b61f-8e8627b51310 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705539474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3705539474 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.901727870 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 1452369023 ps |
CPU time | 6.2 seconds |
Started | Dec 27 12:32:51 PM PST 23 |
Finished | Dec 27 12:33:32 PM PST 23 |
Peak memory | 210648 kb |
Host | smart-eec4ec42-3281-4d2b-8455-e08245f31c2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901727870 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.901727870 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2978907607 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 23157864 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:33:02 PM PST 23 |
Finished | Dec 27 12:33:35 PM PST 23 |
Peak memory | 201180 kb |
Host | smart-3a2fbebd-52c5-428b-990f-bde462a46e7c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978907607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.2978907607 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3015034961 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 7046199661 ps |
CPU time | 267.85 seconds |
Started | Dec 27 12:33:18 PM PST 23 |
Finished | Dec 27 12:38:12 PM PST 23 |
Peak memory | 202388 kb |
Host | smart-aaed5b43-538c-48dc-8596-cbb3404408c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015034961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3015034961 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2660920634 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 27112072 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:32:28 PM PST 23 |
Finished | Dec 27 12:33:08 PM PST 23 |
Peak memory | 201956 kb |
Host | smart-30b13463-1a5e-4d6b-b29c-96a177227fef |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660920634 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2660920634 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3256326528 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 277943865 ps |
CPU time | 4.43 seconds |
Started | Dec 27 12:33:03 PM PST 23 |
Finished | Dec 27 12:33:39 PM PST 23 |
Peak memory | 202304 kb |
Host | smart-ddcd0b9e-8fd6-462f-93e0-872533952834 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256326528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.3256326528 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2680226144 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 758999181 ps |
CPU time | 2.64 seconds |
Started | Dec 27 12:32:54 PM PST 23 |
Finished | Dec 27 12:33:31 PM PST 23 |
Peak memory | 202472 kb |
Host | smart-1e374e66-369e-4aee-805e-e60d1e3e523a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680226144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.2680226144 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4076887818 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 1517848392 ps |
CPU time | 6.26 seconds |
Started | Dec 27 12:32:59 PM PST 23 |
Finished | Dec 27 12:33:38 PM PST 23 |
Peak memory | 210536 kb |
Host | smart-9077950c-3d6d-48f0-bf24-a3f234165f4b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076887818 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.4076887818 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2225741145 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 13156529 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:32:37 PM PST 23 |
Finished | Dec 27 12:33:16 PM PST 23 |
Peak memory | 201476 kb |
Host | smart-b62b2093-766c-4304-be47-6fa4a9944f31 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225741145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.2225741145 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4221608006 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 7350897593 ps |
CPU time | 119.02 seconds |
Started | Dec 27 12:32:56 PM PST 23 |
Finished | Dec 27 12:35:28 PM PST 23 |
Peak memory | 202448 kb |
Host | smart-0186ca1d-6ab9-4b8b-ac33-e4390be8ddec |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221608006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.4221608006 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1646147016 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 24853721 ps |
CPU time | 0.73 seconds |
Started | Dec 27 12:32:47 PM PST 23 |
Finished | Dec 27 12:33:23 PM PST 23 |
Peak memory | 201328 kb |
Host | smart-562aef42-1d40-41b4-adbc-ca5140d45f72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646147016 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1646147016 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1954676897 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 187538501 ps |
CPU time | 2.13 seconds |
Started | Dec 27 12:32:40 PM PST 23 |
Finished | Dec 27 12:33:20 PM PST 23 |
Peak memory | 202300 kb |
Host | smart-b629e1b1-f536-4f90-9a60-d4fd47cb92ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954676897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.1954676897 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1408596477 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 360488595 ps |
CPU time | 13.76 seconds |
Started | Dec 27 12:32:48 PM PST 23 |
Finished | Dec 27 12:33:37 PM PST 23 |
Peak memory | 210648 kb |
Host | smart-3c99cbe5-89cd-4a55-8df6-1140cd341716 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408596477 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1408596477 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4090104106 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 21545783 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:32:17 PM PST 23 |
Finished | Dec 27 12:33:01 PM PST 23 |
Peak memory | 202080 kb |
Host | smart-947a646e-6f9a-46e8-b7e9-2e47af0e14ef |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090104106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.4090104106 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2271293893 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 32063988247 ps |
CPU time | 104.23 seconds |
Started | Dec 27 12:33:31 PM PST 23 |
Finished | Dec 27 12:35:34 PM PST 23 |
Peak memory | 202424 kb |
Host | smart-64afb01b-347c-4658-921e-a300ffab071e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271293893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2271293893 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3806343108 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 96880932 ps |
CPU time | 0.75 seconds |
Started | Dec 27 12:32:52 PM PST 23 |
Finished | Dec 27 12:33:28 PM PST 23 |
Peak memory | 202068 kb |
Host | smart-9d7ec69e-2179-4370-8efb-3e2af24342b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806343108 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3806343108 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3159911150 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 40844531 ps |
CPU time | 3.84 seconds |
Started | Dec 27 12:32:13 PM PST 23 |
Finished | Dec 27 12:33:01 PM PST 23 |
Peak memory | 202256 kb |
Host | smart-8e6a0c32-b858-4670-b092-b403969cee99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159911150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.3159911150 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1424881901 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 405468092 ps |
CPU time | 2.23 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:33:33 PM PST 23 |
Peak memory | 202312 kb |
Host | smart-e07b76e8-2421-4269-9125-368b843ae0fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424881901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.1424881901 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1231953789 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 1405642782 ps |
CPU time | 5.83 seconds |
Started | Dec 27 12:32:28 PM PST 23 |
Finished | Dec 27 12:33:13 PM PST 23 |
Peak memory | 202284 kb |
Host | smart-ecb20201-bd55-44ed-b19e-c58f838de0c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231953789 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1231953789 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.721359110 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 33549293 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:33:01 PM PST 23 |
Finished | Dec 27 12:33:34 PM PST 23 |
Peak memory | 201176 kb |
Host | smart-83040a54-0752-4415-9cad-9a74877a01e5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721359110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_csr_rw.721359110 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4070495503 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 7692185489 ps |
CPU time | 137.01 seconds |
Started | Dec 27 12:32:58 PM PST 23 |
Finished | Dec 27 12:35:48 PM PST 23 |
Peak memory | 202400 kb |
Host | smart-54e6e336-85b3-4036-9eb9-fa5a335c9a3b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070495503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.4070495503 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2302359920 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 15742887 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:32:48 PM PST 23 |
Finished | Dec 27 12:33:32 PM PST 23 |
Peak memory | 202064 kb |
Host | smart-95b16389-3347-4394-aaca-16d532bd6c3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302359920 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2302359920 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1549660898 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 85707600 ps |
CPU time | 4.06 seconds |
Started | Dec 27 12:32:57 PM PST 23 |
Finished | Dec 27 12:33:34 PM PST 23 |
Peak memory | 202348 kb |
Host | smart-6bb010dc-964c-4f1c-a6a9-e3a3c7139eac |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549660898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.1549660898 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4269349255 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 295967166 ps |
CPU time | 1.31 seconds |
Started | Dec 27 12:32:39 PM PST 23 |
Finished | Dec 27 12:33:23 PM PST 23 |
Peak memory | 202288 kb |
Host | smart-972332fb-4995-4442-85bb-7e552957726b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269349255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.4269349255 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3091710005 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 354375853 ps |
CPU time | 12.85 seconds |
Started | Dec 27 12:32:58 PM PST 23 |
Finished | Dec 27 12:33:44 PM PST 23 |
Peak memory | 210676 kb |
Host | smart-c60a0229-7f47-4516-87ad-c9b91a82f21e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091710005 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3091710005 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2049394619 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 13106345 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:33:20 PM PST 23 |
Finished | Dec 27 12:33:50 PM PST 23 |
Peak memory | 202124 kb |
Host | smart-34be3bef-4743-4d68-aee4-bd3e7eb06aec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049394619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2049394619 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3637532718 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 29389867227 ps |
CPU time | 107.55 seconds |
Started | Dec 27 12:33:29 PM PST 23 |
Finished | Dec 27 12:35:36 PM PST 23 |
Peak memory | 210620 kb |
Host | smart-4aef383c-a33f-4427-a010-449bc5924e54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637532718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3637532718 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2876257479 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 12252696 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:32:58 PM PST 23 |
Finished | Dec 27 12:33:32 PM PST 23 |
Peak memory | 201856 kb |
Host | smart-20a9e19a-cfd1-4b25-8441-6be9548e6f4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876257479 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2876257479 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.726500161 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 32217652 ps |
CPU time | 2.24 seconds |
Started | Dec 27 12:32:41 PM PST 23 |
Finished | Dec 27 12:33:20 PM PST 23 |
Peak memory | 202416 kb |
Host | smart-196cea3d-a006-46f9-af51-eca288b2f104 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726500161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.726500161 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1603924157 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 35734332388 ps |
CPU time | 899.07 seconds |
Started | Dec 27 12:44:13 PM PST 23 |
Finished | Dec 27 12:59:23 PM PST 23 |
Peak memory | 378696 kb |
Host | smart-4c08affe-94fa-482d-a39d-ff6f0b3cd6d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603924157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.1603924157 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.427792910 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 315595497730 ps |
CPU time | 1862.82 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 01:15:40 PM PST 23 |
Peak memory | 202084 kb |
Host | smart-d77e34cc-1ceb-4d28-8dad-0e675cd9ffa5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427792910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.427792910 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.2441557702 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 745086899 ps |
CPU time | 75.2 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 12:45:48 PM PST 23 |
Peak memory | 316044 kb |
Host | smart-82ca3f31-7399-40c3-9693-196ae84fe8d2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441557702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.2441557702 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4006782653 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 19876301137 ps |
CPU time | 144.14 seconds |
Started | Dec 27 12:44:35 PM PST 23 |
Finished | Dec 27 12:47:07 PM PST 23 |
Peak memory | 214256 kb |
Host | smart-d56d009a-0d96-42a4-8c95-55d845e95611 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006782653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.4006782653 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.67723935 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 55096451611 ps |
CPU time | 303.94 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 12:49:46 PM PST 23 |
Peak memory | 202032 kb |
Host | smart-184b8075-1827-4460-8780-7fc1a7e19d67 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67723935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m em_walk.67723935 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.3585255568 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 31461862731 ps |
CPU time | 1079.22 seconds |
Started | Dec 27 12:44:15 PM PST 23 |
Finished | Dec 27 01:02:26 PM PST 23 |
Peak memory | 377928 kb |
Host | smart-859bd672-b9d8-4c22-b193-d6542631f278 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585255568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.3585255568 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.2089310581 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 832280531 ps |
CPU time | 18.9 seconds |
Started | Dec 27 12:44:15 PM PST 23 |
Finished | Dec 27 12:44:45 PM PST 23 |
Peak memory | 240292 kb |
Host | smart-4106e4f1-ca7e-4c51-9474-972affb9d907 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089310581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.2089310581 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1175725206 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 13048039264 ps |
CPU time | 287.64 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:49:50 PM PST 23 |
Peak memory | 202080 kb |
Host | smart-3f375c67-c131-4d11-b58c-f2348e60c165 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175725206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1175725206 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.745524202 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 1412334986 ps |
CPU time | 13.63 seconds |
Started | Dec 27 12:44:09 PM PST 23 |
Finished | Dec 27 12:44:35 PM PST 23 |
Peak memory | 202340 kb |
Host | smart-346f7e22-ccfa-4f1d-a7e4-b9f9364f99a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745524202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.745524202 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.4185326964 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 3049757090 ps |
CPU time | 91.48 seconds |
Started | Dec 27 12:44:24 PM PST 23 |
Finished | Dec 27 12:46:05 PM PST 23 |
Peak memory | 302236 kb |
Host | smart-a0b612d9-4b75-49ea-bc05-e5033c6e28bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185326964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.4185326964 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3782452828 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 327819750 ps |
CPU time | 2.69 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 12:44:44 PM PST 23 |
Peak memory | 220712 kb |
Host | smart-97398cf1-cb20-467d-ac33-5fdacefa7ee1 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782452828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3782452828 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.804477768 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 3251710913 ps |
CPU time | 32.93 seconds |
Started | Dec 27 12:44:06 PM PST 23 |
Finished | Dec 27 12:44:51 PM PST 23 |
Peak memory | 286360 kb |
Host | smart-42747e36-3caa-4d95-bdd9-fc618b256b4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804477768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.804477768 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.1107471384 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 188928194423 ps |
CPU time | 6024.9 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 02:25:27 PM PST 23 |
Peak memory | 380004 kb |
Host | smart-0150d2c6-3bae-4731-80d6-6a12a716c742 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107471384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.1107471384 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2910753399 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 2555040156 ps |
CPU time | 3941.23 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 01:50:16 PM PST 23 |
Peak memory | 603384 kb |
Host | smart-6c555566-6815-4ba2-8b06-ea0e517d8a9d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2910753399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2910753399 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4212511650 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 15840292879 ps |
CPU time | 283.06 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:49:20 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-49df7566-02c8-4eb7-a472-04c796ad7f86 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212511650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.4212511650 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1829756780 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 15342089041 ps |
CPU time | 99.19 seconds |
Started | Dec 27 12:44:15 PM PST 23 |
Finished | Dec 27 12:46:05 PM PST 23 |
Peak memory | 349264 kb |
Host | smart-0b81df32-6ad6-462b-80f7-72ecf0418fb2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829756780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1829756780 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1557927102 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 41917943382 ps |
CPU time | 1391.93 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 01:08:20 PM PST 23 |
Peak memory | 379928 kb |
Host | smart-cdc52f30-6a13-4cc5-93e9-9f9c80e35943 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557927102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.1557927102 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.979858587 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 50328878 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:44:58 PM PST 23 |
Peak memory | 201736 kb |
Host | smart-1e561b01-2ee8-4a63-bb0c-e8a98c917f35 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979858587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.979858587 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.1405934525 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 124986995244 ps |
CPU time | 1365.34 seconds |
Started | Dec 27 12:44:16 PM PST 23 |
Finished | Dec 27 01:07:13 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-f42ba22f-af72-472d-ae38-4a978bca1766 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405934525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 1405934525 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.3932993101 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 22368973102 ps |
CPU time | 1480.01 seconds |
Started | Dec 27 12:44:40 PM PST 23 |
Finished | Dec 27 01:09:27 PM PST 23 |
Peak memory | 379940 kb |
Host | smart-62cda126-fca2-4003-ba7b-3007971493c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932993101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.3932993101 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.255671855 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 46960665524 ps |
CPU time | 122.04 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:46:36 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-3389c211-16fa-4db1-9731-36f8f4f6c18d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255671855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca lation.255671855 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.2005068534 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 2003786358 ps |
CPU time | 76.88 seconds |
Started | Dec 27 12:44:11 PM PST 23 |
Finished | Dec 27 12:45:39 PM PST 23 |
Peak memory | 334888 kb |
Host | smart-f1433d1d-4bf5-435e-b8cb-9e36496abe1e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005068534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.2005068534 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2192778118 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 16348782481 ps |
CPU time | 80.36 seconds |
Started | Dec 27 12:44:38 PM PST 23 |
Finished | Dec 27 12:46:09 PM PST 23 |
Peak memory | 211540 kb |
Host | smart-68267085-93f5-4cbb-a00e-72f32bbba699 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192778118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.2192778118 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.198220058 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 9164136455 ps |
CPU time | 247.6 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 12:48:49 PM PST 23 |
Peak memory | 202240 kb |
Host | smart-ee4b22f5-cd7e-4b82-8e95-dae753b20727 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198220058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.198220058 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.1963789072 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 23166057780 ps |
CPU time | 651.91 seconds |
Started | Dec 27 12:44:19 PM PST 23 |
Finished | Dec 27 12:55:26 PM PST 23 |
Peak memory | 356184 kb |
Host | smart-9cf1471d-0386-439f-a66a-ad9eac3a242d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963789072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.1963789072 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.3556891403 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 892337130 ps |
CPU time | 169.08 seconds |
Started | Dec 27 12:44:13 PM PST 23 |
Finished | Dec 27 12:47:12 PM PST 23 |
Peak memory | 362368 kb |
Host | smart-dd399c50-0af1-47cd-a37c-7a5096bd31ad |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556891403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.3556891403 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3581108741 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 60329618524 ps |
CPU time | 395.66 seconds |
Started | Dec 27 12:44:10 PM PST 23 |
Finished | Dec 27 12:50:57 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-3d780c87-969a-4b73-ad7d-26c7040a081e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581108741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.3581108741 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.2772812599 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 1346876403 ps |
CPU time | 5.9 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:45:02 PM PST 23 |
Peak memory | 202268 kb |
Host | smart-1f5f89c2-0a4c-4e0e-a3a1-719520dfe609 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772812599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2772812599 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.2610364875 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 22195010192 ps |
CPU time | 2023.19 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 01:18:25 PM PST 23 |
Peak memory | 378928 kb |
Host | smart-b82d2d92-7c17-4b55-bc0e-8eb6b549ce15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610364875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2610364875 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.566471931 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 373981015 ps |
CPU time | 3.38 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:44:34 PM PST 23 |
Peak memory | 220868 kb |
Host | smart-a5fb0670-d1ae-4121-afc9-73c82291fdbe |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566471931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_sec_cm.566471931 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.429038186 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 749255193 ps |
CPU time | 37.08 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 12:45:19 PM PST 23 |
Peak memory | 250152 kb |
Host | smart-3de38d3e-3c77-4452-8f0f-f20c989fcf3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429038186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.429038186 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.1263606587 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 322199082454 ps |
CPU time | 7423.45 seconds |
Started | Dec 27 12:44:14 PM PST 23 |
Finished | Dec 27 02:48:09 PM PST 23 |
Peak memory | 381992 kb |
Host | smart-eec1dbb5-8453-44c2-bf8c-4fe57ec78586 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263606587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1263606587 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1154961165 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 1017723676 ps |
CPU time | 3571.07 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 01:44:44 PM PST 23 |
Peak memory | 690664 kb |
Host | smart-f9623334-d274-4233-989c-11821f78ce18 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1154961165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1154961165 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1447470865 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 2604469353 ps |
CPU time | 167.82 seconds |
Started | Dec 27 12:44:16 PM PST 23 |
Finished | Dec 27 12:47:15 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-f65e148b-78d3-48d8-a03c-92e04c0eb014 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447470865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1447470865 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1561180821 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 3104923835 ps |
CPU time | 127.11 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:46:55 PM PST 23 |
Peak memory | 361632 kb |
Host | smart-78a3e3fe-dbb6-4f22-b764-75a0d0762af0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561180821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1561180821 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1382439679 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 22620619529 ps |
CPU time | 387.96 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 12:51:32 PM PST 23 |
Peak memory | 350548 kb |
Host | smart-fb9e6445-253b-4e08-a273-e6f94ff3e1c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382439679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.1382439679 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.1400246347 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 11015436 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:44:58 PM PST 23 |
Peak memory | 201796 kb |
Host | smart-42de92da-6887-416d-8419-f6a9529af26f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400246347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1400246347 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.547994275 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 37507104962 ps |
CPU time | 1337.36 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 01:07:26 PM PST 23 |
Peak memory | 210216 kb |
Host | smart-eb7e7c9b-1495-4d1e-8fcd-d379061820ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547994275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 547994275 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.2699425511 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 1192232642 ps |
CPU time | 149.33 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:47:32 PM PST 23 |
Peak memory | 372568 kb |
Host | smart-00101a70-9e64-4ce0-9940-92113a157b20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699425511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.2699425511 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.1087610300 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 35406121419 ps |
CPU time | 95.15 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 12:46:21 PM PST 23 |
Peak memory | 210252 kb |
Host | smart-9b6f85a3-37b7-4bdb-992a-318b24971e66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087610300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1087610300 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.712016104 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 2826553571 ps |
CPU time | 30.47 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:45:22 PM PST 23 |
Peak memory | 222392 kb |
Host | smart-d5189bff-d114-4a7a-8910-362e1d85d429 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712016104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.sram_ctrl_max_throughput.712016104 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1360949725 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 10870650907 ps |
CPU time | 79.75 seconds |
Started | Dec 27 12:44:40 PM PST 23 |
Finished | Dec 27 12:46:07 PM PST 23 |
Peak memory | 211392 kb |
Host | smart-fd741b4a-d83f-4cd8-b780-ebdd48de4fca |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360949725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.1360949725 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.2501429590 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 8219269927 ps |
CPU time | 244.64 seconds |
Started | Dec 27 12:45:05 PM PST 23 |
Finished | Dec 27 12:49:16 PM PST 23 |
Peak memory | 202040 kb |
Host | smart-7928ca92-fa89-4fc7-8bc7-8cac3ce67632 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501429590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.2501429590 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.1206070086 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 49543519459 ps |
CPU time | 1606.62 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 01:11:47 PM PST 23 |
Peak memory | 379988 kb |
Host | smart-07c305c7-1be2-4ab1-90c0-762a0bf5304a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206070086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.1206070086 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.1074959898 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 1202544953 ps |
CPU time | 19.75 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 12:45:27 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-aa7eca92-b471-400d-8b7f-a42e765825af |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074959898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.1074959898 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4027638636 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 42431773583 ps |
CPU time | 226.32 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:48:55 PM PST 23 |
Peak memory | 202032 kb |
Host | smart-1703a790-5f2b-44a3-84c7-3deffd08ce80 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027638636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.4027638636 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.1494718447 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 1357426143 ps |
CPU time | 12.9 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:45:10 PM PST 23 |
Peak memory | 202280 kb |
Host | smart-18841128-5549-44c4-b87b-c1458b43e3c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494718447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1494718447 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.3716132079 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 2106047331 ps |
CPU time | 51.81 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:45:49 PM PST 23 |
Peak memory | 266316 kb |
Host | smart-e92909de-241d-4d32-8c99-e6979fbb80fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716132079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3716132079 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.728912308 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 5882196239 ps |
CPU time | 140.59 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:47:36 PM PST 23 |
Peak memory | 373844 kb |
Host | smart-16f5b73b-92d0-4f67-987b-d14e0100605b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728912308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.728912308 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2784151312 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 2226210980 ps |
CPU time | 6044.01 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 02:25:56 PM PST 23 |
Peak memory | 664584 kb |
Host | smart-2ada7f1f-e1df-40d9-97de-0b165e65b75a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2784151312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2784151312 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.199599943 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 8053775941 ps |
CPU time | 255.22 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 12:49:20 PM PST 23 |
Peak memory | 202040 kb |
Host | smart-3364ae0a-672b-4a07-a016-0a43eb24d36a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199599943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_stress_pipeline.199599943 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.762816943 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 1963373763 ps |
CPU time | 31.38 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:45:24 PM PST 23 |
Peak memory | 234732 kb |
Host | smart-cd675e86-2e67-45d7-a928-35413830615f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762816943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.762816943 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3504004981 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 9773043644 ps |
CPU time | 1073.74 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 01:02:36 PM PST 23 |
Peak memory | 371780 kb |
Host | smart-2a9d98d3-177e-49a5-b321-a8f92069d93e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504004981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3504004981 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.218774096 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 14468268 ps |
CPU time | 0.66 seconds |
Started | Dec 27 12:44:17 PM PST 23 |
Finished | Dec 27 12:44:28 PM PST 23 |
Peak memory | 201812 kb |
Host | smart-0edccccf-5266-43f4-901e-c78b900f7235 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218774096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.218774096 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.1506877909 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 216460470046 ps |
CPU time | 841.43 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:59:15 PM PST 23 |
Peak memory | 202068 kb |
Host | smart-e26c984e-25ff-4e64-85a9-8bcc151f7e8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506877909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .1506877909 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1525878916 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 4542697955 ps |
CPU time | 38.73 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:45:27 PM PST 23 |
Peak memory | 202104 kb |
Host | smart-41accfc8-59d3-4a6f-baa9-b63a9466c7b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525878916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1525878916 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.2228126221 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 3052111150 ps |
CPU time | 143.68 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:47:15 PM PST 23 |
Peak memory | 365688 kb |
Host | smart-b41f5600-2c96-490f-ac3a-05064029aeed |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228126221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.2228126221 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1310941948 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 9422501643 ps |
CPU time | 76.95 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:45:48 PM PST 23 |
Peak memory | 211120 kb |
Host | smart-409083f2-945f-4649-9456-2afe99d89d0e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310941948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.1310941948 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.1757929879 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 15658044791 ps |
CPU time | 152.16 seconds |
Started | Dec 27 12:44:16 PM PST 23 |
Finished | Dec 27 12:46:59 PM PST 23 |
Peak memory | 202144 kb |
Host | smart-e4ae2869-7fc1-4afe-b48a-f907fc11d291 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757929879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.1757929879 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.3438430591 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 7521612752 ps |
CPU time | 32.59 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 12:45:40 PM PST 23 |
Peak memory | 202040 kb |
Host | smart-c16f8194-df96-4d5d-a36c-a4bb6f54eb80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438430591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3438430591 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.1026716887 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 1694626085 ps |
CPU time | 22.88 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:45:04 PM PST 23 |
Peak memory | 201924 kb |
Host | smart-ace54bab-bff3-4349-83e7-ed85b1d41959 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026716887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1026716887 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1015660967 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 15037258171 ps |
CPU time | 433.61 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 12:51:49 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-3c9d3c5d-9236-4b6c-9281-90f7b8e981f7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015660967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.1015660967 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.1645678344 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 1403551962 ps |
CPU time | 6.32 seconds |
Started | Dec 27 12:44:09 PM PST 23 |
Finished | Dec 27 12:44:27 PM PST 23 |
Peak memory | 202360 kb |
Host | smart-a2f7300c-645e-4409-830b-49630a9fca2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645678344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1645678344 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.326509445 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 7209091477 ps |
CPU time | 468.69 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:52:49 PM PST 23 |
Peak memory | 374896 kb |
Host | smart-57843556-e4fd-4dc1-a2a1-1211a626606e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326509445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.326509445 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.2306461257 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 778701813 ps |
CPU time | 14.27 seconds |
Started | Dec 27 12:44:37 PM PST 23 |
Finished | Dec 27 12:44:59 PM PST 23 |
Peak memory | 201920 kb |
Host | smart-eeba94b0-0255-4db1-b425-ef3ee61c0819 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306461257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2306461257 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.185404048 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 878525127544 ps |
CPU time | 4535.37 seconds |
Started | Dec 27 12:44:19 PM PST 23 |
Finished | Dec 27 02:00:05 PM PST 23 |
Peak memory | 378996 kb |
Host | smart-fc118d5f-b6fd-4c17-ae6b-db035342c30d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185404048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_stress_all.185404048 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3595954610 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 7654793032 ps |
CPU time | 5301.53 seconds |
Started | Dec 27 12:44:27 PM PST 23 |
Finished | Dec 27 02:12:58 PM PST 23 |
Peak memory | 519256 kb |
Host | smart-16bdfa7a-f23e-4572-b62d-142e57a7adff |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3595954610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3595954610 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3234435449 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 6361662186 ps |
CPU time | 461.22 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 12:52:13 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-9f69e496-181f-4240-87ba-3ba5bada46c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234435449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.3234435449 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.66799103 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 10207150688 ps |
CPU time | 49.54 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:45:27 PM PST 23 |
Peak memory | 269596 kb |
Host | smart-302f92c8-3ee0-409e-b9ce-8bed8b5f38d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66799103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_throughput_w_partial_write.66799103 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3903094393 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 4775474763 ps |
CPU time | 855.28 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 12:58:48 PM PST 23 |
Peak memory | 375852 kb |
Host | smart-cae5ff88-3345-420b-93ff-6691f5458dc2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903094393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.3903094393 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.450502570 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 178480067 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:44:27 PM PST 23 |
Finished | Dec 27 12:44:36 PM PST 23 |
Peak memory | 201724 kb |
Host | smart-acf5a467-5bca-4287-93ab-97c3b767757a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450502570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.450502570 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.2993257929 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 42502926444 ps |
CPU time | 981.54 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 01:01:01 PM PST 23 |
Peak memory | 202068 kb |
Host | smart-2566f7a4-5994-4418-99ad-063a603ceda9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993257929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .2993257929 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.3374923673 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 2978120947 ps |
CPU time | 24.95 seconds |
Started | Dec 27 12:44:20 PM PST 23 |
Finished | Dec 27 12:44:54 PM PST 23 |
Peak memory | 210208 kb |
Host | smart-573ca8b2-b946-4c52-a758-09a6eaa13b2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374923673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.3374923673 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.2931619241 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 796796834 ps |
CPU time | 133.95 seconds |
Started | Dec 27 12:44:21 PM PST 23 |
Finished | Dec 27 12:46:44 PM PST 23 |
Peak memory | 356336 kb |
Host | smart-10c06159-4184-4c8c-bacf-9bab6ebd6b59 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931619241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.2931619241 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.881420637 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 6271206579 ps |
CPU time | 131.69 seconds |
Started | Dec 27 12:44:36 PM PST 23 |
Finished | Dec 27 12:46:55 PM PST 23 |
Peak memory | 211068 kb |
Host | smart-e9f77b4f-4400-41ce-a0cb-7ca6e744f5b8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881420637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_mem_partial_access.881420637 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.985526650 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 19695198596 ps |
CPU time | 239.51 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:48:47 PM PST 23 |
Peak memory | 202060 kb |
Host | smart-884b8e0d-27fd-4ae9-af45-0ef2a0c521ef |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985526650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _mem_walk.985526650 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.2803236487 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 7133606984 ps |
CPU time | 1157.15 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 01:04:10 PM PST 23 |
Peak memory | 378968 kb |
Host | smart-3e19a54d-a039-4ef1-bec3-d6f512e0aaa9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803236487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.2803236487 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.3178914857 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 1197039572 ps |
CPU time | 73.48 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:46:04 PM PST 23 |
Peak memory | 304868 kb |
Host | smart-b0612a76-b20a-405d-b0fa-595170348c30 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178914857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.3178914857 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3322809190 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 102674257054 ps |
CPU time | 343.12 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:50:20 PM PST 23 |
Peak memory | 202104 kb |
Host | smart-84826560-c524-4a3f-abd9-e5fa9de08dd3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322809190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3322809190 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.3479914012 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 682203554 ps |
CPU time | 6.41 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 12:44:41 PM PST 23 |
Peak memory | 202272 kb |
Host | smart-ad0114af-8927-464f-b931-a773aee60e92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479914012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3479914012 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.3095586421 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 7648549700 ps |
CPU time | 1063.23 seconds |
Started | Dec 27 12:44:36 PM PST 23 |
Finished | Dec 27 01:02:27 PM PST 23 |
Peak memory | 378908 kb |
Host | smart-e079f7e2-e2af-4bd1-a080-ef60e3d1a85d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095586421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3095586421 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.1739167161 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 1097541273 ps |
CPU time | 18.34 seconds |
Started | Dec 27 12:44:24 PM PST 23 |
Finished | Dec 27 12:44:52 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-5bc0dfe2-5178-4e05-87f5-ecb020640a0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739167161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1739167161 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.1120270046 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 683305247494 ps |
CPU time | 4719.84 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 02:03:33 PM PST 23 |
Peak memory | 388212 kb |
Host | smart-d755629c-c150-4b38-ad82-d050cb1d943a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120270046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.1120270046 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3746392452 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 518154490 ps |
CPU time | 1598.27 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 01:11:24 PM PST 23 |
Peak memory | 388532 kb |
Host | smart-13b1d389-ec2e-415f-9c45-c4d4a83a4f23 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3746392452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3746392452 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1749086321 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 14960511247 ps |
CPU time | 320.78 seconds |
Started | Dec 27 12:44:12 PM PST 23 |
Finished | Dec 27 12:49:44 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-9f1624f2-c88b-4867-a51b-975dbdd339ea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749086321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.1749086321 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.755862316 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 6684416996 ps |
CPU time | 72.05 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 12:46:00 PM PST 23 |
Peak memory | 302356 kb |
Host | smart-2cf01065-c746-4d04-8f7b-e164174e7fd0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755862316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.755862316 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3622038048 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 20704560354 ps |
CPU time | 938.68 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 01:00:31 PM PST 23 |
Peak memory | 379952 kb |
Host | smart-087ed734-dbb1-4f56-964d-355d45e91085 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622038048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.3622038048 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.3189310210 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 37572699 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:44:43 PM PST 23 |
Finished | Dec 27 12:44:49 PM PST 23 |
Peak memory | 201292 kb |
Host | smart-f1e1ed06-902f-48bd-82a9-9901254e063c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189310210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3189310210 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.1472270784 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 141172445734 ps |
CPU time | 1622.34 seconds |
Started | Dec 27 12:44:36 PM PST 23 |
Finished | Dec 27 01:11:46 PM PST 23 |
Peak memory | 201872 kb |
Host | smart-65f426c3-c490-4df6-8acb-d3d32d7cfed2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472270784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .1472270784 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.669858042 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 3369712982 ps |
CPU time | 129.74 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:46:52 PM PST 23 |
Peak memory | 361592 kb |
Host | smart-19b88496-3cab-411d-8bfb-f58d7bf03f23 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669858042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executabl e.669858042 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.3288978168 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 14238861622 ps |
CPU time | 142.55 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:47:03 PM PST 23 |
Peak memory | 210232 kb |
Host | smart-0b92505e-6d8f-4243-989c-5282d6468775 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288978168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.3288978168 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.3182159337 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 698781126 ps |
CPU time | 26.85 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 12:45:06 PM PST 23 |
Peak memory | 211212 kb |
Host | smart-2cd98308-4c1c-4a92-a75a-f8d699e40ca3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182159337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.3182159337 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.607189063 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 2457159788 ps |
CPU time | 79.06 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 12:45:54 PM PST 23 |
Peak memory | 211116 kb |
Host | smart-aadb8e19-7331-4d6c-b46f-7c46445c851a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607189063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .sram_ctrl_mem_partial_access.607189063 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.2297013640 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 7184992536 ps |
CPU time | 138.51 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:46:53 PM PST 23 |
Peak memory | 202036 kb |
Host | smart-8f5b4492-7ef5-4c3f-97e7-8912639e3d59 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297013640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.2297013640 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.785656623 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 26043597329 ps |
CPU time | 551.07 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:53:54 PM PST 23 |
Peak memory | 370944 kb |
Host | smart-6bd3571d-b323-4f75-9c51-193c5a046803 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785656623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.785656623 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.4254042376 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 6957923658 ps |
CPU time | 21.32 seconds |
Started | Dec 27 12:44:40 PM PST 23 |
Finished | Dec 27 12:45:08 PM PST 23 |
Peak memory | 258164 kb |
Host | smart-612391fe-4ef4-47e5-8e66-e4756a94354b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254042376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.4254042376 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2341511762 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 103433606993 ps |
CPU time | 425.36 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:51:42 PM PST 23 |
Peak memory | 202004 kb |
Host | smart-4329cc5f-9d78-4afc-92f0-7df23359506d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341511762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.2341511762 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.2124835689 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 3347430792 ps |
CPU time | 7.89 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 12:45:15 PM PST 23 |
Peak memory | 202412 kb |
Host | smart-681e91f3-e313-4a13-9ff4-bb24c9797a37 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124835689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2124835689 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.558936621 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 53461928729 ps |
CPU time | 943.21 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 01:00:24 PM PST 23 |
Peak memory | 376936 kb |
Host | smart-d4cf6751-1c27-416e-a542-b8c749f1e023 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558936621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.558936621 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.3337438971 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 1421826706 ps |
CPU time | 22.82 seconds |
Started | Dec 27 12:44:36 PM PST 23 |
Finished | Dec 27 12:45:06 PM PST 23 |
Peak memory | 201884 kb |
Host | smart-54598e8b-751a-4603-8658-dcbdf53ba21f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337438971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3337438971 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.1881056906 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 144284432605 ps |
CPU time | 2642.68 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 01:29:11 PM PST 23 |
Peak memory | 389304 kb |
Host | smart-b460a3b2-75dc-426d-afa0-b16fb0ff9509 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881056906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.1881056906 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1772594614 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 2892501116 ps |
CPU time | 4399 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 01:58:08 PM PST 23 |
Peak memory | 448304 kb |
Host | smart-d8d418f4-fc56-4990-aad6-1540cb90f849 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1772594614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1772594614 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2128785203 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 35184394717 ps |
CPU time | 376.98 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:51:13 PM PST 23 |
Peak memory | 201984 kb |
Host | smart-883b46c3-2c61-4e75-8794-c00d1a15b081 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128785203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2128785203 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2862144079 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 809783313 ps |
CPU time | 110.39 seconds |
Started | Dec 27 12:44:29 PM PST 23 |
Finished | Dec 27 12:46:29 PM PST 23 |
Peak memory | 344184 kb |
Host | smart-3d5b080c-1866-4387-8b92-25164b4aab53 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862144079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2862144079 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2459363746 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 2938228125 ps |
CPU time | 459.36 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:52:27 PM PST 23 |
Peak memory | 356544 kb |
Host | smart-2c00c8e6-5d9c-455d-97fc-1cf0f3472c4a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459363746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.2459363746 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.1097669359 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 19916520 ps |
CPU time | 0.69 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:45:01 PM PST 23 |
Peak memory | 201808 kb |
Host | smart-6683e659-2418-417b-ab30-f532e1c2207c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097669359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1097669359 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.1894403840 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 48051906069 ps |
CPU time | 1933.02 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 01:16:53 PM PST 23 |
Peak memory | 202068 kb |
Host | smart-27eafbd6-e829-4bea-8a0c-b645bead5ee2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894403840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .1894403840 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.1739998752 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 30242344238 ps |
CPU time | 305.49 seconds |
Started | Dec 27 12:45:05 PM PST 23 |
Finished | Dec 27 12:50:18 PM PST 23 |
Peak memory | 324904 kb |
Host | smart-b21f005b-f6b2-4c84-bc1e-a9e4403e6ec4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739998752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.1739998752 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.199581893 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 55163420328 ps |
CPU time | 147.62 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 12:47:34 PM PST 23 |
Peak memory | 202044 kb |
Host | smart-921edd02-3f99-4389-9946-8289170971ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199581893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc alation.199581893 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.2985432011 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 4049815404 ps |
CPU time | 68.29 seconds |
Started | Dec 27 12:44:29 PM PST 23 |
Finished | Dec 27 12:45:47 PM PST 23 |
Peak memory | 307524 kb |
Host | smart-3dac99fb-5f47-44af-ac8e-189b6759a06f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985432011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.2985432011 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2274889439 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 9932744117 ps |
CPU time | 154.59 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:47:30 PM PST 23 |
Peak memory | 213264 kb |
Host | smart-2485134f-e99f-4b6a-9179-2d965237ad9e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274889439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.2274889439 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.3882500874 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 10768323086 ps |
CPU time | 161.06 seconds |
Started | Dec 27 12:44:35 PM PST 23 |
Finished | Dec 27 12:47:24 PM PST 23 |
Peak memory | 202124 kb |
Host | smart-7b162e8c-a7a4-43ed-8f8d-7ceae5d08777 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882500874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.3882500874 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.1930423271 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 31438298367 ps |
CPU time | 1106.27 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 01:03:14 PM PST 23 |
Peak memory | 373928 kb |
Host | smart-8e7dfed9-7e77-4d16-8767-f9aaf6fbbc90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930423271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.1930423271 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.2090254628 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 895007652 ps |
CPU time | 106.79 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:46:40 PM PST 23 |
Peak memory | 341492 kb |
Host | smart-df6b81e5-d8ef-4a3a-939e-63f4fff83ca7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090254628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.2090254628 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.508502940 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 17307056090 ps |
CPU time | 286.69 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:49:28 PM PST 23 |
Peak memory | 202088 kb |
Host | smart-6f6d4f92-6a65-45c8-aff4-7d989bc73ef7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508502940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.sram_ctrl_partial_access_b2b.508502940 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.1509079597 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 1405709534 ps |
CPU time | 13.47 seconds |
Started | Dec 27 12:44:37 PM PST 23 |
Finished | Dec 27 12:44:58 PM PST 23 |
Peak memory | 202264 kb |
Host | smart-baadb577-32a9-489e-a17b-bd2eda92d5ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509079597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1509079597 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.3026559985 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 734509771 ps |
CPU time | 12.48 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:45:04 PM PST 23 |
Peak memory | 201956 kb |
Host | smart-3b2cfec9-a2bd-4e65-a1f4-ac26f750f674 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026559985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3026559985 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.807191073 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 12885075983 ps |
CPU time | 220.15 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:48:18 PM PST 23 |
Peak memory | 202088 kb |
Host | smart-d28d39af-6536-4f71-9f08-e3e3f4120329 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807191073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .sram_ctrl_stress_pipeline.807191073 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4228549030 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 1379498583 ps |
CPU time | 30.09 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:45:22 PM PST 23 |
Peak memory | 234620 kb |
Host | smart-225440fd-f139-4a3a-ae5c-d083880e6829 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228549030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.4228549030 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.468137362 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 25583152820 ps |
CPU time | 1885.22 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 01:16:11 PM PST 23 |
Peak memory | 381100 kb |
Host | smart-cd0f8817-b358-4828-9454-fbfdcafd233c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468137362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_access_during_key_req.468137362 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.3491607276 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 38427059 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:44:32 PM PST 23 |
Peak memory | 201284 kb |
Host | smart-43aeaffb-a04e-466b-8440-c4f0da606fa7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491607276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3491607276 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2976945088 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 60007909919 ps |
CPU time | 1107.25 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 01:03:08 PM PST 23 |
Peak memory | 202124 kb |
Host | smart-c4e87b02-17b1-428d-81d0-b004c89b612b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976945088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2976945088 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.1384434425 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 21549683931 ps |
CPU time | 119.3 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 12:47:07 PM PST 23 |
Peak memory | 210340 kb |
Host | smart-de4182e3-0c1a-42db-b330-ee254d06e396 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384434425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.1384434425 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.2592011424 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 2684927200 ps |
CPU time | 26.29 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:45:35 PM PST 23 |
Peak memory | 210252 kb |
Host | smart-7c4d17ac-861b-4849-8eb3-5d0f7dde0702 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592011424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.2592011424 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3021590730 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 13027422448 ps |
CPU time | 136.99 seconds |
Started | Dec 27 12:44:38 PM PST 23 |
Finished | Dec 27 12:47:03 PM PST 23 |
Peak memory | 211396 kb |
Host | smart-3c50e4c6-d736-4981-85f8-ab23bd8170b8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021590730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.3021590730 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.1643764842 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 21899768686 ps |
CPU time | 245.7 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 12:48:59 PM PST 23 |
Peak memory | 202148 kb |
Host | smart-1d91f9ed-7792-4e14-b627-5fc3ca865a13 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643764842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.1643764842 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.2195466231 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 126881651373 ps |
CPU time | 1243.47 seconds |
Started | Dec 27 12:44:17 PM PST 23 |
Finished | Dec 27 01:05:11 PM PST 23 |
Peak memory | 376920 kb |
Host | smart-3357f09a-fc02-4173-8ffb-a3d3cffc3e3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195466231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.2195466231 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.3383724070 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 2103607261 ps |
CPU time | 32.56 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:45:04 PM PST 23 |
Peak memory | 201940 kb |
Host | smart-0aa05ef2-bf29-4520-9b14-f48ccd692191 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383724070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.3383724070 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2524430275 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 15129418444 ps |
CPU time | 468.18 seconds |
Started | Dec 27 12:44:43 PM PST 23 |
Finished | Dec 27 12:52:44 PM PST 23 |
Peak memory | 202028 kb |
Host | smart-802cb6ac-9c4a-4aa2-bceb-0e6ceafb4112 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524430275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.2524430275 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.160852802 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 357593929 ps |
CPU time | 6.51 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:45:10 PM PST 23 |
Peak memory | 202264 kb |
Host | smart-946d02eb-2618-47ea-abee-a0d47a3d969e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160852802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.160852802 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.2160056100 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 8108278065 ps |
CPU time | 1214.81 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 01:04:57 PM PST 23 |
Peak memory | 373900 kb |
Host | smart-207cc79e-0862-4c98-a95a-ff2d6944c067 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160056100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2160056100 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.1770519994 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 1668896820 ps |
CPU time | 29.3 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 12:45:04 PM PST 23 |
Peak memory | 201900 kb |
Host | smart-38811df4-6b0c-4fd3-a1be-670240226829 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770519994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1770519994 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2237297257 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 8428068537 ps |
CPU time | 2062.3 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 01:19:26 PM PST 23 |
Peak memory | 653552 kb |
Host | smart-f7a53bdb-608a-4a65-9475-29e3f251a611 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2237297257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2237297257 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.845406958 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 18446610256 ps |
CPU time | 428.89 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 12:51:48 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-5e462343-7927-49f7-8586-2c935d4ee5bb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845406958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_stress_pipeline.845406958 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4212253362 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1594895049 ps |
CPU time | 28.84 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:45:23 PM PST 23 |
Peak memory | 219712 kb |
Host | smart-97ffdf17-fb1b-4296-958a-1941eb2149b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212253362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.4212253362 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3677842709 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 109224216457 ps |
CPU time | 1664.47 seconds |
Started | Dec 27 12:44:43 PM PST 23 |
Finished | Dec 27 01:12:33 PM PST 23 |
Peak memory | 376940 kb |
Host | smart-414925d8-f403-4b34-b8b5-4e33c55ba69b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677842709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.3677842709 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.1248915276 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 20428838 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:44:40 PM PST 23 |
Finished | Dec 27 12:44:47 PM PST 23 |
Peak memory | 201664 kb |
Host | smart-1502a0bd-ba8a-49b0-b6da-739c0455d7ff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248915276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1248915276 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.2726389537 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 11648407402 ps |
CPU time | 720.88 seconds |
Started | Dec 27 12:44:37 PM PST 23 |
Finished | Dec 27 12:56:46 PM PST 23 |
Peak memory | 202088 kb |
Host | smart-ca155d6a-6b46-4366-b9dc-e30b01cbb1e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726389537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .2726389537 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.1921647836 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 4646372243 ps |
CPU time | 92.92 seconds |
Started | Dec 27 12:44:40 PM PST 23 |
Finished | Dec 27 12:46:19 PM PST 23 |
Peak memory | 340108 kb |
Host | smart-313f4932-1777-4f07-953a-274f7394d4ae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921647836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.1921647836 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.110185759 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 9203208811 ps |
CPU time | 146.9 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:47:07 PM PST 23 |
Peak memory | 211144 kb |
Host | smart-765d2c9c-54d0-4adb-9b62-6d20bc512d15 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110185759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_mem_partial_access.110185759 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.4014349050 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 42165350815 ps |
CPU time | 303.32 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:49:46 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-02713d0f-04b5-4b7d-a418-f1a1aa85bbbe |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014349050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.4014349050 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.96225875 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 101660545148 ps |
CPU time | 630.1 seconds |
Started | Dec 27 12:44:37 PM PST 23 |
Finished | Dec 27 12:55:15 PM PST 23 |
Peak memory | 376812 kb |
Host | smart-28bb61c0-599b-4096-9432-32b3ee5f6a19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96225875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multipl e_keys.96225875 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.3240563159 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 1774257813 ps |
CPU time | 124.8 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 12:46:37 PM PST 23 |
Peak memory | 370580 kb |
Host | smart-d73fbf31-28a4-42e0-9345-9fd0a9bed2a4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240563159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3240563159 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2812819113 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 56197541111 ps |
CPU time | 712.35 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:56:40 PM PST 23 |
Peak memory | 202004 kb |
Host | smart-1ab3b3f7-7397-4fd8-afa0-7148d56b8842 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812819113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2812819113 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.617905545 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 360042623 ps |
CPU time | 13.05 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:44:54 PM PST 23 |
Peak memory | 202312 kb |
Host | smart-87cabd17-9c79-47f3-90d6-1c17e15cb24b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617905545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.617905545 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.460945744 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 19163295700 ps |
CPU time | 338.61 seconds |
Started | Dec 27 12:44:19 PM PST 23 |
Finished | Dec 27 12:50:08 PM PST 23 |
Peak memory | 357428 kb |
Host | smart-4b611f5a-4eec-4f10-accb-a5c722944b15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460945744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.460945744 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.1617866092 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 999552130 ps |
CPU time | 21.14 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:45:21 PM PST 23 |
Peak memory | 202072 kb |
Host | smart-3b36c475-f733-4f87-9a39-e08051fd9d59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617866092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1617866092 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.52403178 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 248782081431 ps |
CPU time | 3510.8 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 01:43:19 PM PST 23 |
Peak memory | 382128 kb |
Host | smart-768a3ff0-e675-4b42-83b3-320eb821f90f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52403178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.sram_ctrl_stress_all.52403178 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.886008481 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 1247762356 ps |
CPU time | 4051.17 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 01:52:29 PM PST 23 |
Peak memory | 619432 kb |
Host | smart-b476b30c-36ce-41d6-9213-df7b1f995e8d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=886008481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.886008481 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3386300690 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 5808442212 ps |
CPU time | 213.03 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:48:37 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-123e35eb-b0d0-4418-a2c2-01d9fa2fc154 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386300690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3386300690 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.677050565 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 9234258905 ps |
CPU time | 73.5 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 12:45:53 PM PST 23 |
Peak memory | 305344 kb |
Host | smart-2ed19c7a-7b24-4fe4-8c52-19723109b0c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677050565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.677050565 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2284838917 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 64154677252 ps |
CPU time | 1131.45 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 01:03:27 PM PST 23 |
Peak memory | 372836 kb |
Host | smart-d7e5a448-7d19-4924-a9a2-9802f680bb96 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284838917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.2284838917 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.205645066 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 43819145 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:44:35 PM PST 23 |
Peak memory | 201672 kb |
Host | smart-3e92f96c-6380-4e0d-ac88-a79115e7f805 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205645066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.205645066 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.2038709222 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 76048442913 ps |
CPU time | 1232.68 seconds |
Started | Dec 27 12:44:37 PM PST 23 |
Finished | Dec 27 01:05:17 PM PST 23 |
Peak memory | 202116 kb |
Host | smart-cde6236b-9743-44c4-8f70-8350b33e7d31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038709222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .2038709222 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.3091910510 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 21768024516 ps |
CPU time | 1048.48 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 01:02:25 PM PST 23 |
Peak memory | 378040 kb |
Host | smart-653ac29f-9d97-4ec5-aaa3-e3af4260de35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091910510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.3091910510 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.2809811432 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 50738493689 ps |
CPU time | 70.37 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:46:07 PM PST 23 |
Peak memory | 210468 kb |
Host | smart-577fd222-d144-44e3-9788-e5141f48bb20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809811432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.2809811432 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.1199312218 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 803858285 ps |
CPU time | 72.6 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:46:10 PM PST 23 |
Peak memory | 327788 kb |
Host | smart-cc0cabf2-bd5b-4032-ade7-cd7b437df2b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199312218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1199312218 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3353796234 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 72552893250 ps |
CPU time | 156.28 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:47:40 PM PST 23 |
Peak memory | 210980 kb |
Host | smart-2dd9ab31-09e7-44d8-8300-0603df707e79 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353796234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3353796234 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.159508466 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 4027837353 ps |
CPU time | 242.16 seconds |
Started | Dec 27 12:44:36 PM PST 23 |
Finished | Dec 27 12:48:46 PM PST 23 |
Peak memory | 201976 kb |
Host | smart-6e441c40-1578-4307-a732-97872bf9b422 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159508466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _mem_walk.159508466 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.1785060200 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 50216902225 ps |
CPU time | 1136.12 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 01:03:44 PM PST 23 |
Peak memory | 373784 kb |
Host | smart-b7644622-f673-4dd0-a74b-347f45e0a469 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785060200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1785060200 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.2548854138 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 5714179990 ps |
CPU time | 91.26 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:46:12 PM PST 23 |
Peak memory | 321012 kb |
Host | smart-256034ff-fb49-47c8-b9f5-fc2ece551ed8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548854138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.2548854138 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.884124696 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 4789343030 ps |
CPU time | 5.85 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:45:00 PM PST 23 |
Peak memory | 202348 kb |
Host | smart-7e51ebb0-253e-4ead-a87f-0ca8c7659a27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884124696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.884124696 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.2839628614 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 6515106178 ps |
CPU time | 136.69 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:47:17 PM PST 23 |
Peak memory | 278668 kb |
Host | smart-6dc13c3c-5aba-48d5-8dbf-930aadd7b8f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839628614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2839628614 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.93103374 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 1585200701 ps |
CPU time | 42.82 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 12:45:22 PM PST 23 |
Peak memory | 289720 kb |
Host | smart-afefea77-6ee0-401e-baa8-f754111a4f1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93103374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.93103374 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1013987154 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 1089655407 ps |
CPU time | 3747.3 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 01:47:22 PM PST 23 |
Peak memory | 810872 kb |
Host | smart-1bdc4d39-86a1-4689-85ea-d3d3e188c282 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1013987154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1013987154 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3059624049 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 22355104372 ps |
CPU time | 392.39 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:51:28 PM PST 23 |
Peak memory | 202032 kb |
Host | smart-944b5021-3a63-426a-9e2a-0b66157c1183 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059624049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3059624049 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4288848365 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 3136279267 ps |
CPU time | 102 seconds |
Started | Dec 27 12:44:29 PM PST 23 |
Finished | Dec 27 12:46:20 PM PST 23 |
Peak memory | 328948 kb |
Host | smart-54d3dc2d-5c43-4f64-8615-0c65f0e8b035 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288848365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.4288848365 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1148763064 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 8355929724 ps |
CPU time | 1128.52 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 01:03:51 PM PST 23 |
Peak memory | 378016 kb |
Host | smart-122dbca5-e7f0-4309-b5e1-b976846b18fe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148763064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1148763064 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.3818484770 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 19120945 ps |
CPU time | 0.66 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:44:51 PM PST 23 |
Peak memory | 201792 kb |
Host | smart-8691ed99-3ad7-4e70-a880-725e536128d9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818484770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3818484770 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.3263930636 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 32152402120 ps |
CPU time | 1132.53 seconds |
Started | Dec 27 12:44:44 PM PST 23 |
Finished | Dec 27 01:03:42 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-6f876b9e-c8a5-4a5a-9160-7c3957754d6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263930636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .3263930636 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.1120707125 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 23515077660 ps |
CPU time | 979.37 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 01:01:13 PM PST 23 |
Peak memory | 373740 kb |
Host | smart-125ee371-4fd0-415b-86af-a2140d4466f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120707125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.1120707125 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.1660325506 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 18495814735 ps |
CPU time | 111.8 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:46:49 PM PST 23 |
Peak memory | 213704 kb |
Host | smart-b53908e2-9616-4ba9-8f93-6d6c805fe6fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660325506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.1660325506 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.3096425567 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 806202211 ps |
CPU time | 128.17 seconds |
Started | Dec 27 12:44:58 PM PST 23 |
Finished | Dec 27 12:47:14 PM PST 23 |
Peak memory | 364504 kb |
Host | smart-3d6eaa69-c20d-4de9-be50-8a1b7e362fc2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096425567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.3096425567 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2045530120 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 18839966750 ps |
CPU time | 146.45 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:47:11 PM PST 23 |
Peak memory | 210996 kb |
Host | smart-e2c1395c-b747-461c-a887-5b12b5c5856a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045530120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2045530120 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3380233038 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 15761162154 ps |
CPU time | 238.27 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:48:32 PM PST 23 |
Peak memory | 202160 kb |
Host | smart-c63fc6a9-aef3-40b6-b602-8223f91c2cf8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380233038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3380233038 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.986989154 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 7647419184 ps |
CPU time | 104.64 seconds |
Started | Dec 27 12:44:16 PM PST 23 |
Finished | Dec 27 12:46:12 PM PST 23 |
Peak memory | 290796 kb |
Host | smart-bee97554-6cee-420e-9227-68a1f2d49e4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986989154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip le_keys.986989154 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.1719047720 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 4993848209 ps |
CPU time | 23.89 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:45:48 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-aec55190-a542-4c05-a247-812857adbfe4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719047720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1719047720 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1599239223 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 11592116561 ps |
CPU time | 294.99 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:49:48 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-522eaad2-ecbd-49cd-a35c-0e6e63b40db8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599239223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.1599239223 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.472995212 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 683763025 ps |
CPU time | 6.56 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:44:47 PM PST 23 |
Peak memory | 202228 kb |
Host | smart-b37bcef6-229e-4107-b00e-0373c3c25157 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472995212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.472995212 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.1394604919 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 6550487696 ps |
CPU time | 625.72 seconds |
Started | Dec 27 12:44:43 PM PST 23 |
Finished | Dec 27 12:55:15 PM PST 23 |
Peak memory | 373720 kb |
Host | smart-f6bd9143-88d8-4d0c-b531-e0a672d96b25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394604919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1394604919 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.3148745864 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 1265358927 ps |
CPU time | 14.07 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 12:45:20 PM PST 23 |
Peak memory | 201944 kb |
Host | smart-0ebadbbb-58e8-42fe-86f4-4913a39611d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148745864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3148745864 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.3290977576 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 129714229110 ps |
CPU time | 5446.85 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 02:15:34 PM PST 23 |
Peak memory | 380016 kb |
Host | smart-89b4ba0e-4714-4dca-8776-b308527760cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290977576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.3290977576 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1187059635 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 4215540332 ps |
CPU time | 3908.83 seconds |
Started | Dec 27 12:44:44 PM PST 23 |
Finished | Dec 27 01:49:59 PM PST 23 |
Peak memory | 701700 kb |
Host | smart-0d8a7b3d-ea1a-426a-83a3-3089710667b8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1187059635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1187059635 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1059907068 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 4350054532 ps |
CPU time | 297.85 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 12:49:39 PM PST 23 |
Peak memory | 202020 kb |
Host | smart-ab9a6033-1142-4a01-a439-d3e97792c761 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059907068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.1059907068 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.595936836 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1567681656 ps |
CPU time | 78.27 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:46:22 PM PST 23 |
Peak memory | 327860 kb |
Host | smart-f5e975f0-b55f-418c-b3c1-30f45e967e6a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595936836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.595936836 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.3012933666 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 14299707 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:44:41 PM PST 23 |
Peak memory | 201728 kb |
Host | smart-2955ca4d-f747-4fa8-8849-7a0a991340ca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012933666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3012933666 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.3625264296 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 492875236982 ps |
CPU time | 2328.81 seconds |
Started | Dec 27 12:44:52 PM PST 23 |
Finished | Dec 27 01:23:48 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-5feb122a-8e76-4105-a776-a3ee0fd3b2a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625264296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .3625264296 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.3883543957 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 8439942621 ps |
CPU time | 470.46 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:52:42 PM PST 23 |
Peak memory | 358392 kb |
Host | smart-b599e15a-bf98-4714-bd88-b2dcaa8c2769 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883543957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.3883543957 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.1503418486 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 3333818791 ps |
CPU time | 140.31 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:47:23 PM PST 23 |
Peak memory | 359080 kb |
Host | smart-df47bd9d-aa64-46e7-9bbf-1cee69b5c851 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503418486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.1503418486 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2708940754 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 1922544592 ps |
CPU time | 71.95 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:46:12 PM PST 23 |
Peak memory | 210948 kb |
Host | smart-b69ec847-160e-420d-af7a-9229e30ad676 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708940754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.2708940754 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.1425866576 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 2059987917 ps |
CPU time | 122.68 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 12:46:50 PM PST 23 |
Peak memory | 201912 kb |
Host | smart-21cfe958-9102-4eff-b728-c7db988c12d9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425866576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.1425866576 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.3026473880 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 16457735799 ps |
CPU time | 413.02 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:51:49 PM PST 23 |
Peak memory | 364564 kb |
Host | smart-2e4373c9-8579-48bd-b487-e466409ff61d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026473880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.3026473880 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.2880547747 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 2065231167 ps |
CPU time | 97.41 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 12:46:25 PM PST 23 |
Peak memory | 342536 kb |
Host | smart-b82ca6a3-ff98-4d36-8037-2937af191a97 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880547747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.2880547747 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2167244944 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 17684052076 ps |
CPU time | 341.93 seconds |
Started | Dec 27 12:44:40 PM PST 23 |
Finished | Dec 27 12:50:29 PM PST 23 |
Peak memory | 202004 kb |
Host | smart-4ab1a16d-1df6-400e-8815-57e50b438e45 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167244944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.2167244944 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3030078117 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 1058048187 ps |
CPU time | 6.46 seconds |
Started | Dec 27 12:44:38 PM PST 23 |
Finished | Dec 27 12:44:52 PM PST 23 |
Peak memory | 202360 kb |
Host | smart-42cc9478-1ca5-4e03-b502-31ce6347c517 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030078117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3030078117 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.2736256311 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 47925554947 ps |
CPU time | 1105.34 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 01:03:06 PM PST 23 |
Peak memory | 378976 kb |
Host | smart-b336e8bc-1fea-4cdd-b1e8-456359becef6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736256311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2736256311 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.1878954820 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 10005148233 ps |
CPU time | 57.43 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:46:10 PM PST 23 |
Peak memory | 329752 kb |
Host | smart-40fb90f5-940b-484e-bacd-2043eb7e22f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878954820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1878954820 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1495508963 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 254385635 ps |
CPU time | 3477.14 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 01:43:10 PM PST 23 |
Peak memory | 519192 kb |
Host | smart-77a9f7f7-72e7-442e-9490-f6f332a25d37 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1495508963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1495508963 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1684638429 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 9985369468 ps |
CPU time | 322.62 seconds |
Started | Dec 27 12:44:44 PM PST 23 |
Finished | Dec 27 12:50:12 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-6540b683-d63c-496c-a1e1-c6b7e1b4420a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684638429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.1684638429 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1951663735 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 13009534477 ps |
CPU time | 149.82 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:47:18 PM PST 23 |
Peak memory | 366676 kb |
Host | smart-9a378647-fc8d-4723-9c2c-7d0087d1b444 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951663735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1951663735 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.118131934 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 2315492248 ps |
CPU time | 212.62 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 12:48:05 PM PST 23 |
Peak memory | 352400 kb |
Host | smart-7ea6a47a-09cb-4a10-af98-6b1c927a98b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118131934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_access_during_key_req.118131934 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.2015046752 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 23065268 ps |
CPU time | 0.68 seconds |
Started | Dec 27 12:44:27 PM PST 23 |
Finished | Dec 27 12:44:37 PM PST 23 |
Peak memory | 201728 kb |
Host | smart-6fbead28-6b5f-4075-9d51-3beed5af31de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015046752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2015046752 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.2841614138 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 100779964570 ps |
CPU time | 1822.6 seconds |
Started | Dec 27 12:44:24 PM PST 23 |
Finished | Dec 27 01:14:57 PM PST 23 |
Peak memory | 202152 kb |
Host | smart-885cbd63-9581-43f4-87af-d08c4d8398ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841614138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 2841614138 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.2641820059 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 10723870798 ps |
CPU time | 30.09 seconds |
Started | Dec 27 12:44:29 PM PST 23 |
Finished | Dec 27 12:45:13 PM PST 23 |
Peak memory | 213428 kb |
Host | smart-75c3084e-f3ae-44bc-8ec1-10739d39a512 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641820059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.2641820059 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.3836278708 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 2741625799 ps |
CPU time | 32.67 seconds |
Started | Dec 27 12:44:19 PM PST 23 |
Finished | Dec 27 12:45:02 PM PST 23 |
Peak memory | 234888 kb |
Host | smart-7c16c60d-731c-401a-b0d1-ea152eb7eb68 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836278708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.3836278708 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2152262194 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 18771962470 ps |
CPU time | 159.31 seconds |
Started | Dec 27 12:44:27 PM PST 23 |
Finished | Dec 27 12:47:16 PM PST 23 |
Peak memory | 211060 kb |
Host | smart-c1e3dab1-8d68-4fe2-a2ca-67ca59f0dbf8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152262194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.2152262194 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.3989584146 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 2085931001 ps |
CPU time | 123.71 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:47:01 PM PST 23 |
Peak memory | 201980 kb |
Host | smart-59bd1bbb-c600-4106-b747-2c44f9542c0b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989584146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.3989584146 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.2932043844 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 46625086842 ps |
CPU time | 968.97 seconds |
Started | Dec 27 12:44:10 PM PST 23 |
Finished | Dec 27 01:00:30 PM PST 23 |
Peak memory | 378008 kb |
Host | smart-1ecd2ca3-3213-43b4-ad0b-eedfbd2dfa77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932043844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.2932043844 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.2922548991 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 582695159 ps |
CPU time | 28.57 seconds |
Started | Dec 27 12:44:10 PM PST 23 |
Finished | Dec 27 12:44:50 PM PST 23 |
Peak memory | 202032 kb |
Host | smart-6aa24b9a-a861-45c1-aec5-2bc0117a1c55 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922548991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.2922548991 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.272056389 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 39946979864 ps |
CPU time | 445.22 seconds |
Started | Dec 27 12:44:15 PM PST 23 |
Finished | Dec 27 12:51:51 PM PST 23 |
Peak memory | 202064 kb |
Host | smart-6abb229c-27d2-43a7-b109-e956ab7820cc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272056389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.sram_ctrl_partial_access_b2b.272056389 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.144717842 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1867745417 ps |
CPU time | 13.98 seconds |
Started | Dec 27 12:44:13 PM PST 23 |
Finished | Dec 27 12:44:37 PM PST 23 |
Peak memory | 202212 kb |
Host | smart-285a7068-d213-4c5a-b383-266e75e22664 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144717842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.144717842 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.1110285327 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 30070312896 ps |
CPU time | 417.63 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 12:51:44 PM PST 23 |
Peak memory | 373836 kb |
Host | smart-99310566-b1e9-45ce-8989-36c12631b451 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110285327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1110285327 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.2626837688 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 6900116625 ps |
CPU time | 16.66 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 12:44:56 PM PST 23 |
Peak memory | 202072 kb |
Host | smart-7784b67d-e446-4ff4-93a6-343ef6a074bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626837688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2626837688 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4285675195 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 588934317 ps |
CPU time | 3002.02 seconds |
Started | Dec 27 12:44:09 PM PST 23 |
Finished | Dec 27 01:34:23 PM PST 23 |
Peak memory | 519316 kb |
Host | smart-11c38d4b-2730-424a-9cd8-6c8b66b59ffe |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4285675195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.4285675195 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3561941587 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 2808351528 ps |
CPU time | 210.36 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:48:02 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-0a39a44e-68ce-4876-8687-31a1f986f131 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561941587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.3561941587 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3748920436 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1019213875 ps |
CPU time | 30.2 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:45:02 PM PST 23 |
Peak memory | 222528 kb |
Host | smart-7b7363fc-3df1-408c-a9eb-f4dfc06a0f3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748920436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3748920436 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3460051874 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 10558695481 ps |
CPU time | 534.86 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 12:54:02 PM PST 23 |
Peak memory | 379036 kb |
Host | smart-b57471c6-4c65-4d57-925d-154eea1d6701 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460051874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.3460051874 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.1601323190 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 28328850 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:44:55 PM PST 23 |
Peak memory | 201768 kb |
Host | smart-8ff10c09-0c26-4aa3-840f-1bab363e44bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601323190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1601323190 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.2619431256 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 403363695351 ps |
CPU time | 2122.16 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 01:19:58 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-16d2ea55-9c63-48b8-910d-e9fc7be5aebb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619431256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .2619431256 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.122574920 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 46157091608 ps |
CPU time | 126.23 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:46:54 PM PST 23 |
Peak memory | 210528 kb |
Host | smart-c1159126-79b7-4d74-8271-a1aff3479e2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122574920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc alation.122574920 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.3243742602 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 697844204 ps |
CPU time | 33.14 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:45:26 PM PST 23 |
Peak memory | 238660 kb |
Host | smart-f820818a-27c2-4d4f-9b36-a3723579294c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243742602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.3243742602 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3465023825 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 1554664849 ps |
CPU time | 131.65 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:47:02 PM PST 23 |
Peak memory | 210376 kb |
Host | smart-0cd886a9-6707-4de0-a2de-178953e759ae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465023825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.3465023825 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.168376192 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 25489279550 ps |
CPU time | 133.73 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 12:47:01 PM PST 23 |
Peak memory | 202032 kb |
Host | smart-ea5ba68a-dca0-400d-8550-a588483a0c78 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168376192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _mem_walk.168376192 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.1419196656 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 6892098955 ps |
CPU time | 799.75 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:58:21 PM PST 23 |
Peak memory | 380108 kb |
Host | smart-975121c7-e0d9-48c2-9181-b39da638c415 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419196656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.1419196656 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.1873407559 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 1084606317 ps |
CPU time | 44.68 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:45:38 PM PST 23 |
Peak memory | 291280 kb |
Host | smart-4a38ebf1-27fd-4106-a4e0-40848bec8f40 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873407559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1873407559 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3334600918 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 26442419923 ps |
CPU time | 323.65 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:50:06 PM PST 23 |
Peak memory | 202096 kb |
Host | smart-3e524a08-4e59-4cc2-8e79-67bca89e57c9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334600918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.3334600918 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.3465865685 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 369822881 ps |
CPU time | 13.03 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:45:09 PM PST 23 |
Peak memory | 202260 kb |
Host | smart-ee83cf01-f5d3-4480-a6d3-5c035479e187 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465865685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3465865685 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.1737537986 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 3977225879 ps |
CPU time | 23.67 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 12:45:03 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-db41cf1a-d1ee-48b8-9be3-af8cd2f927ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737537986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1737537986 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.446954627 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 79076575397 ps |
CPU time | 2633.61 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 01:28:56 PM PST 23 |
Peak memory | 380996 kb |
Host | smart-273f2248-f05c-4c65-a2ca-681b516e2e93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446954627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_stress_all.446954627 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3035080644 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1675136743 ps |
CPU time | 3065.8 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 01:36:11 PM PST 23 |
Peak memory | 632592 kb |
Host | smart-c6cdedc7-0f7c-436a-af8b-f44e59ffff47 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3035080644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3035080644 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1621582130 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 5133936555 ps |
CPU time | 386.83 seconds |
Started | Dec 27 12:44:35 PM PST 23 |
Finished | Dec 27 12:51:10 PM PST 23 |
Peak memory | 201976 kb |
Host | smart-8a78cd82-cee4-4133-bd55-4595029333f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621582130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1621582130 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3686246539 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 2684717332 ps |
CPU time | 27.72 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:45:20 PM PST 23 |
Peak memory | 211844 kb |
Host | smart-41c31276-c4f3-4e55-823b-5036f1eae664 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686246539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3686246539 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.4265762550 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 12296377113 ps |
CPU time | 1073.61 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 01:02:33 PM PST 23 |
Peak memory | 380108 kb |
Host | smart-4d0280fa-a723-4700-a437-e3741f533cde |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265762550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.4265762550 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.1543371081 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 24143050 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:44:51 PM PST 23 |
Peak memory | 201752 kb |
Host | smart-cfbcd0b6-b636-44bd-95ee-d103f3d47ff1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543371081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1543371081 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.3691061110 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 82891890018 ps |
CPU time | 1924.2 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 01:17:16 PM PST 23 |
Peak memory | 202084 kb |
Host | smart-bf31accd-e5df-412c-ac38-dda2264d05fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691061110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3691061110 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.3056202185 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 49346898495 ps |
CPU time | 392.52 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 12:51:39 PM PST 23 |
Peak memory | 370820 kb |
Host | smart-cf5bdaa0-d503-4620-9064-ea4e9dac4284 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056202185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.3056202185 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.3417484245 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 769369385 ps |
CPU time | 97.81 seconds |
Started | Dec 27 12:44:43 PM PST 23 |
Finished | Dec 27 12:46:26 PM PST 23 |
Peak memory | 348528 kb |
Host | smart-7b28303e-2def-4e30-a890-0333b0777cbd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417484245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.3417484245 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.4196837802 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 5232354808 ps |
CPU time | 146.17 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 12:47:33 PM PST 23 |
Peak memory | 210340 kb |
Host | smart-16a62312-726d-474a-831e-758a273a507e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196837802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.4196837802 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.3062751476 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 15764661516 ps |
CPU time | 261.71 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:49:10 PM PST 23 |
Peak memory | 202052 kb |
Host | smart-489cd2b9-8aa2-4593-be99-a3bc4c70233e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062751476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.3062751476 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.2327305255 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 20702690724 ps |
CPU time | 629.81 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:55:26 PM PST 23 |
Peak memory | 378668 kb |
Host | smart-3831f165-3404-4c14-970a-f212fde6f243 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327305255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2327305255 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.3684192921 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 2419058780 ps |
CPU time | 17.89 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:45:06 PM PST 23 |
Peak memory | 217768 kb |
Host | smart-a9ff0295-c470-43ca-984f-3c2585cb4862 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684192921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.3684192921 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2885731403 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 9270399855 ps |
CPU time | 242.6 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:48:58 PM PST 23 |
Peak memory | 202052 kb |
Host | smart-dafb8247-4b5d-4f45-887f-f2b8d253fe74 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885731403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.2885731403 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.3972497056 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 2606126823 ps |
CPU time | 6.47 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 12:44:46 PM PST 23 |
Peak memory | 202344 kb |
Host | smart-9c1be892-fa5f-45cf-8438-720668350412 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972497056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3972497056 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.1908904991 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 39585952934 ps |
CPU time | 264.9 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:49:38 PM PST 23 |
Peak memory | 361236 kb |
Host | smart-51c9ce4a-2389-4ad0-b7ba-8607de5ff711 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908904991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1908904991 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.4012429079 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 6654945359 ps |
CPU time | 25.14 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:45:33 PM PST 23 |
Peak memory | 201984 kb |
Host | smart-3fb24358-fc5c-453b-b17e-9590fd4dbb15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012429079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.4012429079 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1358647529 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1303323812 ps |
CPU time | 2608.39 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 01:28:21 PM PST 23 |
Peak memory | 416540 kb |
Host | smart-f458cfd1-9d17-4014-aa72-a77416d41d40 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1358647529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1358647529 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.850314890 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 2245649167 ps |
CPU time | 151.6 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:47:25 PM PST 23 |
Peak memory | 201976 kb |
Host | smart-f399a8f7-bb39-4e15-be37-5d783801b5cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850314890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_stress_pipeline.850314890 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1353338785 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 4122126305 ps |
CPU time | 128.43 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:47:05 PM PST 23 |
Peak memory | 366632 kb |
Host | smart-999dcc8b-ee14-475c-b72a-882871378153 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353338785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1353338785 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.700363818 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 16782415964 ps |
CPU time | 1724.35 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 01:13:56 PM PST 23 |
Peak memory | 379980 kb |
Host | smart-24bdd543-8338-43bc-a66e-24dcf350b31c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700363818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.sram_ctrl_access_during_key_req.700363818 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.1052675243 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 33978136 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 12:45:06 PM PST 23 |
Peak memory | 201712 kb |
Host | smart-e7c0b8db-41ac-4d71-bf5e-28c574f26c60 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052675243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1052675243 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.4045177168 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 957500571412 ps |
CPU time | 1796.7 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 01:14:36 PM PST 23 |
Peak memory | 202088 kb |
Host | smart-f04364b3-c76b-464b-8a87-247eca113a73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045177168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .4045177168 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.1945458186 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 36003588347 ps |
CPU time | 458.56 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:52:52 PM PST 23 |
Peak memory | 376852 kb |
Host | smart-b3065464-14c5-4301-ae6c-6567e3606ca9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945458186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.1945458186 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.3971362471 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 1613930977 ps |
CPU time | 65.33 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:46:24 PM PST 23 |
Peak memory | 319636 kb |
Host | smart-8372b8d6-b913-4638-9be6-4ab3d1d38e57 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971362471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.3971362471 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2043656055 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 1570839520 ps |
CPU time | 131.31 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 12:47:17 PM PST 23 |
Peak memory | 210996 kb |
Host | smart-cd2dff8b-29bb-4cea-a3ac-181be1547ce8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043656055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.2043656055 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.2963952839 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 4111023829 ps |
CPU time | 242.36 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:49:03 PM PST 23 |
Peak memory | 201976 kb |
Host | smart-4b121a52-1f0f-4343-88aa-4b4081584090 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963952839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.2963952839 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.1517372137 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 14877508307 ps |
CPU time | 856.96 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:59:31 PM PST 23 |
Peak memory | 380064 kb |
Host | smart-34274ffd-df5a-4eed-a3b3-54413e57b500 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517372137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.1517372137 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.3726473391 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 1153320666 ps |
CPU time | 61.89 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:46:11 PM PST 23 |
Peak memory | 306252 kb |
Host | smart-1021c443-a65e-44d3-a8a9-90c8152e145d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726473391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.3726473391 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.289992887 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 12591376998 ps |
CPU time | 297.72 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:49:46 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-a9793060-557a-4bfa-b08c-fab8f66875f2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289992887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.sram_ctrl_partial_access_b2b.289992887 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.2246802534 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 1539417892 ps |
CPU time | 6.11 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:44:59 PM PST 23 |
Peak memory | 202268 kb |
Host | smart-d3f379e1-871a-4ee1-b9a4-cb36652e68a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246802534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2246802534 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.3726843224 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 81695015510 ps |
CPU time | 1793.91 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 01:14:57 PM PST 23 |
Peak memory | 377984 kb |
Host | smart-3ee6c999-438e-4b5b-934b-1f7ca0c592eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726843224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3726843224 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.3785099976 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 411453230 ps |
CPU time | 7.9 seconds |
Started | Dec 27 12:44:29 PM PST 23 |
Finished | Dec 27 12:44:46 PM PST 23 |
Peak memory | 207588 kb |
Host | smart-d12f5930-3c13-48ec-b1ac-85d0c5196c70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785099976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3785099976 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4147087387 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 2890469433 ps |
CPU time | 2636.01 seconds |
Started | Dec 27 12:44:58 PM PST 23 |
Finished | Dec 27 01:29:02 PM PST 23 |
Peak memory | 434468 kb |
Host | smart-9e26cc66-e09e-44f0-86bb-921fbe56c888 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4147087387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.4147087387 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.977352368 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 9067759256 ps |
CPU time | 306.49 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 12:50:11 PM PST 23 |
Peak memory | 202036 kb |
Host | smart-94629d0d-a065-4ee8-9a18-54028a9c0c18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977352368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.977352368 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2355982516 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 3186317497 ps |
CPU time | 93.84 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:46:27 PM PST 23 |
Peak memory | 347400 kb |
Host | smart-5c37116d-fed0-4523-b4d4-b99b81775dc1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355982516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2355982516 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.662925771 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 3702836746 ps |
CPU time | 71.13 seconds |
Started | Dec 27 12:44:26 PM PST 23 |
Finished | Dec 27 12:45:46 PM PST 23 |
Peak memory | 294116 kb |
Host | smart-04afe421-9120-45b6-a740-691fdf4a03c3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662925771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 23.sram_ctrl_access_during_key_req.662925771 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.1085438487 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 42345518 ps |
CPU time | 0.6 seconds |
Started | Dec 27 12:45:05 PM PST 23 |
Finished | Dec 27 12:45:12 PM PST 23 |
Peak memory | 201388 kb |
Host | smart-6ce27a34-cf25-43d7-9d7b-fa94a64048f3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085438487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1085438487 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.2054620301 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 90488554160 ps |
CPU time | 1551.67 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 01:11:30 PM PST 23 |
Peak memory | 201984 kb |
Host | smart-46bae0ea-aff0-43a5-8b15-e0231ad6b959 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054620301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .2054620301 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.2684359724 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 9907518479 ps |
CPU time | 112.22 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:46:53 PM PST 23 |
Peak memory | 210300 kb |
Host | smart-427270ac-1922-4e10-a3b1-6446d261c176 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684359724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2684359724 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.974788226 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 3014862321 ps |
CPU time | 54.16 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:46:03 PM PST 23 |
Peak memory | 300108 kb |
Host | smart-ed28a0a0-aa79-44f0-9b8d-6ae56fea01b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974788226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.sram_ctrl_max_throughput.974788226 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1362086056 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 4745310021 ps |
CPU time | 144.84 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:47:23 PM PST 23 |
Peak memory | 214612 kb |
Host | smart-6e42af06-5473-4cfe-85e3-eaca92ab82d1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362086056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1362086056 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.1623787794 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 2104153464 ps |
CPU time | 126.61 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:47:03 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-fd6e2884-b855-4152-8e80-aac0a4f44e6a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623787794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.1623787794 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.1011571376 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 29368276446 ps |
CPU time | 695.98 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:56:32 PM PST 23 |
Peak memory | 356484 kb |
Host | smart-a0baf8a3-86b5-4166-8960-6148e563672f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011571376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.1011571376 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.2164554431 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 1930693118 ps |
CPU time | 66.22 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 12:45:52 PM PST 23 |
Peak memory | 336944 kb |
Host | smart-b29ba53b-22a1-4271-af3a-f150fab10aa4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164554431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2164554431 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3793324423 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 6070163231 ps |
CPU time | 400.06 seconds |
Started | Dec 27 12:44:58 PM PST 23 |
Finished | Dec 27 12:51:46 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-52f9a473-1f65-4e5a-9a92-bc57130b5117 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793324423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.3793324423 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.445634793 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 352919402 ps |
CPU time | 5.47 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:45:00 PM PST 23 |
Peak memory | 202340 kb |
Host | smart-89180f38-1377-4a52-8834-b0979862971a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445634793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.445634793 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.872531335 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 9581463939 ps |
CPU time | 682.68 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:56:35 PM PST 23 |
Peak memory | 377980 kb |
Host | smart-e9ae61e2-0c73-4e33-9dc7-1a4a23fca985 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872531335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.872531335 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.1023704842 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 2880303516 ps |
CPU time | 50.5 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:45:59 PM PST 23 |
Peak memory | 287120 kb |
Host | smart-80cc7a7a-2b48-4a8b-843f-bf805d2881b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023704842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1023704842 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.666388826 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 989291904935 ps |
CPU time | 6805.73 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 02:38:35 PM PST 23 |
Peak memory | 378032 kb |
Host | smart-3d88f39e-3542-4a37-90d4-af64867435a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666388826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_stress_all.666388826 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1456960443 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 1092212727 ps |
CPU time | 5685.28 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 02:19:49 PM PST 23 |
Peak memory | 758248 kb |
Host | smart-f94af13f-5d4f-42cb-82be-1d4657fb2742 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1456960443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1456960443 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.806254048 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 29105089214 ps |
CPU time | 207.12 seconds |
Started | Dec 27 12:45:19 PM PST 23 |
Finished | Dec 27 12:48:55 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-f1688d01-d4d6-421a-8f73-331e4da2f77d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806254048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sram_ctrl_stress_pipeline.806254048 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3974781558 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 3155555260 ps |
CPU time | 90.84 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:46:25 PM PST 23 |
Peak memory | 332956 kb |
Host | smart-25d61608-2482-4283-acd4-9dd1fa915e12 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974781558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3974781558 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1631200480 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 2264827186 ps |
CPU time | 202.99 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:48:36 PM PST 23 |
Peak memory | 342040 kb |
Host | smart-22597115-4ac9-42b7-a92b-924467b0b2d3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631200480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.1631200480 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.292343226 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 12661303 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:44:55 PM PST 23 |
Peak memory | 201716 kb |
Host | smart-11e2e02f-608d-46f6-b2af-613a3a1dfb56 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292343226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.292343226 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.1304085843 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 288102690617 ps |
CPU time | 1621.02 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 01:12:13 PM PST 23 |
Peak memory | 202044 kb |
Host | smart-4a8407e2-920a-4f3f-9b17-314a9592f609 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304085843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .1304085843 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.3922557054 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 9749159858 ps |
CPU time | 204.95 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 12:48:41 PM PST 23 |
Peak memory | 336056 kb |
Host | smart-0275a4b6-cdad-4663-89ff-990075595f50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922557054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3922557054 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.1061451698 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 17104102715 ps |
CPU time | 103.68 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:46:57 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-bf507784-92e6-4cd1-bd85-2363b45718e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061451698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.1061451698 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.2514956018 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 772085308 ps |
CPU time | 72.49 seconds |
Started | Dec 27 12:45:16 PM PST 23 |
Finished | Dec 27 12:46:36 PM PST 23 |
Peak memory | 308404 kb |
Host | smart-71c4252f-3916-4b3a-8668-90a7634b3558 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514956018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.2514956018 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3934656449 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 6198534935 ps |
CPU time | 139 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:47:32 PM PST 23 |
Peak memory | 211072 kb |
Host | smart-cafa31bb-b01c-4f17-95bd-479e6065f930 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934656449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.3934656449 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2499373909 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 10553175437 ps |
CPU time | 148.34 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 12:47:16 PM PST 23 |
Peak memory | 202060 kb |
Host | smart-44f8e099-31c5-4d24-9ae7-f37c5b59c9cf |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499373909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2499373909 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.2934730606 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 17851633839 ps |
CPU time | 785.26 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:57:56 PM PST 23 |
Peak memory | 365612 kb |
Host | smart-e1c00d02-16b9-45c5-8902-a6ec19b021a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934730606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.2934730606 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.802632602 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 6364133473 ps |
CPU time | 23.23 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 12:45:39 PM PST 23 |
Peak memory | 245968 kb |
Host | smart-22dd59ba-9f8c-4aad-aae1-a17498ed4b69 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802632602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s ram_ctrl_partial_access.802632602 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.613197654 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 65051416318 ps |
CPU time | 312.02 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:50:25 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-8928d804-02a4-4300-9b83-6ed6bb39ef2b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613197654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.sram_ctrl_partial_access_b2b.613197654 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.558327497 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 492821156 ps |
CPU time | 6.83 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 12:44:46 PM PST 23 |
Peak memory | 202228 kb |
Host | smart-8408e99e-cf1e-4ddc-aa16-28b32b9e9653 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558327497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.558327497 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.302114974 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 936551229 ps |
CPU time | 241.91 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:48:50 PM PST 23 |
Peak memory | 355420 kb |
Host | smart-ccc615b0-3b41-48b7-a9a2-996af3b48718 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302114974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.302114974 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.3408498109 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 768165496 ps |
CPU time | 68.24 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:46:16 PM PST 23 |
Peak memory | 309732 kb |
Host | smart-154ea1d6-f6fa-4ed0-a4da-8742b2f7e14a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408498109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3408498109 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.1417842385 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1013746143139 ps |
CPU time | 6646.85 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 02:35:48 PM PST 23 |
Peak memory | 385076 kb |
Host | smart-676b4336-ce82-4f8a-a117-48d7b73055b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417842385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.1417842385 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2080514658 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 5589538500 ps |
CPU time | 3900.74 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 01:49:47 PM PST 23 |
Peak memory | 628812 kb |
Host | smart-f6a0eb50-e1c6-449f-82d2-0011b8cdac7f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2080514658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2080514658 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3665030855 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 5633653454 ps |
CPU time | 198.07 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:48:21 PM PST 23 |
Peak memory | 202096 kb |
Host | smart-b9fa2dba-61c7-4259-afef-a8c5ee6a91d2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665030855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.3665030855 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1256904508 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 780161172 ps |
CPU time | 138.47 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:47:21 PM PST 23 |
Peak memory | 357368 kb |
Host | smart-45db0282-f940-4317-a3ce-317d624a9429 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256904508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1256904508 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1912404984 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 15499275391 ps |
CPU time | 1153.42 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 01:04:21 PM PST 23 |
Peak memory | 380048 kb |
Host | smart-12a02a8e-67f2-41d8-835a-400d148d10eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912404984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.1912404984 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.1869113373 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 15314625 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:44:59 PM PST 23 |
Peak memory | 201372 kb |
Host | smart-e0bbb814-34bd-4a38-99c8-f4b73f487e6c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869113373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1869113373 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.2819424810 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 138433936166 ps |
CPU time | 1194.1 seconds |
Started | Dec 27 12:44:43 PM PST 23 |
Finished | Dec 27 01:04:43 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-e9d4a2ea-f78d-49d1-8693-c8d227924c4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819424810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .2819424810 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.1982678891 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 11993406270 ps |
CPU time | 27.59 seconds |
Started | Dec 27 12:45:15 PM PST 23 |
Finished | Dec 27 12:45:50 PM PST 23 |
Peak memory | 213736 kb |
Host | smart-4ece7611-b228-426c-b056-b3f72e4ec5ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982678891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.1982678891 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.2792610010 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 721692594 ps |
CPU time | 44.23 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 12:45:49 PM PST 23 |
Peak memory | 280676 kb |
Host | smart-2c900c11-022c-491b-b3ae-5a29241c62fd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792610010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.2792610010 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3761732625 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 3102529452 ps |
CPU time | 130.43 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:47:03 PM PST 23 |
Peak memory | 214160 kb |
Host | smart-449429ca-ba07-48a4-8e16-80b4e5000b8c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761732625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3761732625 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.430880271 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 1977590857 ps |
CPU time | 124.06 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:47:12 PM PST 23 |
Peak memory | 201900 kb |
Host | smart-ccd7536f-36c5-438e-a6d7-6476adad1f90 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430880271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _mem_walk.430880271 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.2265966345 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 14102426309 ps |
CPU time | 1244.9 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 01:05:24 PM PST 23 |
Peak memory | 373852 kb |
Host | smart-d213f792-a841-42a6-8a2f-7787e9321759 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265966345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.2265966345 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3764249363 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 3850197389 ps |
CPU time | 16.8 seconds |
Started | Dec 27 12:45:03 PM PST 23 |
Finished | Dec 27 12:45:27 PM PST 23 |
Peak memory | 201980 kb |
Host | smart-8c87a385-1d16-4a77-9b0a-7f81dad9d70e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764249363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3764249363 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3875976839 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 11426094210 ps |
CPU time | 260.93 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:49:23 PM PST 23 |
Peak memory | 210296 kb |
Host | smart-490bacef-1ad4-429a-b914-e93dba2a5e33 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875976839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3875976839 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.2380107362 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 699318370 ps |
CPU time | 13.04 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:45:25 PM PST 23 |
Peak memory | 202276 kb |
Host | smart-b00a1f2c-67a1-4ec9-b9ed-b64f9230ef50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380107362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2380107362 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.3243402472 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 3366706367 ps |
CPU time | 2123.9 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 01:20:25 PM PST 23 |
Peak memory | 374876 kb |
Host | smart-268ae082-7d14-4bdc-a408-4cc6c32661b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243402472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3243402472 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.612029509 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 1788407456 ps |
CPU time | 159.26 seconds |
Started | Dec 27 12:44:58 PM PST 23 |
Finished | Dec 27 12:47:45 PM PST 23 |
Peak memory | 367584 kb |
Host | smart-4110c36c-3512-4438-ade9-ae8b3d80332f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612029509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.612029509 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.3530615083 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 177784933851 ps |
CPU time | 5756.26 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 02:20:50 PM PST 23 |
Peak memory | 380028 kb |
Host | smart-7d41d8d7-c433-405b-9d98-e486ce369833 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530615083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.3530615083 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.517560447 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 5970551044 ps |
CPU time | 4180.25 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 01:54:53 PM PST 23 |
Peak memory | 768232 kb |
Host | smart-65706d7b-ef3c-4f4f-8d91-f11efb39d834 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=517560447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.517560447 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2076071808 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 47524965189 ps |
CPU time | 347.27 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:50:51 PM PST 23 |
Peak memory | 202020 kb |
Host | smart-8cb31b04-7b27-40ee-9647-5e9c4d9baa72 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076071808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.2076071808 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.551118629 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 716815455 ps |
CPU time | 31.29 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:45:26 PM PST 23 |
Peak memory | 225892 kb |
Host | smart-d67c274f-3694-463a-a64b-09d6d6f90749 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551118629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.551118629 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3355288097 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 3834229857 ps |
CPU time | 333.25 seconds |
Started | Dec 27 12:44:42 PM PST 23 |
Finished | Dec 27 12:50:22 PM PST 23 |
Peak memory | 375968 kb |
Host | smart-e2760f25-92b1-4e80-8556-1c75ba278de9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355288097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.3355288097 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.945443206 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 13171635 ps |
CPU time | 0.61 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:44:58 PM PST 23 |
Peak memory | 201496 kb |
Host | smart-6e8e79dc-2967-4dc4-9422-3cb62400d7c0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945443206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.945443206 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.244063196 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 69153504087 ps |
CPU time | 1129.78 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 01:03:55 PM PST 23 |
Peak memory | 202068 kb |
Host | smart-c98e80ce-f6e9-432e-bb82-3c9daf5871c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244063196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 244063196 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.3725069881 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 38901566727 ps |
CPU time | 102.29 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:46:43 PM PST 23 |
Peak memory | 210320 kb |
Host | smart-5af41058-2798-4e04-99ee-a8d142072159 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725069881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.3725069881 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.1228664076 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 1561621494 ps |
CPU time | 91.49 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:46:25 PM PST 23 |
Peak memory | 324408 kb |
Host | smart-b06265fc-76d6-49d3-8a01-9f0af9d2c55a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228664076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.1228664076 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.409493396 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 3129168198 ps |
CPU time | 137.44 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:47:38 PM PST 23 |
Peak memory | 211140 kb |
Host | smart-42e8d19f-4700-48f9-9231-48cc5aec2723 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409493396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_mem_partial_access.409493396 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.63097409 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 13810769393 ps |
CPU time | 275.87 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:49:37 PM PST 23 |
Peak memory | 202240 kb |
Host | smart-145448cd-aade-49df-8334-b7f5dcd36527 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63097409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ mem_walk.63097409 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.343507287 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 10676970568 ps |
CPU time | 135.4 seconds |
Started | Dec 27 12:45:20 PM PST 23 |
Finished | Dec 27 12:47:44 PM PST 23 |
Peak memory | 357480 kb |
Host | smart-bfea5468-7482-487f-b5af-96cf8b543503 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343507287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip le_keys.343507287 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.1493680936 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 511760531 ps |
CPU time | 82.91 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:46:17 PM PST 23 |
Peak memory | 344112 kb |
Host | smart-106292b5-be76-40f0-ab40-99f0d4a4c52f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493680936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.1493680936 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3407230704 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 50506402793 ps |
CPU time | 321.73 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:50:05 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-00772823-202c-49f7-92d7-43c62b11b1d4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407230704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3407230704 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.959683552 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 364613501 ps |
CPU time | 6.42 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:45:21 PM PST 23 |
Peak memory | 202336 kb |
Host | smart-5f8f69a4-3255-4d02-a545-5f577aa27c0c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959683552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.959683552 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.3187107753 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 28752147047 ps |
CPU time | 757.77 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:57:47 PM PST 23 |
Peak memory | 369308 kb |
Host | smart-1d8f9dcd-2b08-4f72-8902-6c22fd4daaa5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187107753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3187107753 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.521602580 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 6140654977 ps |
CPU time | 87.94 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:46:47 PM PST 23 |
Peak memory | 323744 kb |
Host | smart-ac4c2601-c35c-442f-8619-924940553a6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521602580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.521602580 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.3841972006 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 538313556738 ps |
CPU time | 3774.76 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 01:48:00 PM PST 23 |
Peak memory | 380968 kb |
Host | smart-94c75db0-d5a7-4bb2-981d-969823e26aff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841972006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.3841972006 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.348567733 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 892869358 ps |
CPU time | 901.4 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 01:00:10 PM PST 23 |
Peak memory | 412292 kb |
Host | smart-3f301ca4-b975-4ff0-884f-81150b96bf8a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=348567733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.348567733 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1671489793 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 4174317942 ps |
CPU time | 307.46 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:50:10 PM PST 23 |
Peak memory | 210216 kb |
Host | smart-eb89891a-cb7c-46fd-a95b-5688136842b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671489793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.1671489793 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.819825437 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 2939491884 ps |
CPU time | 39.08 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:45:41 PM PST 23 |
Peak memory | 255040 kb |
Host | smart-1add8d92-0588-4e89-92ca-f7a661d7b470 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819825437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.819825437 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1688577229 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 11366010098 ps |
CPU time | 1277.06 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 01:06:29 PM PST 23 |
Peak memory | 377960 kb |
Host | smart-7dda6400-afdc-48b9-a61c-5a3dd3483270 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688577229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1688577229 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.1525818045 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 24274879 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:45:09 PM PST 23 |
Peak memory | 201288 kb |
Host | smart-f683d476-254d-4fe6-9c20-9066ef7bc244 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525818045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1525818045 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.4043569179 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 14762713866 ps |
CPU time | 1013.62 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 01:02:12 PM PST 23 |
Peak memory | 202076 kb |
Host | smart-e6cf5032-9d6f-4b31-b9f4-8c049cf8d879 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043569179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .4043569179 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.272219944 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 12633452036 ps |
CPU time | 120.69 seconds |
Started | Dec 27 12:45:11 PM PST 23 |
Finished | Dec 27 12:47:17 PM PST 23 |
Peak memory | 210304 kb |
Host | smart-02879a20-3238-4e34-a930-bd79a975c51b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272219944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esc alation.272219944 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.553251263 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 1379730726 ps |
CPU time | 27.73 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:45:30 PM PST 23 |
Peak memory | 213596 kb |
Host | smart-4d926a6e-f163-4bdf-a596-d9026e6f1b7e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553251263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_max_throughput.553251263 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2690898589 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 9403266103 ps |
CPU time | 80.63 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:46:29 PM PST 23 |
Peak memory | 211864 kb |
Host | smart-68af83f8-b4ab-4538-ab7e-b1d06c4ae8f9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690898589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.2690898589 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.2668826816 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 8233339266 ps |
CPU time | 124.82 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:47:05 PM PST 23 |
Peak memory | 202040 kb |
Host | smart-55854eb1-c1d6-4c5f-8e09-c1dc312c95a0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668826816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.2668826816 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.3035859122 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 9184467463 ps |
CPU time | 659.69 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:56:14 PM PST 23 |
Peak memory | 373052 kb |
Host | smart-2a8bf177-aad3-4f65-bf92-2088a7ce9069 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035859122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.3035859122 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.2962019001 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 903187762 ps |
CPU time | 36.7 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:45:40 PM PST 23 |
Peak memory | 201936 kb |
Host | smart-355e0dd1-9580-4d50-af0b-90cb9c74fc13 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962019001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.2962019001 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2282320364 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 252481685408 ps |
CPU time | 464.34 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:52:58 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-8bbf5c41-6bd0-4108-8044-c22236a29239 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282320364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.2282320364 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.3711375685 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 680028707 ps |
CPU time | 6.75 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:45:21 PM PST 23 |
Peak memory | 202364 kb |
Host | smart-7458dedf-9878-4752-8fcd-caba773d8e65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711375685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3711375685 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.192120421 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 3373675764 ps |
CPU time | 787.88 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:58:12 PM PST 23 |
Peak memory | 377940 kb |
Host | smart-70e7d7f4-8a54-4884-b381-db74ea73b379 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192120421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.192120421 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.657710738 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 1403980631 ps |
CPU time | 28.4 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:45:48 PM PST 23 |
Peak memory | 201936 kb |
Host | smart-95626366-8a27-4d02-b9f0-bb465cdee440 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657710738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.657710738 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.1577015620 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 27124413605 ps |
CPU time | 1553.13 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 01:10:54 PM PST 23 |
Peak memory | 376976 kb |
Host | smart-f7911448-404a-4ce2-82d7-8cf8a3d1fb26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577015620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.1577015620 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3263716595 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 812009205 ps |
CPU time | 3386.76 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 01:41:40 PM PST 23 |
Peak memory | 619832 kb |
Host | smart-48d77c40-4e1e-49e7-97fc-71b24115bad5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3263716595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3263716595 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.689783817 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 3325873159 ps |
CPU time | 234.54 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:49:10 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-555a632c-104b-4688-990b-ac55e4cd86ad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689783817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_stress_pipeline.689783817 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4181505424 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 5043905659 ps |
CPU time | 85.85 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:46:26 PM PST 23 |
Peak memory | 329828 kb |
Host | smart-bd3fbd97-6c6e-4d66-81de-33f29066f875 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181505424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.4181505424 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2730300917 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 37472135571 ps |
CPU time | 1425.33 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 01:09:05 PM PST 23 |
Peak memory | 376000 kb |
Host | smart-cfb9a2e6-0820-4099-b57f-be0eb050c0a4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730300917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.2730300917 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.3092101172 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 12368786 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:45:14 PM PST 23 |
Peak memory | 201284 kb |
Host | smart-459d21ef-5919-49bc-bfcd-afcd600f379e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092101172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3092101172 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.4286544882 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 31697592634 ps |
CPU time | 1175.11 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 01:04:43 PM PST 23 |
Peak memory | 202040 kb |
Host | smart-2dd510ec-eda5-4b02-b42d-026d6edc9daf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286544882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .4286544882 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.1617332382 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 8339087962 ps |
CPU time | 223.18 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:48:36 PM PST 23 |
Peak memory | 369716 kb |
Host | smart-a833f910-9c43-4d93-9f21-1701093e704e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617332382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1617332382 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.3493655733 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 2737124832 ps |
CPU time | 24.82 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:46:07 PM PST 23 |
Peak memory | 202136 kb |
Host | smart-a91523e5-50ff-4249-8136-01f4d1c843aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493655733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.3493655733 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.1712010471 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 2801839922 ps |
CPU time | 40.37 seconds |
Started | Dec 27 12:45:12 PM PST 23 |
Finished | Dec 27 12:45:58 PM PST 23 |
Peak memory | 261468 kb |
Host | smart-c7790768-895b-4d82-94dc-5d24da6043e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712010471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.1712010471 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1025399201 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 4797235586 ps |
CPU time | 77.59 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 12:46:24 PM PST 23 |
Peak memory | 218368 kb |
Host | smart-a82b7051-722d-4ceb-a370-a0f8d65861b9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025399201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.1025399201 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.4029865834 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 55080416425 ps |
CPU time | 295.31 seconds |
Started | Dec 27 12:45:12 PM PST 23 |
Finished | Dec 27 12:50:13 PM PST 23 |
Peak memory | 202244 kb |
Host | smart-31aeaabe-5b6b-4d9b-91ec-b647115e4493 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029865834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.4029865834 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.1716781796 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 71604118430 ps |
CPU time | 516.46 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 12:53:43 PM PST 23 |
Peak memory | 379032 kb |
Host | smart-99f2c644-d043-434d-978a-f1b04c47e073 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716781796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.1716781796 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.3311526411 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 1125466389 ps |
CPU time | 95.36 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:46:55 PM PST 23 |
Peak memory | 339868 kb |
Host | smart-a9090a52-827e-47b9-8fd1-8ccdbea12f9f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311526411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.3311526411 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.127367620 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 43584675501 ps |
CPU time | 538.76 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:54:13 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-188c7b28-df56-44e3-bbbf-f19935220154 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127367620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.sram_ctrl_partial_access_b2b.127367620 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.4009786541 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 36094350566 ps |
CPU time | 816.67 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:58:49 PM PST 23 |
Peak memory | 378932 kb |
Host | smart-32ad39df-8302-43c4-a8a0-6e18eaa44a68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009786541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.4009786541 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.3541133142 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 438285585 ps |
CPU time | 18.6 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:45:15 PM PST 23 |
Peak memory | 201908 kb |
Host | smart-fe9cf016-b978-476c-b59a-7a79d0f2057b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541133142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3541133142 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.282163630 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 1870851671 ps |
CPU time | 4079.38 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 01:53:20 PM PST 23 |
Peak memory | 572036 kb |
Host | smart-426b39c2-4d02-469c-8094-cd08f36ba91e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=282163630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.282163630 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1683798988 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2726762199 ps |
CPU time | 225.31 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:48:59 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-31d1d322-dd75-4535-a422-284dc92ae3c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683798988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.1683798988 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2583094349 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 3190660356 ps |
CPU time | 115.95 seconds |
Started | Dec 27 12:45:20 PM PST 23 |
Finished | Dec 27 12:47:25 PM PST 23 |
Peak memory | 344960 kb |
Host | smart-c403c479-c79f-4445-af6d-8b02ca1d7c62 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583094349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2583094349 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3954096053 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 9100030000 ps |
CPU time | 1240.96 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 01:06:02 PM PST 23 |
Peak memory | 363628 kb |
Host | smart-e694195a-bff6-4cef-9d68-541c0f06fc3e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954096053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.3954096053 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.4250863075 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 25009832 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 12:45:05 PM PST 23 |
Peak memory | 201740 kb |
Host | smart-0936df62-b524-42be-b530-a7abc0255dc4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250863075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.4250863075 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.2032185459 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 62866245136 ps |
CPU time | 571.74 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:54:30 PM PST 23 |
Peak memory | 202116 kb |
Host | smart-5ea0f8f4-9447-49cc-ae15-599048a32ce9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032185459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2032185459 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.2811762666 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 32900255934 ps |
CPU time | 165.2 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:47:59 PM PST 23 |
Peak memory | 210336 kb |
Host | smart-352fb272-7385-4180-bfa6-65fbb54f3477 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811762666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.2811762666 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.728315717 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 2982993476 ps |
CPU time | 116.94 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:47:12 PM PST 23 |
Peak memory | 342940 kb |
Host | smart-b75f2ccb-0c52-404a-ad3f-925a5cd642d4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728315717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.sram_ctrl_max_throughput.728315717 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3862490165 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 948140598 ps |
CPU time | 68.02 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:46:32 PM PST 23 |
Peak memory | 210908 kb |
Host | smart-410d43de-3c0e-4c9e-8f39-217733a90002 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862490165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.3862490165 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.559866385 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 4068392436 ps |
CPU time | 235.36 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:49:03 PM PST 23 |
Peak memory | 202060 kb |
Host | smart-1008bc59-3c89-4435-97dd-28c225acbc1f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559866385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.559866385 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.2917408215 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 5889010152 ps |
CPU time | 693.55 seconds |
Started | Dec 27 12:45:03 PM PST 23 |
Finished | Dec 27 12:56:44 PM PST 23 |
Peak memory | 380064 kb |
Host | smart-ca3b5bf3-e4ec-49ec-b0a7-43652e9e3f23 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917408215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.2917408215 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.3257685688 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 964648211 ps |
CPU time | 21.1 seconds |
Started | Dec 27 12:45:11 PM PST 23 |
Finished | Dec 27 12:45:37 PM PST 23 |
Peak memory | 250580 kb |
Host | smart-b547f914-5ec0-4cf4-a29f-80024e96f7d8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257685688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.3257685688 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.313832332 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 7103566303 ps |
CPU time | 169.65 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:47:58 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-0b189c21-d511-4ceb-9f65-8edd3a440d8c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313832332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.sram_ctrl_partial_access_b2b.313832332 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.2274662170 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 1412850786 ps |
CPU time | 6.49 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:45:03 PM PST 23 |
Peak memory | 202352 kb |
Host | smart-b42a7783-0260-4044-9c2c-03c104b75b62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274662170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2274662170 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.827859519 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 3124845202 ps |
CPU time | 114.66 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:47:14 PM PST 23 |
Peak memory | 299168 kb |
Host | smart-645bbda1-3ea5-4960-9a08-261c8036013b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827859519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.827859519 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.2068325789 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 3505463700 ps |
CPU time | 33.23 seconds |
Started | Dec 27 12:45:03 PM PST 23 |
Finished | Dec 27 12:45:43 PM PST 23 |
Peak memory | 289808 kb |
Host | smart-5dd31eed-5802-4da2-abe1-c9244ba2d71f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068325789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2068325789 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.3180375620 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 285583830170 ps |
CPU time | 3522.64 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 01:43:50 PM PST 23 |
Peak memory | 378952 kb |
Host | smart-23ba9b8e-f61d-4af7-ab92-564832d78e4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180375620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.3180375620 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.157806254 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 6801462251 ps |
CPU time | 4385.01 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 01:58:12 PM PST 23 |
Peak memory | 542896 kb |
Host | smart-52c2d74e-98cb-4fe2-9c08-b86428ebad78 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=157806254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.157806254 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1200398792 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 14265841797 ps |
CPU time | 279.29 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:49:48 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-2d00ed67-c8ad-4b24-baf1-6f9cbcc53443 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200398792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.1200398792 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1747283937 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 9099750730 ps |
CPU time | 64.93 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 12:46:21 PM PST 23 |
Peak memory | 288904 kb |
Host | smart-d84eac3c-b8c0-48d0-8e19-4cb93fc06597 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747283937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1747283937 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1458678178 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 13176601902 ps |
CPU time | 1987.23 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 01:17:39 PM PST 23 |
Peak memory | 380980 kb |
Host | smart-4033c20a-f4d8-4964-bafe-210c1e593935 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458678178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1458678178 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.3644351109 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 36472215 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 12:44:33 PM PST 23 |
Peak memory | 201808 kb |
Host | smart-0f7d2bfa-daad-46fd-8d31-8bdfc70b589e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644351109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3644351109 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.4218705960 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 119829416757 ps |
CPU time | 2607.49 seconds |
Started | Dec 27 12:44:24 PM PST 23 |
Finished | Dec 27 01:28:02 PM PST 23 |
Peak memory | 201976 kb |
Host | smart-6f5db083-4382-4549-997b-1b8e32562a4c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218705960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 4218705960 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.3808657840 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 33168981047 ps |
CPU time | 843.02 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:58:37 PM PST 23 |
Peak memory | 373940 kb |
Host | smart-7add55e3-6b0e-4049-bcfb-be3f93b37e47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808657840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.3808657840 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.3741402444 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 1493266203 ps |
CPU time | 85.18 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:46:24 PM PST 23 |
Peak memory | 312408 kb |
Host | smart-c70a7543-41af-417e-b142-bc7fea52d7e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741402444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3741402444 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2387864514 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 4977830918 ps |
CPU time | 146.49 seconds |
Started | Dec 27 12:44:18 PM PST 23 |
Finished | Dec 27 12:46:55 PM PST 23 |
Peak memory | 211468 kb |
Host | smart-dd7a824f-26c9-4cdf-b1b0-5c91e72bd8e5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387864514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.2387864514 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.2164151390 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 8232326271 ps |
CPU time | 120.3 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:46:38 PM PST 23 |
Peak memory | 201992 kb |
Host | smart-39703216-b21c-4d1a-ab61-196cbe019069 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164151390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.2164151390 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.2266749389 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 49281470952 ps |
CPU time | 299.54 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:49:41 PM PST 23 |
Peak memory | 327772 kb |
Host | smart-59c2f1df-d384-4b2a-ade7-1cf03c61ea6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266749389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2266749389 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.1590233031 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 725597912 ps |
CPU time | 30.82 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 12:45:10 PM PST 23 |
Peak memory | 218848 kb |
Host | smart-575a1bb4-ccc2-4a1b-b78a-d7c2fd799c8f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590233031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.1590233031 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3412768539 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 25332310487 ps |
CPU time | 301.98 seconds |
Started | Dec 27 12:44:24 PM PST 23 |
Finished | Dec 27 12:49:35 PM PST 23 |
Peak memory | 202100 kb |
Host | smart-e7985261-bbaa-4fe8-b953-27ac0309e6db |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412768539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.3412768539 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.2502942117 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 367860540 ps |
CPU time | 5.56 seconds |
Started | Dec 27 12:44:21 PM PST 23 |
Finished | Dec 27 12:44:35 PM PST 23 |
Peak memory | 202360 kb |
Host | smart-cc18202b-5f1f-42cf-9802-c7a59305e22d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502942117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2502942117 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.2212549556 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 9432688981 ps |
CPU time | 1123.32 seconds |
Started | Dec 27 12:44:52 PM PST 23 |
Finished | Dec 27 01:03:42 PM PST 23 |
Peak memory | 372864 kb |
Host | smart-d19b9bbf-321c-4dc4-8e3f-09aa08b31b9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212549556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2212549556 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.4089603100 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 225646445 ps |
CPU time | 2.92 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:44:44 PM PST 23 |
Peak memory | 220972 kb |
Host | smart-e5785cbd-a0fe-4ae1-88ad-2ad4727c6e52 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089603100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.4089603100 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.3909944595 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 3848967401 ps |
CPU time | 39.05 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 12:45:18 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-710723ee-a399-495f-8b16-1805c2ff620f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909944595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3909944595 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.721958015 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 423248841 ps |
CPU time | 1682.04 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 01:12:34 PM PST 23 |
Peak memory | 533548 kb |
Host | smart-ef25ca45-d3fa-49ab-adee-c72b03ef6cbd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=721958015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.721958015 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.915836824 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 9488285692 ps |
CPU time | 390.31 seconds |
Started | Dec 27 12:44:20 PM PST 23 |
Finished | Dec 27 12:51:00 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-74a8a2dc-11d0-4750-b0e8-99cb72c3df41 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915836824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.915836824 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.388805583 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 2928890904 ps |
CPU time | 36.29 seconds |
Started | Dec 27 12:44:18 PM PST 23 |
Finished | Dec 27 12:45:05 PM PST 23 |
Peak memory | 251124 kb |
Host | smart-0c5716eb-b3c3-49bd-9b97-ecc085244de2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388805583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.388805583 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4099726546 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 8883011871 ps |
CPU time | 1378.96 seconds |
Started | Dec 27 12:45:03 PM PST 23 |
Finished | Dec 27 01:08:10 PM PST 23 |
Peak memory | 377924 kb |
Host | smart-c75e15ef-b72a-46f9-8c46-b4f0c1cbd5af |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099726546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.4099726546 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.3418876639 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 17116981 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 12:45:12 PM PST 23 |
Peak memory | 201292 kb |
Host | smart-4f21f824-0eca-4eed-a7ba-c522d8d068b0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418876639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3418876639 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.1340069775 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 38492344808 ps |
CPU time | 1853.19 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 01:16:05 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-d6e06987-3395-4ebb-8316-12b190a7274d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340069775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .1340069775 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.2896577908 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 68240878145 ps |
CPU time | 875.42 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 12:59:57 PM PST 23 |
Peak memory | 361496 kb |
Host | smart-45a5e9ad-f038-46b7-94cb-8aa391ff59dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896577908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.2896577908 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.2497962771 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 42331828889 ps |
CPU time | 93.08 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 12:46:44 PM PST 23 |
Peak memory | 210280 kb |
Host | smart-da3d8aa2-a3e9-4900-8d79-7b69ff47c621 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497962771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.2497962771 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.1090307430 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 1557106741 ps |
CPU time | 99.54 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:46:52 PM PST 23 |
Peak memory | 341704 kb |
Host | smart-8b165f98-75c0-4958-9880-ee994f2f14ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090307430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.1090307430 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3684786581 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 967547216 ps |
CPU time | 71.5 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:46:06 PM PST 23 |
Peak memory | 210936 kb |
Host | smart-a9efd81b-e25f-498b-8e72-166304ebfb1c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684786581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.3684786581 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.2748668659 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 47143857995 ps |
CPU time | 154.18 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:47:36 PM PST 23 |
Peak memory | 202076 kb |
Host | smart-aff1431c-ebb3-47e1-b15e-45091ebbacde |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748668659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.2748668659 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.2583961787 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 4093161288 ps |
CPU time | 365.66 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:51:19 PM PST 23 |
Peak memory | 364632 kb |
Host | smart-5b9cf25a-1efb-4aee-b005-7c0eaa4560c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583961787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.2583961787 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.3762811044 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 520479322 ps |
CPU time | 8.29 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:45:21 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-58778a7b-1fe9-42ad-9c8b-37dd3b469552 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762811044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.3762811044 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2125727662 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 30546841460 ps |
CPU time | 357.03 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:51:10 PM PST 23 |
Peak memory | 201968 kb |
Host | smart-fa46df4a-7368-42b6-bc75-837f2f5c429e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125727662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.2125727662 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.3070989204 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 1345626628 ps |
CPU time | 5.28 seconds |
Started | Dec 27 12:45:05 PM PST 23 |
Finished | Dec 27 12:45:17 PM PST 23 |
Peak memory | 202204 kb |
Host | smart-d8ee34e2-9c38-4a0b-af66-0bd844fe0c8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070989204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3070989204 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.3988074542 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 57883601691 ps |
CPU time | 1008.03 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 01:01:56 PM PST 23 |
Peak memory | 366624 kb |
Host | smart-07e90546-77da-4daa-aa56-b1736e3843b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988074542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3988074542 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.2511238734 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 1420554795 ps |
CPU time | 23.16 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 12:45:55 PM PST 23 |
Peak memory | 201956 kb |
Host | smart-6d5abcb4-72f4-4f5b-8f96-ccf038cf3dc5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511238734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2511238734 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.1294821191 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 84632765316 ps |
CPU time | 613.4 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:55:08 PM PST 23 |
Peak memory | 370844 kb |
Host | smart-7e56547d-74bf-4c07-8dd7-dfc3ed0ecb3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294821191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.1294821191 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.398061209 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 394268856 ps |
CPU time | 1165.76 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 01:04:46 PM PST 23 |
Peak memory | 429972 kb |
Host | smart-a6489da9-cea9-4daf-8d89-b6e104095d9f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=398061209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.398061209 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2887769335 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 3501773750 ps |
CPU time | 223.32 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 12:49:15 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-a194e91b-6e16-4b42-82ad-7dbe25476450 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887769335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.2887769335 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1282039074 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 2990199888 ps |
CPU time | 75.77 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:46:35 PM PST 23 |
Peak memory | 319820 kb |
Host | smart-e7eec102-6d23-47e8-aa74-469225d74b67 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282039074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1282039074 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1203103023 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 30311419806 ps |
CPU time | 801.31 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 12:58:44 PM PST 23 |
Peak memory | 378928 kb |
Host | smart-c7aaf586-42ff-4768-9abd-67b566adb259 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203103023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.1203103023 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.1993772903 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 13959264 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:45:32 PM PST 23 |
Finished | Dec 27 12:45:41 PM PST 23 |
Peak memory | 201716 kb |
Host | smart-aa0f320b-ea55-4c82-873b-0f607b26848d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993772903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.1993772903 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.1645669127 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 50567248415 ps |
CPU time | 843.24 seconds |
Started | Dec 27 12:45:16 PM PST 23 |
Finished | Dec 27 12:59:26 PM PST 23 |
Peak memory | 201992 kb |
Host | smart-6e1fc2c6-70be-449d-b261-c7e6f49b40e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645669127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .1645669127 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.1288440858 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 13714324094 ps |
CPU time | 737.73 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:57:54 PM PST 23 |
Peak memory | 376896 kb |
Host | smart-e2b70394-04fa-4b09-8d86-9b6f4d4c71e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288440858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.1288440858 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.1917857104 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 20500417890 ps |
CPU time | 87.22 seconds |
Started | Dec 27 12:45:15 PM PST 23 |
Finished | Dec 27 12:46:49 PM PST 23 |
Peak memory | 213628 kb |
Host | smart-0c0e7ce5-b67d-4642-9b5e-9459df7568c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917857104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.1917857104 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.3577945382 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 1187425124 ps |
CPU time | 141.54 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:47:34 PM PST 23 |
Peak memory | 352384 kb |
Host | smart-52fdac6b-f67e-4515-914c-41074b929355 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577945382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.3577945382 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1488989147 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 4563555669 ps |
CPU time | 147.67 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:47:49 PM PST 23 |
Peak memory | 211072 kb |
Host | smart-38c13aca-a6cb-4208-ad6d-9c41967cadfd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488989147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.1488989147 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.2627547393 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 26534266870 ps |
CPU time | 274.78 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:49:50 PM PST 23 |
Peak memory | 202200 kb |
Host | smart-5b11bf04-8c51-492b-9f29-346aa162f0d3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627547393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.2627547393 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.656827450 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 22206593020 ps |
CPU time | 1417.68 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 01:08:58 PM PST 23 |
Peak memory | 376972 kb |
Host | smart-54de87ed-b5a6-40d9-bf13-03390c6f0606 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656827450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip le_keys.656827450 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.1661618363 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 1260838005 ps |
CPU time | 30.68 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:45:39 PM PST 23 |
Peak memory | 201924 kb |
Host | smart-04684e5e-2f61-419d-ae9d-ec693932837f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661618363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.1661618363 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2139575922 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 34615966476 ps |
CPU time | 421.56 seconds |
Started | Dec 27 12:44:52 PM PST 23 |
Finished | Dec 27 12:52:00 PM PST 23 |
Peak memory | 202020 kb |
Host | smart-cc86bc9a-dfc6-4e42-8ba3-7095a9acc349 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139575922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2139575922 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.750526869 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 362376093 ps |
CPU time | 5.27 seconds |
Started | Dec 27 12:45:03 PM PST 23 |
Finished | Dec 27 12:45:15 PM PST 23 |
Peak memory | 202184 kb |
Host | smart-36cfa767-0f4d-422d-8b2a-d81f36ee5981 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750526869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.750526869 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.3492836131 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 16629804370 ps |
CPU time | 1510.23 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 01:10:48 PM PST 23 |
Peak memory | 380016 kb |
Host | smart-d50ffeef-841f-42e2-9655-9a96adadc5bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492836131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3492836131 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.3523382799 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 4898626875 ps |
CPU time | 107.48 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:46:56 PM PST 23 |
Peak memory | 359528 kb |
Host | smart-159683de-f808-4be8-9b64-ef66470263a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523382799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3523382799 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.3525492016 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 587135004215 ps |
CPU time | 4384.29 seconds |
Started | Dec 27 12:45:41 PM PST 23 |
Finished | Dec 27 01:58:54 PM PST 23 |
Peak memory | 381120 kb |
Host | smart-cbf63069-a95e-475f-bb97-2b0b32e3f0a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525492016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.3525492016 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2851828425 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 2193752101 ps |
CPU time | 3018.9 seconds |
Started | Dec 27 12:45:25 PM PST 23 |
Finished | Dec 27 01:35:52 PM PST 23 |
Peak memory | 789600 kb |
Host | smart-6440846a-e4fa-4d8c-a39d-a75533af3745 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2851828425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2851828425 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2269496417 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 16522257132 ps |
CPU time | 251.27 seconds |
Started | Dec 27 12:44:48 PM PST 23 |
Finished | Dec 27 12:49:06 PM PST 23 |
Peak memory | 201992 kb |
Host | smart-e739605f-a66e-41e3-8f4f-a22a548bfc76 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269496417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.2269496417 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1181934150 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 1098062625 ps |
CPU time | 141.12 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:47:36 PM PST 23 |
Peak memory | 375176 kb |
Host | smart-deca2389-70f2-4ff6-b5f5-9e166adf96ad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181934150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1181934150 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2536313184 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 49194220673 ps |
CPU time | 1675.4 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 01:13:37 PM PST 23 |
Peak memory | 380000 kb |
Host | smart-da4cb2cf-382e-4343-a7ea-cb6020c5322f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536313184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.2536313184 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.3027281189 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 16476888 ps |
CPU time | 0.67 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 12:45:33 PM PST 23 |
Peak memory | 201780 kb |
Host | smart-bdf76d0b-4c06-4525-8abd-7b687352b89c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027281189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3027281189 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.2522953756 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 533467199109 ps |
CPU time | 2667.95 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 01:30:20 PM PST 23 |
Peak memory | 202060 kb |
Host | smart-3878714e-ddb7-4b50-a8f7-304cc8780aef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522953756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .2522953756 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.1819241452 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 29147851283 ps |
CPU time | 61.66 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:46:49 PM PST 23 |
Peak memory | 210328 kb |
Host | smart-11870b7b-c0a4-40d6-82e0-64f446ef7576 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819241452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1819241452 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.2429395081 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 2922323707 ps |
CPU time | 41.27 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:46:08 PM PST 23 |
Peak memory | 267452 kb |
Host | smart-517bd678-2319-4f34-9d86-b6e8aa7a4cb8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429395081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.2429395081 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2304411066 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 6459534101 ps |
CPU time | 133.84 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:47:48 PM PST 23 |
Peak memory | 211116 kb |
Host | smart-1d672f99-1597-4685-b340-75503092af75 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304411066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.2304411066 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3400255133 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 14066806268 ps |
CPU time | 285.71 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:50:23 PM PST 23 |
Peak memory | 202136 kb |
Host | smart-195bcb6e-2117-4a9b-bc30-aba4a9141a42 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400255133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3400255133 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.510300857 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 5623223234 ps |
CPU time | 27.43 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:46:02 PM PST 23 |
Peak memory | 202004 kb |
Host | smart-cfcc159f-1be5-40eb-8824-54e591d5643b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510300857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s ram_ctrl_partial_access.510300857 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2459269362 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 8688199187 ps |
CPU time | 269.68 seconds |
Started | Dec 27 12:45:12 PM PST 23 |
Finished | Dec 27 12:49:48 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-bd80cd1c-2edf-4854-91b7-3d09ffda9560 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459269362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2459269362 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.221658915 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 1351566596 ps |
CPU time | 12.97 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:45:54 PM PST 23 |
Peak memory | 202220 kb |
Host | smart-016cd801-d113-4f17-ac92-17afe79adb76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221658915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.221658915 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.2074791375 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 100348652107 ps |
CPU time | 1534.47 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 01:11:16 PM PST 23 |
Peak memory | 374828 kb |
Host | smart-28df6c11-8c78-4dab-94b7-84c8c0d64df3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074791375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2074791375 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.2103587874 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 1743831460 ps |
CPU time | 28.22 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:45:43 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-adb65be2-7862-44d4-8f45-f998bf3a437e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103587874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2103587874 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1008880673 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 206453348 ps |
CPU time | 2672.97 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 01:30:05 PM PST 23 |
Peak memory | 435852 kb |
Host | smart-d7363707-082b-43c2-b498-54deae18206c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1008880673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1008880673 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.65227840 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 15665705329 ps |
CPU time | 261.06 seconds |
Started | Dec 27 12:45:50 PM PST 23 |
Finished | Dec 27 12:50:18 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-bf96f389-53fa-426a-bb54-9630edf871f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65227840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_stress_pipeline.65227840 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1499346233 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 909084811 ps |
CPU time | 78.55 seconds |
Started | Dec 27 12:45:47 PM PST 23 |
Finished | Dec 27 12:47:14 PM PST 23 |
Peak memory | 316472 kb |
Host | smart-4ec5c82e-5b47-4ee1-81f9-869b5dbc3d14 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499346233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1499346233 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1921623507 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 6518574618 ps |
CPU time | 1453.7 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 01:09:48 PM PST 23 |
Peak memory | 374992 kb |
Host | smart-196daa42-ec84-4fff-b85a-013383a1abaf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921623507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.1921623507 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.982974853 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 48101574 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:45:15 PM PST 23 |
Peak memory | 201368 kb |
Host | smart-607232c3-e490-4414-a8a6-51e08c4ec71b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982974853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.982974853 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.2385673247 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 133764952290 ps |
CPU time | 2169.84 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 01:21:42 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-6c37c6c3-8de7-4600-bf99-58f5b0ad0287 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385673247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .2385673247 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.4015640790 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 54240550686 ps |
CPU time | 161.9 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 12:48:03 PM PST 23 |
Peak memory | 210244 kb |
Host | smart-b048d3c6-7af5-45e8-9120-02358db2be87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015640790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.4015640790 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.1013019973 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 3063326436 ps |
CPU time | 71.72 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:46:39 PM PST 23 |
Peak memory | 317028 kb |
Host | smart-5c3f3f0b-da3e-4d97-b3ba-6bfe327c4460 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013019973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.1013019973 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2909811083 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 3935259490 ps |
CPU time | 72.4 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:46:36 PM PST 23 |
Peak memory | 211100 kb |
Host | smart-8f4a61c5-f8d8-461c-a29f-212c63caf630 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909811083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2909811083 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.4039038805 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 14224765217 ps |
CPU time | 269.39 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 12:50:14 PM PST 23 |
Peak memory | 202228 kb |
Host | smart-4e5d9e39-3b5c-4a13-8887-86be2a5efb1c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039038805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.4039038805 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.3552076039 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 68518002186 ps |
CPU time | 729.07 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:57:33 PM PST 23 |
Peak memory | 370820 kb |
Host | smart-a9003bfe-ca08-498d-a84c-bce55a398d71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552076039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.3552076039 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.2658784558 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 1040943350 ps |
CPU time | 131.9 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 12:47:33 PM PST 23 |
Peak memory | 364348 kb |
Host | smart-4cd86923-48f8-4851-ab2d-ffd5cad76a9a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658784558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.2658784558 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1550894590 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 34522346104 ps |
CPU time | 556.37 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 12:55:01 PM PST 23 |
Peak memory | 202064 kb |
Host | smart-b71440c4-526c-4a9a-a82d-4a2ce2359359 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550894590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.1550894590 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.2866176633 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 1347981531 ps |
CPU time | 13.26 seconds |
Started | Dec 27 12:45:19 PM PST 23 |
Finished | Dec 27 12:45:41 PM PST 23 |
Peak memory | 202220 kb |
Host | smart-7633f22d-9235-4ada-b399-96d8f2376df9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866176633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2866176633 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.359835592 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 9024806910 ps |
CPU time | 567.74 seconds |
Started | Dec 27 12:45:32 PM PST 23 |
Finished | Dec 27 12:55:07 PM PST 23 |
Peak memory | 378920 kb |
Host | smart-58986ed3-d527-4182-a7eb-9b6707f09a68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359835592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.359835592 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.415445271 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 569750529 ps |
CPU time | 28.6 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:45:55 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-216e1082-a517-4792-b2b6-f0d2c175f3d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415445271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.415445271 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.3781491889 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 189035440885 ps |
CPU time | 5782.84 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 02:21:39 PM PST 23 |
Peak memory | 380996 kb |
Host | smart-5c9ecf50-4337-40f8-8be7-be6d636a4165 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781491889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.3781491889 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1662497597 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 318046069 ps |
CPU time | 2271.94 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 01:23:41 PM PST 23 |
Peak memory | 572648 kb |
Host | smart-9c1eae44-d22d-43c4-ab69-ba2ac8d3c2fb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1662497597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1662497597 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.411012613 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 3091276607 ps |
CPU time | 212.19 seconds |
Started | Dec 27 12:45:11 PM PST 23 |
Finished | Dec 27 12:48:48 PM PST 23 |
Peak memory | 202100 kb |
Host | smart-e6a69ae7-9912-4314-9ccc-8e723e984264 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411012613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_stress_pipeline.411012613 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.517620531 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 1409182480 ps |
CPU time | 31.36 seconds |
Started | Dec 27 12:45:12 PM PST 23 |
Finished | Dec 27 12:45:50 PM PST 23 |
Peak memory | 234740 kb |
Host | smart-34ebe6d8-437b-45cd-b345-26dc3e9f861e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517620531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.517620531 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.605057980 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 44744520393 ps |
CPU time | 762.34 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:58:19 PM PST 23 |
Peak memory | 370804 kb |
Host | smart-3d19c994-e374-42c3-8663-0b0254028ea3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605057980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 34.sram_ctrl_access_during_key_req.605057980 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.4268090722 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 24244096 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:45:43 PM PST 23 |
Peak memory | 201732 kb |
Host | smart-b0f3a7ae-1c62-4d7b-83b4-70178d6e4774 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268090722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.4268090722 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.3373366176 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 852664909756 ps |
CPU time | 2479.89 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 01:26:32 PM PST 23 |
Peak memory | 210260 kb |
Host | smart-73fd29d6-e438-43b9-ab78-5c94d3b2b635 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373366176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .3373366176 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.3461816001 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 56488270222 ps |
CPU time | 690.86 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:56:58 PM PST 23 |
Peak memory | 352468 kb |
Host | smart-d2057627-a980-4365-9dc4-827d2ebd3dbd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461816001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.3461816001 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.3681649507 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 774369320 ps |
CPU time | 154.24 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:48:17 PM PST 23 |
Peak memory | 366632 kb |
Host | smart-37f2a680-0f1b-41d5-b14e-13c0ce7068b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681649507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.3681649507 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3869833093 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 6438260837 ps |
CPU time | 129.23 seconds |
Started | Dec 27 12:45:15 PM PST 23 |
Finished | Dec 27 12:47:32 PM PST 23 |
Peak memory | 214284 kb |
Host | smart-c38b1555-a8b8-4cca-ae03-39d01b77b29b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869833093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.3869833093 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.1689540520 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 41265313360 ps |
CPU time | 298.35 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:50:29 PM PST 23 |
Peak memory | 202088 kb |
Host | smart-311e0fc0-db0e-4bf2-afc6-4022f6631f31 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689540520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.1689540520 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.217001312 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 2483507201 ps |
CPU time | 57.41 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 12:46:15 PM PST 23 |
Peak memory | 281644 kb |
Host | smart-13b0d5cb-563d-4d39-874f-fae27e1e9265 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217001312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip le_keys.217001312 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.1849941159 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 2852950044 ps |
CPU time | 30.17 seconds |
Started | Dec 27 12:45:03 PM PST 23 |
Finished | Dec 27 12:45:39 PM PST 23 |
Peak memory | 202084 kb |
Host | smart-23c47852-2089-4c96-88ec-961a01b98264 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849941159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.1849941159 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1934257220 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 4805220833 ps |
CPU time | 301.08 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:50:48 PM PST 23 |
Peak memory | 202048 kb |
Host | smart-d5fce225-90bf-406b-bd5f-f6245fe4809c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934257220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.1934257220 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.1730182998 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 355798368 ps |
CPU time | 13.35 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:45:40 PM PST 23 |
Peak memory | 202352 kb |
Host | smart-13790245-f159-4c20-846b-d6348138ddb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730182998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1730182998 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.3651707952 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 111272300685 ps |
CPU time | 479.58 seconds |
Started | Dec 27 12:45:16 PM PST 23 |
Finished | Dec 27 12:53:24 PM PST 23 |
Peak memory | 377892 kb |
Host | smart-2865ef09-3b13-41aa-87cc-580731fad06e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651707952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3651707952 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1901497039 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 15900218622 ps |
CPU time | 100.37 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:46:53 PM PST 23 |
Peak memory | 341316 kb |
Host | smart-38941d20-c797-421e-a47f-d471f7ef5eec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901497039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1901497039 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.413102386 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 4008578406 ps |
CPU time | 3960.22 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 01:51:45 PM PST 23 |
Peak memory | 688164 kb |
Host | smart-42eb95a3-1d73-4ac0-87a7-6728b14e623d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=413102386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.413102386 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4213230422 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 5128054497 ps |
CPU time | 172.6 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:48:40 PM PST 23 |
Peak memory | 202100 kb |
Host | smart-be6ae464-b89b-4eec-b36a-a77f3c51c7b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213230422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.4213230422 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3235825566 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 772205722 ps |
CPU time | 121.78 seconds |
Started | Dec 27 12:45:37 PM PST 23 |
Finished | Dec 27 12:47:47 PM PST 23 |
Peak memory | 343004 kb |
Host | smart-4863bc91-8617-42e7-b2c8-227f938a440c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235825566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3235825566 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3535045283 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 23088481194 ps |
CPU time | 1211.86 seconds |
Started | Dec 27 12:45:20 PM PST 23 |
Finished | Dec 27 01:05:41 PM PST 23 |
Peak memory | 377760 kb |
Host | smart-77c0a843-e86e-4449-9532-1c60d46f9237 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535045283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.3535045283 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2936152754 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 18860218 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:45:27 PM PST 23 |
Peak memory | 201732 kb |
Host | smart-721c79f5-5274-4ccc-a0c1-cad5a14c7fbb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936152754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2936152754 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.1654707195 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 575074949063 ps |
CPU time | 2336.26 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 01:24:31 PM PST 23 |
Peak memory | 201968 kb |
Host | smart-429ad0de-078e-4829-9510-93ac53a048a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654707195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .1654707195 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.335680707 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 3158367449 ps |
CPU time | 91.29 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 12:47:10 PM PST 23 |
Peak memory | 327812 kb |
Host | smart-8a2c307e-7cf6-4f67-9560-90b5b3a74035 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335680707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.sram_ctrl_max_throughput.335680707 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3954271906 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 10184610851 ps |
CPU time | 150.51 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:48:07 PM PST 23 |
Peak memory | 211040 kb |
Host | smart-77cdd2db-6082-4844-af76-c35a339afe2a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954271906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3954271906 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.425760351 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 3945632695 ps |
CPU time | 238.84 seconds |
Started | Dec 27 12:45:19 PM PST 23 |
Finished | Dec 27 12:49:27 PM PST 23 |
Peak memory | 201952 kb |
Host | smart-89342068-5682-4f9d-bfea-aef1f374c78b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425760351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _mem_walk.425760351 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3430352081 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 3078603066 ps |
CPU time | 45.73 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:46:29 PM PST 23 |
Peak memory | 297160 kb |
Host | smart-62cf9178-3f08-4a4e-84e8-9e9451e384f2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430352081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3430352081 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.910225541 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 17028849168 ps |
CPU time | 407.22 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:52:12 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-c5e1024b-7633-4321-bb41-799f6c48598d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910225541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.sram_ctrl_partial_access_b2b.910225541 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.3496124005 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 1410181653 ps |
CPU time | 5.66 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:45:48 PM PST 23 |
Peak memory | 202360 kb |
Host | smart-c751326e-014b-4c7d-b6dd-92fd0b0bc191 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496124005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3496124005 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.3948318098 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 1900152752 ps |
CPU time | 19.9 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:46:01 PM PST 23 |
Peak memory | 201936 kb |
Host | smart-9d540f9f-8543-4f82-a13d-bdbcf78a7270 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948318098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3948318098 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.62822635 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 1673835839561 ps |
CPU time | 2519.14 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 01:27:31 PM PST 23 |
Peak memory | 210288 kb |
Host | smart-81c1c448-f4b0-4ba1-9f18-e12fd613d16b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62822635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.sram_ctrl_stress_all.62822635 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.221807550 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 19473460139 ps |
CPU time | 5991.81 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 02:25:23 PM PST 23 |
Peak memory | 555696 kb |
Host | smart-af5210a0-d465-4247-961b-53f9820caa09 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=221807550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.221807550 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3739980497 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 8147194309 ps |
CPU time | 287.51 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:50:21 PM PST 23 |
Peak memory | 202132 kb |
Host | smart-9813abb9-f11f-4a90-af25-d1e1f4f93008 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739980497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.3739980497 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4009084615 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 812962208 ps |
CPU time | 166.24 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 12:48:33 PM PST 23 |
Peak memory | 375136 kb |
Host | smart-6f46c5a3-f957-465b-90b4-456a2c34c76e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009084615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.4009084615 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.945623350 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 8149261936 ps |
CPU time | 992.04 seconds |
Started | Dec 27 12:45:35 PM PST 23 |
Finished | Dec 27 01:02:16 PM PST 23 |
Peak memory | 373588 kb |
Host | smart-3e217c8e-d698-4846-9740-930604aa3e9e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945623350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 36.sram_ctrl_access_during_key_req.945623350 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.1316422126 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 16938853 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:45:32 PM PST 23 |
Peak memory | 201316 kb |
Host | smart-6c12550b-4737-4ba6-8e9e-37930af667b8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316422126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1316422126 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.3507432777 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 625081005281 ps |
CPU time | 2043.82 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 01:19:41 PM PST 23 |
Peak memory | 201936 kb |
Host | smart-e91a90de-d142-41d7-9b47-33ea3ac9ebf5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507432777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .3507432777 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.26382413 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 11978611446 ps |
CPU time | 1053.98 seconds |
Started | Dec 27 12:45:50 PM PST 23 |
Finished | Dec 27 01:03:31 PM PST 23 |
Peak memory | 376884 kb |
Host | smart-1099dbd7-91f3-413e-a8e1-64babfa36815 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26382413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable .26382413 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.410387399 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 695247054 ps |
CPU time | 28.01 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:46:05 PM PST 23 |
Peak memory | 210280 kb |
Host | smart-c5f5f675-c7bf-4490-8a54-dae9cc527df4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410387399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.sram_ctrl_max_throughput.410387399 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2104486000 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 9983825987 ps |
CPU time | 147.06 seconds |
Started | Dec 27 12:45:55 PM PST 23 |
Finished | Dec 27 12:48:33 PM PST 23 |
Peak memory | 218432 kb |
Host | smart-c6e83196-84a6-430c-9d37-480551e3ab7a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104486000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2104486000 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.4254699039 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 57379870779 ps |
CPU time | 308.58 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 12:50:55 PM PST 23 |
Peak memory | 202256 kb |
Host | smart-94c591d4-9074-4474-a01e-4d96a36d3380 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254699039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.4254699039 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.1733175862 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 40730044525 ps |
CPU time | 295.44 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 12:50:11 PM PST 23 |
Peak memory | 335996 kb |
Host | smart-27f7da21-97c0-4a73-b7e2-2af5b49c58a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733175862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.1733175862 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.909039458 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 2470687715 ps |
CPU time | 22.09 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:45:56 PM PST 23 |
Peak memory | 201936 kb |
Host | smart-c0fcc7fc-d98a-4237-a871-1f8b7eb76bd7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909039458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s ram_ctrl_partial_access.909039458 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3382042705 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 13168885534 ps |
CPU time | 204.9 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:49:13 PM PST 23 |
Peak memory | 202112 kb |
Host | smart-3676fcea-4488-4d7f-886e-e94213de073d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382042705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.3382042705 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.785804904 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 368505856 ps |
CPU time | 6.24 seconds |
Started | Dec 27 12:45:24 PM PST 23 |
Finished | Dec 27 12:45:39 PM PST 23 |
Peak memory | 202392 kb |
Host | smart-bf9b2215-57a9-4120-a950-86594347894b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785804904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.785804904 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.3668115857 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 47438034853 ps |
CPU time | 892.35 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 01:00:45 PM PST 23 |
Peak memory | 375840 kb |
Host | smart-205c5a65-67e8-404a-b885-40df8d88043f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668115857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3668115857 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.4184452375 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 2408524716 ps |
CPU time | 77.21 seconds |
Started | Dec 27 12:45:43 PM PST 23 |
Finished | Dec 27 12:47:08 PM PST 23 |
Peak memory | 328912 kb |
Host | smart-01063c66-442a-4ba2-98ca-fa8469271947 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184452375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.4184452375 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.664483993 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 3684756074 ps |
CPU time | 3194.65 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 01:39:02 PM PST 23 |
Peak memory | 519284 kb |
Host | smart-7ef0d32d-3a42-4aea-86f0-beb18ffdd06b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=664483993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.664483993 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3714175986 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 11463226934 ps |
CPU time | 415.04 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 12:52:44 PM PST 23 |
Peak memory | 202044 kb |
Host | smart-9049ce24-1eec-4eaf-9c06-acd518471921 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714175986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.3714175986 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3312187471 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 734323392 ps |
CPU time | 36.54 seconds |
Started | Dec 27 12:45:55 PM PST 23 |
Finished | Dec 27 12:46:42 PM PST 23 |
Peak memory | 253100 kb |
Host | smart-82932470-6df9-44b4-8d50-5c647acaa533 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312187471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.3312187471 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2375543862 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 10407637732 ps |
CPU time | 1150.3 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 01:04:32 PM PST 23 |
Peak memory | 380216 kb |
Host | smart-c021230e-5750-4a12-9cca-edda9f29ffe0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375543862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.2375543862 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.1453094778 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 34463524 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:45:35 PM PST 23 |
Peak memory | 201708 kb |
Host | smart-a3593e18-b319-4668-b910-d5a49b915af5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453094778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1453094778 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.2990069686 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 99681824883 ps |
CPU time | 1195.94 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 01:05:45 PM PST 23 |
Peak memory | 202072 kb |
Host | smart-c6e020c1-d18b-4067-a35d-9567df7ba57a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990069686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .2990069686 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.3176773731 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 5096306178 ps |
CPU time | 55.81 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:46:15 PM PST 23 |
Peak memory | 210328 kb |
Host | smart-4dfcd005-58c7-47b2-a1e1-b3abc308f14d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176773731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.3176773731 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.4013104064 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 1422422795 ps |
CPU time | 51.15 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:46:22 PM PST 23 |
Peak memory | 274616 kb |
Host | smart-04394ca4-291c-4682-b5fa-8e699ee5cbc9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013104064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.4013104064 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.390688770 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 4613556148 ps |
CPU time | 147.8 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:48:01 PM PST 23 |
Peak memory | 210988 kb |
Host | smart-52546e77-de52-4c58-b4f9-e53ad153542a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390688770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.390688770 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.2084188023 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 3347966749 ps |
CPU time | 118.05 seconds |
Started | Dec 27 12:45:54 PM PST 23 |
Finished | Dec 27 12:48:03 PM PST 23 |
Peak memory | 201972 kb |
Host | smart-e51fbbe2-856a-4b25-bdf7-0ea979708358 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084188023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.2084188023 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.4196247663 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 4010558741 ps |
CPU time | 734.56 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:57:28 PM PST 23 |
Peak memory | 378916 kb |
Host | smart-41c1540c-e418-4d30-bf6d-9915293cd8d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196247663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.4196247663 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.3326415669 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 2654169307 ps |
CPU time | 129.03 seconds |
Started | Dec 27 12:45:11 PM PST 23 |
Finished | Dec 27 12:47:25 PM PST 23 |
Peak memory | 360500 kb |
Host | smart-08d0bdd6-7c7f-4678-9af6-ccddeb41b6e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326415669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.3326415669 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.894976122 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 14217826065 ps |
CPU time | 336.39 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:51:19 PM PST 23 |
Peak memory | 201928 kb |
Host | smart-212ae2e4-2c9e-4117-9c55-3a5d63bcc170 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894976122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.sram_ctrl_partial_access_b2b.894976122 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.1007739048 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 718355783 ps |
CPU time | 14.26 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:45:56 PM PST 23 |
Peak memory | 202244 kb |
Host | smart-ec0baeb2-909b-4afe-a2c8-d5c77af3f4b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007739048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1007739048 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3337113167 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 87165559800 ps |
CPU time | 1707.08 seconds |
Started | Dec 27 12:45:35 PM PST 23 |
Finished | Dec 27 01:14:17 PM PST 23 |
Peak memory | 377964 kb |
Host | smart-4daabb0d-c7c3-472a-8030-d72aab697904 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337113167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3337113167 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.497866888 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 1044295518 ps |
CPU time | 27.58 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 12:46:17 PM PST 23 |
Peak memory | 264308 kb |
Host | smart-39857a52-4e6b-4d69-b709-880cce1803a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497866888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.497866888 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.3817641901 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 323268563019 ps |
CPU time | 4960.53 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 02:08:28 PM PST 23 |
Peak memory | 382708 kb |
Host | smart-2bf5968a-5642-46c5-85dd-4b2b1b0ec792 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817641901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.3817641901 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2694970619 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 6751917860 ps |
CPU time | 4324.99 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 01:57:50 PM PST 23 |
Peak memory | 685360 kb |
Host | smart-7f23636a-0958-4975-b68c-77a6661e230c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2694970619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2694970619 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1001601917 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 6161166832 ps |
CPU time | 444.4 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:53:06 PM PST 23 |
Peak memory | 202040 kb |
Host | smart-c0620b93-b94c-426b-bb47-0e4a58674e86 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001601917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.1001601917 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3756092448 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 3248628265 ps |
CPU time | 42.38 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:46:14 PM PST 23 |
Peak memory | 267528 kb |
Host | smart-3786c5b8-2346-4c10-992d-65078ecf24d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756092448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3756092448 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2083604985 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 20381301376 ps |
CPU time | 1304.74 seconds |
Started | Dec 27 12:45:16 PM PST 23 |
Finished | Dec 27 01:07:08 PM PST 23 |
Peak memory | 378040 kb |
Host | smart-da1c6318-d3c6-419e-a374-a09a09c041e7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083604985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.2083604985 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.3924590820 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 43212471 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:45:35 PM PST 23 |
Peak memory | 201388 kb |
Host | smart-510a2e8a-2ae5-4ff4-832b-a82a71705094 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924590820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3924590820 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2173137218 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 86496140211 ps |
CPU time | 1337.66 seconds |
Started | Dec 27 12:45:52 PM PST 23 |
Finished | Dec 27 01:08:17 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-4660fd6f-1323-4d93-8758-3093a6179bfa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173137218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2173137218 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.3301312656 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 105101280510 ps |
CPU time | 1522.64 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 01:11:09 PM PST 23 |
Peak memory | 372760 kb |
Host | smart-9859a425-22e2-4c40-87e6-d1acf5c394d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301312656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.3301312656 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.3758771179 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 22202539718 ps |
CPU time | 120.42 seconds |
Started | Dec 27 12:45:20 PM PST 23 |
Finished | Dec 27 12:47:29 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-60106a57-67aa-4546-bac3-c739c70c23a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758771179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.3758771179 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.3711839081 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 775282528 ps |
CPU time | 77.44 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:46:48 PM PST 23 |
Peak memory | 332976 kb |
Host | smart-fd8370cc-ff90-4ecd-bfd0-692ca22d6b86 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711839081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.3711839081 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.560408552 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 1971989682 ps |
CPU time | 74.1 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:46:29 PM PST 23 |
Peak memory | 218304 kb |
Host | smart-f734d60f-be28-4b3f-b9bb-dd16d13e2ae7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560408552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_mem_partial_access.560408552 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.3388368146 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 275576859545 ps |
CPU time | 305.8 seconds |
Started | Dec 27 12:45:19 PM PST 23 |
Finished | Dec 27 12:50:33 PM PST 23 |
Peak memory | 202148 kb |
Host | smart-b5da1e54-3289-4e9c-b00a-799986d6d496 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388368146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.3388368146 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.1878460661 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 51939590100 ps |
CPU time | 1330.43 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 01:07:47 PM PST 23 |
Peak memory | 374652 kb |
Host | smart-845b51d8-0329-42f8-8174-9d3b83302dbf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878460661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.1878460661 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.3991148267 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 999235274 ps |
CPU time | 15.56 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 12:46:07 PM PST 23 |
Peak memory | 243740 kb |
Host | smart-fc069749-57c4-4884-b78f-000b41a76740 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991148267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.3991148267 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1659818908 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 15531389476 ps |
CPU time | 362.96 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:51:46 PM PST 23 |
Peak memory | 210260 kb |
Host | smart-1fd6b26e-6db0-4b79-8564-24d32f5e71d8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659818908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.1659818908 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.1968717061 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 1411613212 ps |
CPU time | 5.95 seconds |
Started | Dec 27 12:45:19 PM PST 23 |
Finished | Dec 27 12:45:35 PM PST 23 |
Peak memory | 202256 kb |
Host | smart-59dcdf2d-ed11-409c-913c-7dd210bd4d59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968717061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1968717061 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.2327732835 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 4600685710 ps |
CPU time | 56.94 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 12:46:17 PM PST 23 |
Peak memory | 205592 kb |
Host | smart-fdb3e8a2-6542-4d05-873f-203e910e4ddb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327732835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2327732835 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.42515451 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 1174974352 ps |
CPU time | 160.72 seconds |
Started | Dec 27 12:45:46 PM PST 23 |
Finished | Dec 27 12:48:35 PM PST 23 |
Peak memory | 369648 kb |
Host | smart-72745ddb-97c1-4aea-bcc5-0ad752a42cfd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42515451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.42515451 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.1980348616 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 646137274917 ps |
CPU time | 5963.68 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 02:24:55 PM PST 23 |
Peak memory | 381088 kb |
Host | smart-f807c206-e0ef-4634-b21f-651b98993962 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980348616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.1980348616 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.204932823 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 218807450 ps |
CPU time | 2120.03 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 01:21:01 PM PST 23 |
Peak memory | 467572 kb |
Host | smart-beb63bae-9047-4252-95d0-27638e246ec1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=204932823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.204932823 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3137626821 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 4589715029 ps |
CPU time | 343.58 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:51:19 PM PST 23 |
Peak memory | 202028 kb |
Host | smart-252f2cd5-250e-43e9-9711-a33ea4d92d27 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137626821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.3137626821 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2973498590 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 4560485166 ps |
CPU time | 61.9 seconds |
Started | Dec 27 12:45:52 PM PST 23 |
Finished | Dec 27 12:47:04 PM PST 23 |
Peak memory | 291432 kb |
Host | smart-b2a8221e-9656-419f-9496-f8c86a1ed007 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973498590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2973498590 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.483723805 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 31496881738 ps |
CPU time | 988.01 seconds |
Started | Dec 27 12:45:35 PM PST 23 |
Finished | Dec 27 01:02:12 PM PST 23 |
Peak memory | 374896 kb |
Host | smart-8c143dd3-dd08-4d7a-9291-e73d7de29705 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483723805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.483723805 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3241659177 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 10786223 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:45:36 PM PST 23 |
Peak memory | 201836 kb |
Host | smart-0382a013-a263-4c6a-8e1e-9ef6e749582a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241659177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3241659177 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.699752055 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 126816940685 ps |
CPU time | 2027.61 seconds |
Started | Dec 27 12:45:16 PM PST 23 |
Finished | Dec 27 01:19:11 PM PST 23 |
Peak memory | 210196 kb |
Host | smart-3585ec93-01b8-4c1b-9185-aa5818c9f66a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699752055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection. 699752055 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.4262107223 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 10000619071 ps |
CPU time | 370.99 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 12:51:49 PM PST 23 |
Peak memory | 354240 kb |
Host | smart-954224fe-3a49-40fa-9044-d478109673a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262107223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.4262107223 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.2707998946 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 6074584080 ps |
CPU time | 74.77 seconds |
Started | Dec 27 12:45:42 PM PST 23 |
Finished | Dec 27 12:47:05 PM PST 23 |
Peak memory | 202100 kb |
Host | smart-0d2577e3-fe31-41bb-ae58-26d48b31b07f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707998946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.2707998946 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.4151216145 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 695297577 ps |
CPU time | 29.64 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:45:49 PM PST 23 |
Peak memory | 217744 kb |
Host | smart-65bc573b-3c73-41a2-8be5-974b9829cc5b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151216145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.4151216145 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3467484785 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 5781750167 ps |
CPU time | 133.37 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:47:56 PM PST 23 |
Peak memory | 211152 kb |
Host | smart-189b1f70-bcac-42ed-b8b8-7127a736f2f9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467484785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.3467484785 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.464612743 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 68955852644 ps |
CPU time | 170.14 seconds |
Started | Dec 27 12:45:09 PM PST 23 |
Finished | Dec 27 12:48:05 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-b714414f-0910-4d8a-b3c8-040abe89efa7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464612743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _mem_walk.464612743 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.3157225199 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 10465832248 ps |
CPU time | 391.43 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:51:59 PM PST 23 |
Peak memory | 377348 kb |
Host | smart-c4ddec6d-1926-4c77-b46a-49106cdee7d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157225199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.3157225199 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.433889923 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 11276392668 ps |
CPU time | 30.86 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:45:56 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-b2b222bd-09d2-4796-b50b-d752930cee78 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433889923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s ram_ctrl_partial_access.433889923 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3450760331 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 6350275689 ps |
CPU time | 388.51 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 12:52:17 PM PST 23 |
Peak memory | 202044 kb |
Host | smart-b93c77a5-4cc3-434e-a8f4-6741e907e511 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450760331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.3450760331 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.2899169448 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 1354816233 ps |
CPU time | 13.58 seconds |
Started | Dec 27 12:45:15 PM PST 23 |
Finished | Dec 27 12:45:36 PM PST 23 |
Peak memory | 202260 kb |
Host | smart-b7458b89-3e49-466a-8a48-40611bc5d68b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899169448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2899169448 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.950674122 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 84695700053 ps |
CPU time | 1654.73 seconds |
Started | Dec 27 12:45:48 PM PST 23 |
Finished | Dec 27 01:13:31 PM PST 23 |
Peak memory | 380096 kb |
Host | smart-3f1b8d44-4558-4559-9c66-58c8da385adc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950674122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.950674122 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.3436357733 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 3183011089 ps |
CPU time | 27.01 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:46:01 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-b8d927dd-16ec-4764-9d14-c83ec8e60c89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436357733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3436357733 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.2876449275 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 204794726836 ps |
CPU time | 2298.74 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 01:24:01 PM PST 23 |
Peak memory | 381104 kb |
Host | smart-224e5985-4aca-4a5d-9135-bdec05b0fab3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876449275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2876449275 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3898756100 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 1776530329 ps |
CPU time | 5158.31 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 02:11:32 PM PST 23 |
Peak memory | 677064 kb |
Host | smart-573d2f98-e4fb-4593-806f-ebc2dc879a97 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3898756100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3898756100 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1844087603 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 5682898449 ps |
CPU time | 373.01 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:52:00 PM PST 23 |
Peak memory | 201936 kb |
Host | smart-dbd45187-e444-476a-9f80-8be8ff7f1d38 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844087603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1844087603 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.274385650 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 791805956 ps |
CPU time | 154.93 seconds |
Started | Dec 27 12:45:06 PM PST 23 |
Finished | Dec 27 12:47:48 PM PST 23 |
Peak memory | 356428 kb |
Host | smart-832b2b8b-b7f5-4d1a-a044-463ab8936ea0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274385650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.274385650 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1132084907 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 20103302492 ps |
CPU time | 666.54 seconds |
Started | Dec 27 12:44:31 PM PST 23 |
Finished | Dec 27 12:55:46 PM PST 23 |
Peak memory | 378012 kb |
Host | smart-5431770a-f16b-4ea7-8fdb-5e000d10ef5e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132084907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.1132084907 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.2130681792 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 14449386 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:44:53 PM PST 23 |
Peak memory | 201788 kb |
Host | smart-246d8897-fd71-4355-8cc1-bab236c32b22 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130681792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2130681792 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.2699322184 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 43293133287 ps |
CPU time | 680.23 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:56:33 PM PST 23 |
Peak memory | 202152 kb |
Host | smart-1ad25941-b57e-468d-bf7c-79f1bb423a78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699322184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 2699322184 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.3116758167 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 5677258266 ps |
CPU time | 348.41 seconds |
Started | Dec 27 12:44:46 PM PST 23 |
Finished | Dec 27 12:50:40 PM PST 23 |
Peak memory | 375844 kb |
Host | smart-fdbc17ee-0766-486e-899f-73f5fd2be4f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116758167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.3116758167 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.1093104476 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 9153901239 ps |
CPU time | 104.42 seconds |
Started | Dec 27 12:44:52 PM PST 23 |
Finished | Dec 27 12:46:43 PM PST 23 |
Peak memory | 210332 kb |
Host | smart-69f6ade1-3a57-424f-a3e7-912e91fb0630 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093104476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.1093104476 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.2045939117 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 881687155 ps |
CPU time | 42.6 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:45:45 PM PST 23 |
Peak memory | 267496 kb |
Host | smart-d0040293-8b20-4d21-b034-62209106bb51 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045939117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.2045939117 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2726496664 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 17401778374 ps |
CPU time | 152.92 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:47:26 PM PST 23 |
Peak memory | 211112 kb |
Host | smart-c8acb390-b7e9-42ef-b79b-d9a97e721c83 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726496664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2726496664 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.2450532092 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 10754812733 ps |
CPU time | 155.41 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:47:06 PM PST 23 |
Peak memory | 202088 kb |
Host | smart-51ccc3f8-fb72-4afa-aca2-f05612359f72 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450532092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2450532092 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.509764148 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 20978261736 ps |
CPU time | 798.61 seconds |
Started | Dec 27 12:44:20 PM PST 23 |
Finished | Dec 27 12:57:48 PM PST 23 |
Peak memory | 368660 kb |
Host | smart-d0620a6e-efe8-40f4-9f18-ecccf4671518 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509764148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.509764148 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.2858932030 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 4218777661 ps |
CPU time | 18.75 seconds |
Started | Dec 27 12:44:32 PM PST 23 |
Finished | Dec 27 12:45:00 PM PST 23 |
Peak memory | 202068 kb |
Host | smart-7b7f74a8-69d3-4233-bab6-724efb230e63 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858932030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.2858932030 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2945612535 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 86282462941 ps |
CPU time | 241.16 seconds |
Started | Dec 27 12:44:20 PM PST 23 |
Finished | Dec 27 12:48:31 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-adce5b81-9086-48f4-a64d-db043a020ec0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945612535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.2945612535 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.287934574 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 737213931 ps |
CPU time | 13.63 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:45:07 PM PST 23 |
Peak memory | 202368 kb |
Host | smart-cfe2d274-8fef-4128-83b5-6b7ed2f50f59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287934574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.287934574 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.681070009 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 25325167723 ps |
CPU time | 480.77 seconds |
Started | Dec 27 12:45:05 PM PST 23 |
Finished | Dec 27 12:53:12 PM PST 23 |
Peak memory | 369712 kb |
Host | smart-86ef04f8-cbdf-4dbd-badc-1641eabdba80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681070009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.681070009 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.2565391798 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 3719646230 ps |
CPU time | 3.38 seconds |
Started | Dec 27 12:44:29 PM PST 23 |
Finished | Dec 27 12:44:42 PM PST 23 |
Peak memory | 221740 kb |
Host | smart-eebe1a6b-61e1-4a96-830e-deb07ad72fcb |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565391798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2565391798 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.533094210 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 9587080145 ps |
CPU time | 102.73 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 12:46:40 PM PST 23 |
Peak memory | 350464 kb |
Host | smart-a3718d01-5b5c-49ee-a466-05b88667dd07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533094210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.533094210 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1622037090 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 5074030434 ps |
CPU time | 2216.98 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 01:21:31 PM PST 23 |
Peak memory | 489756 kb |
Host | smart-2ceec257-9fea-41e9-b65d-927bd5912d85 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1622037090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1622037090 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.351012709 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 10183453149 ps |
CPU time | 288.74 seconds |
Started | Dec 27 12:44:16 PM PST 23 |
Finished | Dec 27 12:49:16 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-913d83a4-4641-4355-8b34-eec6730daf0e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351012709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_stress_pipeline.351012709 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1051332817 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 2882378961 ps |
CPU time | 118.48 seconds |
Started | Dec 27 12:44:17 PM PST 23 |
Finished | Dec 27 12:46:26 PM PST 23 |
Peak memory | 362644 kb |
Host | smart-d685d6c7-29d2-46bb-b37c-8184e792f72b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051332817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1051332817 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3757360536 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 6257819439 ps |
CPU time | 323.18 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:50:49 PM PST 23 |
Peak memory | 351336 kb |
Host | smart-df5334e1-284f-4bd6-bc9d-962cac8789df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757360536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.3757360536 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.1944982561 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 184624410 ps |
CPU time | 0.68 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 12:45:32 PM PST 23 |
Peak memory | 201708 kb |
Host | smart-e3758f87-fc07-40a7-8a28-929e418d6892 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944982561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1944982561 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.2645413260 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 145553428876 ps |
CPU time | 2525.59 seconds |
Started | Dec 27 12:45:37 PM PST 23 |
Finished | Dec 27 01:27:51 PM PST 23 |
Peak memory | 202056 kb |
Host | smart-f06e69ab-4b1f-43b3-87c6-b33ffe2711e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645413260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .2645413260 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.555213065 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1755187527 ps |
CPU time | 213.67 seconds |
Started | Dec 27 12:45:15 PM PST 23 |
Finished | Dec 27 12:48:56 PM PST 23 |
Peak memory | 372804 kb |
Host | smart-03864bbd-409e-4d49-96ee-1b5c68e07ad4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555213065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl e.555213065 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.217394880 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 13833186756 ps |
CPU time | 46.83 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:46:17 PM PST 23 |
Peak memory | 213664 kb |
Host | smart-2a0e539c-00f8-470b-ad1a-8af6630e54ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217394880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc alation.217394880 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.798546 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 693454693 ps |
CPU time | 30.34 seconds |
Started | Dec 27 12:45:32 PM PST 23 |
Finished | Dec 27 12:46:11 PM PST 23 |
Peak memory | 225724 kb |
Host | smart-765d6b51-73f0-467c-92ee-6440ff214d5b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.sram_ctrl_max_throughput.798546 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.295585266 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 5198453394 ps |
CPU time | 145.96 seconds |
Started | Dec 27 12:45:24 PM PST 23 |
Finished | Dec 27 12:47:58 PM PST 23 |
Peak memory | 211156 kb |
Host | smart-083d312f-dbbc-4e47-9f65-980a69c33787 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295585266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_mem_partial_access.295585266 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.3180939990 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 3953426601 ps |
CPU time | 123.17 seconds |
Started | Dec 27 12:45:19 PM PST 23 |
Finished | Dec 27 12:47:31 PM PST 23 |
Peak memory | 202204 kb |
Host | smart-8b98da54-5842-43f8-8edc-bbbbb4ca5e70 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180939990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.3180939990 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.1834083698 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 44142003544 ps |
CPU time | 1170.71 seconds |
Started | Dec 27 12:45:37 PM PST 23 |
Finished | Dec 27 01:05:17 PM PST 23 |
Peak memory | 378976 kb |
Host | smart-ddf517d6-5a56-4dc1-9ae6-32f18a92707d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834083698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.1834083698 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.3113545317 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 2367664372 ps |
CPU time | 10.43 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:45:45 PM PST 23 |
Peak memory | 201980 kb |
Host | smart-b3b5a861-c553-4d7a-ad7e-c7af3d044cdf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113545317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.3113545317 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4070987501 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 182546918886 ps |
CPU time | 251.79 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:49:53 PM PST 23 |
Peak memory | 202096 kb |
Host | smart-0b1a1449-4355-4232-8c26-2c784a44401b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070987501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.4070987501 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.4086858169 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 676839221 ps |
CPU time | 5.77 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:45:30 PM PST 23 |
Peak memory | 202312 kb |
Host | smart-fe01bbda-e759-4038-8a73-9cb2b9e3cfa1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086858169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.4086858169 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.3327887488 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 36848155912 ps |
CPU time | 522.4 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:54:09 PM PST 23 |
Peak memory | 370920 kb |
Host | smart-4336dee9-a5c6-46e9-b46b-525889d20d4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327887488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3327887488 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.3736619777 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 1596139292 ps |
CPU time | 35.73 seconds |
Started | Dec 27 12:45:15 PM PST 23 |
Finished | Dec 27 12:45:58 PM PST 23 |
Peak memory | 201952 kb |
Host | smart-da6b3691-aa65-400b-a72b-eee808d7fe02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736619777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3736619777 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2743186262 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 435582481 ps |
CPU time | 2283.34 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 01:23:23 PM PST 23 |
Peak memory | 617392 kb |
Host | smart-f6ec01e1-3187-40c8-be9c-c9cbd3eaabe6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2743186262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2743186262 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3524271936 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 26488160271 ps |
CPU time | 392.07 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:52:02 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-95f9c70a-5464-4342-9373-43a86bdc8c82 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524271936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.3524271936 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3310535252 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 798767074 ps |
CPU time | 93.62 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 12:47:25 PM PST 23 |
Peak memory | 354396 kb |
Host | smart-b96b6bcb-a3c9-4329-9eaf-7ce5801a1cf7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310535252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3310535252 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1855955531 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 7661089581 ps |
CPU time | 741 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:57:47 PM PST 23 |
Peak memory | 362704 kb |
Host | smart-6638c5f8-6d78-4f52-939a-22bc6db76c97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855955531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.1855955531 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.3774230592 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 31985204 ps |
CPU time | 0.6 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:45:31 PM PST 23 |
Peak memory | 201252 kb |
Host | smart-babe9758-4aa0-45f0-81fb-4902c510bf55 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774230592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3774230592 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.317422862 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 473749868854 ps |
CPU time | 2158.75 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 01:21:41 PM PST 23 |
Peak memory | 202080 kb |
Host | smart-d4d6006e-c19f-4ad7-ae42-8852dd1a00eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317422862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection. 317422862 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.3635908716 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 34365328494 ps |
CPU time | 86.44 seconds |
Started | Dec 27 12:45:25 PM PST 23 |
Finished | Dec 27 12:47:00 PM PST 23 |
Peak memory | 210268 kb |
Host | smart-887c0b26-d47c-45dd-9c46-8f4d3af23718 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635908716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3635908716 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.3122505421 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 5440705845 ps |
CPU time | 45.06 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 12:46:24 PM PST 23 |
Peak memory | 269484 kb |
Host | smart-604b07b1-e047-4460-971d-0fe74384c612 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122505421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.3122505421 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.658110152 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 19048532670 ps |
CPU time | 147.91 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:47:55 PM PST 23 |
Peak memory | 210960 kb |
Host | smart-9ae3cb5d-dd89-4392-a5fa-5490b63f20f8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658110152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_mem_partial_access.658110152 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.667064604 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 16425340690 ps |
CPU time | 249.21 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 12:49:33 PM PST 23 |
Peak memory | 202036 kb |
Host | smart-9f1832de-4314-401d-b4d1-806daf4aeb76 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667064604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _mem_walk.667064604 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.156855447 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 4275099875 ps |
CPU time | 200.82 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:48:55 PM PST 23 |
Peak memory | 371932 kb |
Host | smart-14d2f272-f6c7-421d-ac76-e886eb09a733 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156855447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip le_keys.156855447 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.3563966228 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 2020196415 ps |
CPU time | 136.29 seconds |
Started | Dec 27 12:45:15 PM PST 23 |
Finished | Dec 27 12:47:38 PM PST 23 |
Peak memory | 374988 kb |
Host | smart-eacd2cd6-1a20-4655-9624-de26aafcfd1e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563966228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.3563966228 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.767820603 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 12385434020 ps |
CPU time | 194.83 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:48:46 PM PST 23 |
Peak memory | 202020 kb |
Host | smart-d6de32f9-2f30-4bf7-87fa-eb8e12706db9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767820603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.sram_ctrl_partial_access_b2b.767820603 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.4013344743 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 2110136228 ps |
CPU time | 7.03 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:45:37 PM PST 23 |
Peak memory | 202348 kb |
Host | smart-b5fdee81-352a-4928-baeb-4135650c01f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013344743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4013344743 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.1966386328 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 89239284067 ps |
CPU time | 1330.4 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 01:07:55 PM PST 23 |
Peak memory | 379972 kb |
Host | smart-f2ab137b-5e00-47ec-8464-7d1a403a6f6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966386328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1966386328 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.542677828 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 4015880838 ps |
CPU time | 19.59 seconds |
Started | Dec 27 12:45:12 PM PST 23 |
Finished | Dec 27 12:45:37 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-b8ec4330-8d01-4233-8e38-3873d0baa6ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542677828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.542677828 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3583179082 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 964288838 ps |
CPU time | 2149.51 seconds |
Started | Dec 27 12:45:17 PM PST 23 |
Finished | Dec 27 01:21:15 PM PST 23 |
Peak memory | 446820 kb |
Host | smart-c3f748a0-db67-4bf9-99b2-6deda47cf812 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3583179082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3583179082 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3510343169 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 7882799365 ps |
CPU time | 303.61 seconds |
Started | Dec 27 12:45:37 PM PST 23 |
Finished | Dec 27 12:50:49 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-a9db3cae-c7a4-4e27-82c2-38c19f8daa2d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510343169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.3510343169 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1033233903 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 771127244 ps |
CPU time | 123.37 seconds |
Started | Dec 27 12:45:42 PM PST 23 |
Finished | Dec 27 12:47:54 PM PST 23 |
Peak memory | 349296 kb |
Host | smart-06e7d7d3-fc18-4272-a3bf-fca3b9b5d928 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033233903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1033233903 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.321350068 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 11016878859 ps |
CPU time | 846.19 seconds |
Started | Dec 27 12:45:20 PM PST 23 |
Finished | Dec 27 12:59:36 PM PST 23 |
Peak memory | 377948 kb |
Host | smart-b17c030b-9df9-4183-91ee-0c78537a4ddb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321350068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sram_ctrl_access_during_key_req.321350068 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.1032352619 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 32711245 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:45:32 PM PST 23 |
Peak memory | 201724 kb |
Host | smart-cdd0045a-f7cc-411d-a5e5-e59523a7a209 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032352619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1032352619 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.3083258054 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 72797450494 ps |
CPU time | 1106.48 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 01:04:00 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-3682948b-2d43-4a20-bdf0-07ea0bbbce2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083258054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3083258054 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.776396471 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 6558622038 ps |
CPU time | 43.64 seconds |
Started | Dec 27 12:45:41 PM PST 23 |
Finished | Dec 27 12:46:33 PM PST 23 |
Peak memory | 202036 kb |
Host | smart-35c11d31-aef3-452f-b29f-3a7a86add417 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776396471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc alation.776396471 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.2874894870 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 783040415 ps |
CPU time | 138.4 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:47:45 PM PST 23 |
Peak memory | 364776 kb |
Host | smart-eaa68ee4-ed15-4c3e-9753-444665e7c1f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874894870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2874894870 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4123838927 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 10459381826 ps |
CPU time | 79.68 seconds |
Started | Dec 27 12:45:12 PM PST 23 |
Finished | Dec 27 12:46:38 PM PST 23 |
Peak memory | 211420 kb |
Host | smart-f37b9c8f-da76-4dbc-ac61-5143651b0166 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123838927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.4123838927 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.1503632258 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 57444852539 ps |
CPU time | 289.41 seconds |
Started | Dec 27 12:45:32 PM PST 23 |
Finished | Dec 27 12:50:30 PM PST 23 |
Peak memory | 202108 kb |
Host | smart-a9cd7a36-fd90-4228-a6fa-3c1d9ec0de95 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503632258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.1503632258 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.3688366363 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 15062272466 ps |
CPU time | 481.24 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 12:53:33 PM PST 23 |
Peak memory | 374916 kb |
Host | smart-99fbdf8e-0899-4eef-8547-213c2f0b0ce2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688366363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.3688366363 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.327931546 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 1235690915 ps |
CPU time | 92.34 seconds |
Started | Dec 27 12:45:50 PM PST 23 |
Finished | Dec 27 12:47:30 PM PST 23 |
Peak memory | 346132 kb |
Host | smart-ee3823c6-4e2c-4fee-9220-704fe355caa5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327931546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s ram_ctrl_partial_access.327931546 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2538807390 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 14727988747 ps |
CPU time | 331.84 seconds |
Started | Dec 27 12:45:37 PM PST 23 |
Finished | Dec 27 12:51:18 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-6e58101c-8add-4b96-a62b-6dea16e2b99a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538807390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.2538807390 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.586071017 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 5608204337 ps |
CPU time | 15.07 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:45:45 PM PST 23 |
Peak memory | 202320 kb |
Host | smart-26d41a94-2be6-43ce-b884-c046f7289028 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586071017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.586071017 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.46290062 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 14515646822 ps |
CPU time | 1521.19 seconds |
Started | Dec 27 12:45:58 PM PST 23 |
Finished | Dec 27 01:11:30 PM PST 23 |
Peak memory | 371772 kb |
Host | smart-5f56e602-09ab-4d3e-8967-d0b1dc05fef9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46290062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.46290062 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.1400298771 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 7899242191 ps |
CPU time | 44.29 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 12:46:16 PM PST 23 |
Peak memory | 264424 kb |
Host | smart-b87fca85-e03a-4541-8664-7cec8c4bda9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400298771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1400298771 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.1739145769 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 328518230444 ps |
CPU time | 2996.92 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 01:35:15 PM PST 23 |
Peak memory | 383420 kb |
Host | smart-9a616899-5514-4776-b119-234a582566ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739145769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1739145769 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3615251507 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 4953519129 ps |
CPU time | 5982.17 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 02:25:22 PM PST 23 |
Peak memory | 676084 kb |
Host | smart-be5c2139-f38b-48e6-a2de-b5dc09b6afbd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3615251507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3615251507 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.359527666 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 37775833347 ps |
CPU time | 411.14 seconds |
Started | Dec 27 12:45:35 PM PST 23 |
Finished | Dec 27 12:52:35 PM PST 23 |
Peak memory | 201924 kb |
Host | smart-4ccc9175-c40a-46bb-8c9b-2462e1deb462 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359527666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_stress_pipeline.359527666 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4175215341 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 2994992227 ps |
CPU time | 73.31 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 12:46:59 PM PST 23 |
Peak memory | 321740 kb |
Host | smart-97b58fc3-0d89-414b-8852-dc16a47c04d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175215341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.4175215341 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2835883515 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 2596956252 ps |
CPU time | 553.94 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 12:55:07 PM PST 23 |
Peak memory | 374288 kb |
Host | smart-3f517996-3b4d-4595-b038-5bdf9efd276f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835883515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.2835883515 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.658962690 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 37943403 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:45:42 PM PST 23 |
Peak memory | 201284 kb |
Host | smart-29546e13-2796-47a1-85ba-6fc9ee504a79 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658962690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.658962690 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.2700621655 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 607021092461 ps |
CPU time | 2540.4 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 01:28:09 PM PST 23 |
Peak memory | 201968 kb |
Host | smart-f495f613-1fc6-4aa5-9ed3-99e2c6baaaab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700621655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .2700621655 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.2481962702 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 13368331005 ps |
CPU time | 181.69 seconds |
Started | Dec 27 12:45:19 PM PST 23 |
Finished | Dec 27 12:48:30 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-550efd85-aa6b-475b-8c1d-c7474699a4a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481962702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2481962702 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.1249364287 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 5259186843 ps |
CPU time | 30.17 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:46:00 PM PST 23 |
Peak memory | 234784 kb |
Host | smart-a7a9eecd-f182-4581-a348-1581bfdfbe03 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249364287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.1249364287 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2329686456 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 10884297946 ps |
CPU time | 85.31 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 12:46:46 PM PST 23 |
Peak memory | 211020 kb |
Host | smart-48607dc4-9cb3-4276-8d94-721097369ba1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329686456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.2329686456 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.332001899 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 4065452913 ps |
CPU time | 246.75 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:49:37 PM PST 23 |
Peak memory | 202124 kb |
Host | smart-22ac964f-cc2a-442e-82ef-8105fa294a56 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332001899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _mem_walk.332001899 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.973343370 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 1507129027 ps |
CPU time | 26.11 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:45:56 PM PST 23 |
Peak memory | 201948 kb |
Host | smart-46bf330b-c320-4614-b4a0-3036c196573e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973343370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s ram_ctrl_partial_access.973343370 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1636569873 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 15150336521 ps |
CPU time | 472.83 seconds |
Started | Dec 27 12:45:37 PM PST 23 |
Finished | Dec 27 12:53:38 PM PST 23 |
Peak memory | 202096 kb |
Host | smart-e983a538-a1eb-4261-a72d-67638464b84d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636569873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.1636569873 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.2881811237 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 1410372926 ps |
CPU time | 6.77 seconds |
Started | Dec 27 12:45:37 PM PST 23 |
Finished | Dec 27 12:45:53 PM PST 23 |
Peak memory | 202348 kb |
Host | smart-6fafe10a-88dd-41ec-a447-87262aa4ad7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881811237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.2881811237 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.3471178905 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 69639728419 ps |
CPU time | 1657.87 seconds |
Started | Dec 27 12:45:47 PM PST 23 |
Finished | Dec 27 01:13:33 PM PST 23 |
Peak memory | 378952 kb |
Host | smart-c860e204-4b21-460b-941d-da59787dfb0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471178905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3471178905 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.350493544 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 726975998 ps |
CPU time | 37.67 seconds |
Started | Dec 27 12:45:35 PM PST 23 |
Finished | Dec 27 12:46:21 PM PST 23 |
Peak memory | 294896 kb |
Host | smart-f2a33355-807a-4d98-aaf8-f7610dfc0f6f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350493544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.350493544 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.62410163 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 5020993212 ps |
CPU time | 4052.22 seconds |
Started | Dec 27 12:45:23 PM PST 23 |
Finished | Dec 27 01:53:05 PM PST 23 |
Peak memory | 667648 kb |
Host | smart-02230208-ad34-4f9d-ac01-af924ff7b9d2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=62410163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.62410163 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.21686135 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 54126943405 ps |
CPU time | 258.89 seconds |
Started | Dec 27 12:45:46 PM PST 23 |
Finished | Dec 27 12:50:12 PM PST 23 |
Peak memory | 202020 kb |
Host | smart-fd148d69-3d68-40d2-88fa-426525608db7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21686135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_stress_pipeline.21686135 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1240945162 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 2575958884 ps |
CPU time | 33.54 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:46:15 PM PST 23 |
Peak memory | 240428 kb |
Host | smart-054a60be-d975-4e65-9977-100ed9d4983c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240945162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1240945162 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.167685642 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 11750231662 ps |
CPU time | 2148.88 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 01:21:37 PM PST 23 |
Peak memory | 379964 kb |
Host | smart-2cfaef8b-0ed4-4c48-a46d-f8d0d6aba443 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167685642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 44.sram_ctrl_access_during_key_req.167685642 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.2829740831 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 25616060 ps |
CPU time | 0.65 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 12:45:53 PM PST 23 |
Peak memory | 201308 kb |
Host | smart-440213f0-c46f-4f88-a285-0301666c90aa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829740831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2829740831 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2502870928 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 21333573814 ps |
CPU time | 1467.68 seconds |
Started | Dec 27 12:45:35 PM PST 23 |
Finished | Dec 27 01:10:12 PM PST 23 |
Peak memory | 202012 kb |
Host | smart-459457b1-fba2-4a9c-86a8-766a4c326fde |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502870928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2502870928 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2182271096 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 92620861399 ps |
CPU time | 84.99 seconds |
Started | Dec 27 12:45:32 PM PST 23 |
Finished | Dec 27 12:47:04 PM PST 23 |
Peak memory | 210224 kb |
Host | smart-ac30efa2-023a-4eaa-820a-4d3204eb47d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182271096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2182271096 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.4092613249 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 750840266 ps |
CPU time | 78.7 seconds |
Started | Dec 27 12:45:24 PM PST 23 |
Finished | Dec 27 12:46:51 PM PST 23 |
Peak memory | 324820 kb |
Host | smart-940bf1f6-ec41-49ca-a52e-603bb5fd9e50 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092613249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.4092613249 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3598663609 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 2618524923 ps |
CPU time | 78.81 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:46:57 PM PST 23 |
Peak memory | 210752 kb |
Host | smart-eaf16f4f-1c46-41e5-b911-6063338d5a36 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598663609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.3598663609 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1154932788 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 86003687462 ps |
CPU time | 317.45 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 12:51:10 PM PST 23 |
Peak memory | 202064 kb |
Host | smart-55068426-e8ff-4498-a62a-cca5853e7144 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154932788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1154932788 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.1017270714 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 59619236018 ps |
CPU time | 1087.13 seconds |
Started | Dec 27 12:45:12 PM PST 23 |
Finished | Dec 27 01:03:25 PM PST 23 |
Peak memory | 375888 kb |
Host | smart-7db84452-d38c-40f4-9e73-11b71ba4e544 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017270714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.1017270714 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.844287469 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 3089681173 ps |
CPU time | 44.73 seconds |
Started | Dec 27 12:45:27 PM PST 23 |
Finished | Dec 27 12:46:19 PM PST 23 |
Peak memory | 266436 kb |
Host | smart-662f9fd0-8187-409a-9f91-70ba5d9ee438 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844287469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.844287469 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1261737973 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 29532457812 ps |
CPU time | 324.06 seconds |
Started | Dec 27 12:45:14 PM PST 23 |
Finished | Dec 27 12:50:45 PM PST 23 |
Peak memory | 202032 kb |
Host | smart-c713246d-cc56-4674-996c-11bafee5801d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261737973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1261737973 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.3870942184 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 390564457 ps |
CPU time | 5.57 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:45:41 PM PST 23 |
Peak memory | 202220 kb |
Host | smart-d464ad61-f2c0-463c-9791-133d1f28c857 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870942184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3870942184 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.2703299460 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 3294621464 ps |
CPU time | 34.42 seconds |
Started | Dec 27 12:45:25 PM PST 23 |
Finished | Dec 27 12:46:07 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-8cad7cdd-bced-4e6d-b611-aa6f519d9a33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703299460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2703299460 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1777344551 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 1622724955 ps |
CPU time | 4228.91 seconds |
Started | Dec 27 12:45:35 PM PST 23 |
Finished | Dec 27 01:56:13 PM PST 23 |
Peak memory | 732840 kb |
Host | smart-062ed426-9db7-4d83-af4a-70c84ad48b01 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1777344551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1777344551 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.585378237 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 3885469777 ps |
CPU time | 257.3 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:49:53 PM PST 23 |
Peak memory | 201944 kb |
Host | smart-e5be3eca-845f-43ca-bcfe-d6000d15062b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585378237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .sram_ctrl_stress_pipeline.585378237 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1437104083 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 726884090 ps |
CPU time | 29.97 seconds |
Started | Dec 27 12:45:42 PM PST 23 |
Finished | Dec 27 12:46:20 PM PST 23 |
Peak memory | 234708 kb |
Host | smart-c3e2f42b-770b-4301-8891-a1d4fb265626 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437104083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1437104083 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2688746298 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 9194719369 ps |
CPU time | 1397.63 seconds |
Started | Dec 27 12:45:16 PM PST 23 |
Finished | Dec 27 01:08:42 PM PST 23 |
Peak memory | 379028 kb |
Host | smart-1d0ded25-3d2d-4168-aa82-42f175a2fc93 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688746298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.2688746298 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.1063683146 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 37211322 ps |
CPU time | 0.61 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:45:30 PM PST 23 |
Peak memory | 201736 kb |
Host | smart-bc069953-5653-42e2-a903-6e1ea88edf4d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063683146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1063683146 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.717659000 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 164169887071 ps |
CPU time | 670.69 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:56:52 PM PST 23 |
Peak memory | 202076 kb |
Host | smart-1708330c-6f54-400f-8c08-dad2ab94c4a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717659000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection. 717659000 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.2948858329 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 24906535066 ps |
CPU time | 833.4 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:59:30 PM PST 23 |
Peak memory | 370796 kb |
Host | smart-6b282516-1951-4999-90eb-2a5d18526e3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948858329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.2948858329 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1580123071 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 12158102919 ps |
CPU time | 105.42 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:47:12 PM PST 23 |
Peak memory | 213640 kb |
Host | smart-73e095cf-aad6-45f1-aadf-d991ea3f8c89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580123071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.1580123071 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.818325344 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 801531808 ps |
CPU time | 35.17 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 12:46:14 PM PST 23 |
Peak memory | 251116 kb |
Host | smart-20e8c772-90d0-4127-b433-ccd6cb492a6c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818325344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.sram_ctrl_max_throughput.818325344 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.597913719 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 9149109453 ps |
CPU time | 76.58 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:46:50 PM PST 23 |
Peak memory | 211540 kb |
Host | smart-03878292-d369-4b3e-b0f7-6617b0958220 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597913719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .sram_ctrl_mem_partial_access.597913719 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.429298072 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 20737023000 ps |
CPU time | 247.99 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 12:49:45 PM PST 23 |
Peak memory | 202088 kb |
Host | smart-3e0ba5c1-17ae-46bb-b1fd-4dfb20d94d2a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429298072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _mem_walk.429298072 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.1480778570 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 65314605944 ps |
CPU time | 528.17 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:54:15 PM PST 23 |
Peak memory | 354460 kb |
Host | smart-3b21ea93-0e0d-4ea8-ae4c-2f582a8a5ec1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480778570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.1480778570 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.3785614307 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 990069864 ps |
CPU time | 22.54 seconds |
Started | Dec 27 12:45:47 PM PST 23 |
Finished | Dec 27 12:46:18 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-2b203169-2fdc-46ac-9435-b3a4c27796b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785614307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.3785614307 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.130400660 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 135537579916 ps |
CPU time | 620.68 seconds |
Started | Dec 27 12:45:25 PM PST 23 |
Finished | Dec 27 12:55:54 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-8ab90b45-8804-4bd3-a054-9fe17b7dd3b2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130400660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_partial_access_b2b.130400660 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.1639296248 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 707597521 ps |
CPU time | 6.11 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:45:40 PM PST 23 |
Peak memory | 202204 kb |
Host | smart-c7c25427-fff4-4e22-8f71-865a6bbd8330 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639296248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1639296248 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.3412861188 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 5183206661 ps |
CPU time | 1340.01 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 01:07:58 PM PST 23 |
Peak memory | 375884 kb |
Host | smart-6261d9b1-55fb-494a-a525-e7ac4780e1d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412861188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3412861188 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.383929492 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 1112988951 ps |
CPU time | 19.62 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:46:02 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-37865299-857b-4554-aa32-d78fe21c0469 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383929492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.383929492 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3482537005 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 5227334202 ps |
CPU time | 3517.84 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 01:44:27 PM PST 23 |
Peak memory | 698768 kb |
Host | smart-152819bd-872f-4ad8-9fc7-288692a7e687 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3482537005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3482537005 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3928407240 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 7448462603 ps |
CPU time | 278.83 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 12:50:17 PM PST 23 |
Peak memory | 202096 kb |
Host | smart-4efa2418-f898-4434-91e3-3cb89dcaa76c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928407240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.3928407240 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4038170503 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 1328168229 ps |
CPU time | 31.59 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:46:14 PM PST 23 |
Peak memory | 219884 kb |
Host | smart-e8059d25-7cf3-44ea-8fce-bf874844820b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038170503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.4038170503 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3713397957 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 8997804822 ps |
CPU time | 891.86 seconds |
Started | Dec 27 12:45:47 PM PST 23 |
Finished | Dec 27 01:00:47 PM PST 23 |
Peak memory | 368744 kb |
Host | smart-e9b44d63-f936-4593-b68e-6443794ab965 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713397957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.3713397957 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1762960266 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 84910467 ps |
CPU time | 0.68 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:45:30 PM PST 23 |
Peak memory | 201764 kb |
Host | smart-f2c5c4fd-8f0c-47d5-bdd2-cbf200968370 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762960266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1762960266 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.1963747813 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 307210437046 ps |
CPU time | 1911.8 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 01:17:39 PM PST 23 |
Peak memory | 201968 kb |
Host | smart-37262585-65f4-43e3-a1f2-b706713e31b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963747813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .1963747813 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.3961146136 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 53048934553 ps |
CPU time | 770.98 seconds |
Started | Dec 27 12:45:43 PM PST 23 |
Finished | Dec 27 12:58:42 PM PST 23 |
Peak memory | 370292 kb |
Host | smart-3acafd54-9dd0-4584-8c11-46bd0e142ca3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961146136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.3961146136 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.2979867510 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 2789984361 ps |
CPU time | 27.42 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 12:46:14 PM PST 23 |
Peak memory | 210248 kb |
Host | smart-ed96dde7-4c3f-4190-9150-e38c1d01db74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979867510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.2979867510 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.2496325571 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 2836124106 ps |
CPU time | 43.27 seconds |
Started | Dec 27 12:45:50 PM PST 23 |
Finished | Dec 27 12:46:41 PM PST 23 |
Peak memory | 271624 kb |
Host | smart-ca5cfe77-0060-4de1-8185-cf6d04cf135f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496325571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.2496325571 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3986105022 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 1547870064 ps |
CPU time | 136.96 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 12:47:55 PM PST 23 |
Peak memory | 211092 kb |
Host | smart-40ed9303-1fa4-490c-bd09-916e967b9450 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986105022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.3986105022 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.2927315574 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 3950791786 ps |
CPU time | 119.56 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:47:38 PM PST 23 |
Peak memory | 202064 kb |
Host | smart-44e40515-0cec-4484-a3d3-698a200a3783 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927315574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.2927315574 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.3705729648 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 73327151385 ps |
CPU time | 947.89 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 01:01:33 PM PST 23 |
Peak memory | 380984 kb |
Host | smart-17b78290-7341-4770-9e0b-585181ae879f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705729648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.3705729648 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.37497382 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 1086327985 ps |
CPU time | 109.29 seconds |
Started | Dec 27 12:45:25 PM PST 23 |
Finished | Dec 27 12:47:22 PM PST 23 |
Peak memory | 366580 kb |
Host | smart-7806bbde-7873-47eb-b0bb-606d8da7bfbf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37497382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sr am_ctrl_partial_access.37497382 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4224067273 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 245730601867 ps |
CPU time | 548.9 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 12:54:47 PM PST 23 |
Peak memory | 210280 kb |
Host | smart-35f822fe-ca51-40f0-a378-7270419116ed |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224067273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.4224067273 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2867810163 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 4800665843 ps |
CPU time | 7.82 seconds |
Started | Dec 27 12:46:59 PM PST 23 |
Finished | Dec 27 12:47:24 PM PST 23 |
Peak memory | 202456 kb |
Host | smart-57df05c6-bef6-427a-9012-df554df055e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867810163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2867810163 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.1172112073 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 66063614097 ps |
CPU time | 474.97 seconds |
Started | Dec 27 12:45:18 PM PST 23 |
Finished | Dec 27 12:53:21 PM PST 23 |
Peak memory | 372880 kb |
Host | smart-8fcc3ea7-cbca-4b9f-b2c8-245435d665a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172112073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1172112073 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.3206819795 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 1814304192 ps |
CPU time | 42.01 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:46:12 PM PST 23 |
Peak memory | 202044 kb |
Host | smart-d40fd300-1b1d-4395-903b-c73332a9ad34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206819795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3206819795 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.2657433594 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 809981575753 ps |
CPU time | 3867.89 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 01:50:14 PM PST 23 |
Peak memory | 379804 kb |
Host | smart-20ada279-91e3-4795-99f9-5b7eaa3258e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657433594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.2657433594 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3399350681 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 3016040282 ps |
CPU time | 5589.12 seconds |
Started | Dec 27 12:45:20 PM PST 23 |
Finished | Dec 27 02:18:38 PM PST 23 |
Peak memory | 735096 kb |
Host | smart-d6a4db32-2374-4ff2-be77-5993b2e8a94f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3399350681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3399350681 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2534442575 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 6062672654 ps |
CPU time | 233.16 seconds |
Started | Dec 27 12:45:16 PM PST 23 |
Finished | Dec 27 12:49:17 PM PST 23 |
Peak memory | 202020 kb |
Host | smart-2b927275-d2a9-41f4-9539-a6541d8fc962 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534442575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2534442575 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1922952504 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 769714776 ps |
CPU time | 51.53 seconds |
Started | Dec 27 12:45:10 PM PST 23 |
Finished | Dec 27 12:46:07 PM PST 23 |
Peak memory | 277620 kb |
Host | smart-907db0fe-5b71-435d-a3b4-3ca7ddd268ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922952504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.1922952504 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.471380452 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 13068170989 ps |
CPU time | 204.43 seconds |
Started | Dec 27 12:45:52 PM PST 23 |
Finished | Dec 27 12:49:23 PM PST 23 |
Peak memory | 263980 kb |
Host | smart-bfed662d-2a39-4f1f-aee9-16cfdf06ab8a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471380452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 47.sram_ctrl_access_during_key_req.471380452 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.1590816290 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 47831339 ps |
CPU time | 0.64 seconds |
Started | Dec 27 12:45:53 PM PST 23 |
Finished | Dec 27 12:46:02 PM PST 23 |
Peak memory | 201808 kb |
Host | smart-0e3abc82-4ba1-4aa0-8fee-c70f3c1cacf9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590816290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1590816290 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.3025375018 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 74752578080 ps |
CPU time | 1323.25 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 01:07:50 PM PST 23 |
Peak memory | 201992 kb |
Host | smart-2bc7027d-614c-4d17-9327-40a874462ca6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025375018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .3025375018 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.4215504009 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 37845666420 ps |
CPU time | 188.53 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:48:38 PM PST 23 |
Peak memory | 202036 kb |
Host | smart-3a31b4b7-b674-4673-8dbb-6492f169bdef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215504009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.4215504009 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.588188778 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 2899912557 ps |
CPU time | 70.13 seconds |
Started | Dec 27 12:45:41 PM PST 23 |
Finished | Dec 27 12:47:00 PM PST 23 |
Peak memory | 301176 kb |
Host | smart-11fd0a02-1190-4643-92de-760c10cbe7d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588188778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.sram_ctrl_max_throughput.588188778 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.2046566437 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 2065640199 ps |
CPU time | 122.79 seconds |
Started | Dec 27 12:45:22 PM PST 23 |
Finished | Dec 27 12:47:34 PM PST 23 |
Peak memory | 202008 kb |
Host | smart-df3cba6a-7bf3-44d3-91f2-c78032b5c926 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046566437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2046566437 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.2186211930 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 100600959440 ps |
CPU time | 1096.3 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 01:03:53 PM PST 23 |
Peak memory | 380016 kb |
Host | smart-743e76ec-aa21-438a-877e-c6b39747ac0e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186211930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.2186211930 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2332066134 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 2789648117 ps |
CPU time | 137.55 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:48:06 PM PST 23 |
Peak memory | 370748 kb |
Host | smart-37dff732-02f7-4e74-84c8-a9bba9e39c0a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332066134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2332066134 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1586274918 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 32490741986 ps |
CPU time | 385.15 seconds |
Started | Dec 27 12:45:43 PM PST 23 |
Finished | Dec 27 12:52:17 PM PST 23 |
Peak memory | 202016 kb |
Host | smart-1682aac5-8e87-45fb-b727-f064f87a5254 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586274918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.1586274918 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.764000163 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 373615350 ps |
CPU time | 6.46 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 12:45:45 PM PST 23 |
Peak memory | 202256 kb |
Host | smart-ccb16ddf-2f85-46e4-a922-9154413b7445 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764000163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.764000163 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.3667875852 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 5496135076 ps |
CPU time | 1058.37 seconds |
Started | Dec 27 12:45:45 PM PST 23 |
Finished | Dec 27 01:03:32 PM PST 23 |
Peak memory | 374844 kb |
Host | smart-7985c460-3c61-4491-be9e-1e4541feed2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667875852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3667875852 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.1306045703 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 5337915907 ps |
CPU time | 108.76 seconds |
Started | Dec 27 12:45:49 PM PST 23 |
Finished | Dec 27 12:47:45 PM PST 23 |
Peak memory | 343128 kb |
Host | smart-a208d500-ff2f-44f9-857b-32b1366d41b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306045703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1306045703 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.124803744 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 6677203714 ps |
CPU time | 2147.69 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 01:21:17 PM PST 23 |
Peak memory | 633136 kb |
Host | smart-c3ee7a91-c556-4a82-8460-1715150ab730 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=124803744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.124803744 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4159182041 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 8643065273 ps |
CPU time | 319.73 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:50:53 PM PST 23 |
Peak memory | 202020 kb |
Host | smart-350691ee-ffd4-49ae-8f8e-3cf7efd18ab3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159182041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.4159182041 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1737472657 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 2077335223 ps |
CPU time | 44.38 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:46:18 PM PST 23 |
Peak memory | 253724 kb |
Host | smart-df130bbe-43a2-4f52-8fcc-4688eac49192 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737472657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1737472657 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1429540761 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 4194164745 ps |
CPU time | 377.83 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:51:53 PM PST 23 |
Peak memory | 370684 kb |
Host | smart-5adb2ab2-13d7-4a7d-be98-71b39fdb3f43 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429540761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.1429540761 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.1925022185 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 13005921 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:45:52 PM PST 23 |
Finished | Dec 27 12:46:00 PM PST 23 |
Peak memory | 201272 kb |
Host | smart-6130a91c-1506-43a0-a536-873231c38820 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925022185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1925022185 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.2975826572 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 83327915790 ps |
CPU time | 1431.56 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 01:09:45 PM PST 23 |
Peak memory | 202080 kb |
Host | smart-f1020895-794e-4467-897d-42d5aee00b95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975826572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .2975826572 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.1633389816 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 11031361487 ps |
CPU time | 133.07 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:47:48 PM PST 23 |
Peak memory | 210316 kb |
Host | smart-4504f3a5-097a-48c5-8c0a-4c8b3c2f9aba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633389816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.1633389816 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.3689005476 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 727517350 ps |
CPU time | 57.66 seconds |
Started | Dec 27 12:45:29 PM PST 23 |
Finished | Dec 27 12:46:33 PM PST 23 |
Peak memory | 295220 kb |
Host | smart-0343e731-805a-4176-9937-f6119ca524ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689005476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.3689005476 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1903743818 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 6720168610 ps |
CPU time | 76.04 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 12:47:01 PM PST 23 |
Peak memory | 211028 kb |
Host | smart-d36ab88d-ff0a-43c0-92b9-e2db678ea0db |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903743818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.1903743818 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.1806676709 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 21138821561 ps |
CPU time | 158.76 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 12:48:28 PM PST 23 |
Peak memory | 202056 kb |
Host | smart-c6a20885-e7cf-40b3-8b64-e1ef5bd7e076 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806676709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.1806676709 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.3876131884 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 9118071411 ps |
CPU time | 604.29 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:55:51 PM PST 23 |
Peak memory | 370800 kb |
Host | smart-6587d026-6723-4a02-876e-ae2ce80c801a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876131884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.3876131884 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.1616694004 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 1275761448 ps |
CPU time | 13.72 seconds |
Started | Dec 27 12:45:45 PM PST 23 |
Finished | Dec 27 12:46:07 PM PST 23 |
Peak memory | 202004 kb |
Host | smart-737815ac-9ef2-4d70-9b62-b4c76da2cca4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616694004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1616694004 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1822631849 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 64296774092 ps |
CPU time | 358.37 seconds |
Started | Dec 27 12:45:25 PM PST 23 |
Finished | Dec 27 12:51:31 PM PST 23 |
Peak memory | 202024 kb |
Host | smart-29fe4c1c-acf3-49bc-a522-157a017549e7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822631849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1822631849 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.3374505429 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 1397611606 ps |
CPU time | 13.19 seconds |
Started | Dec 27 12:45:33 PM PST 23 |
Finished | Dec 27 12:45:54 PM PST 23 |
Peak memory | 202344 kb |
Host | smart-dddd8221-7f5b-4d3f-aeab-9aef5f32a451 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374505429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3374505429 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.256091041 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 5113560254 ps |
CPU time | 916.74 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 01:00:56 PM PST 23 |
Peak memory | 377960 kb |
Host | smart-bd13c3dc-60c7-4150-b7ac-37508c3d12c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256091041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.256091041 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.2938076176 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 845314694 ps |
CPU time | 28.52 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 12:46:17 PM PST 23 |
Peak memory | 201920 kb |
Host | smart-98f8590b-82f0-4cbb-9adf-fca7665045b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938076176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2938076176 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.974253805 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 32704113574 ps |
CPU time | 1162.23 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 01:05:07 PM PST 23 |
Peak memory | 380012 kb |
Host | smart-04b92fa1-a1c1-44bc-ac9f-33e2b6699aa6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974253805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_stress_all.974253805 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2755358735 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 2892446640 ps |
CPU time | 1756.68 seconds |
Started | Dec 27 12:45:36 PM PST 23 |
Finished | Dec 27 01:15:01 PM PST 23 |
Peak memory | 431256 kb |
Host | smart-72339fc9-1781-43ea-b539-1f53ba2d24a4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2755358735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2755358735 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.850406025 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 4813133857 ps |
CPU time | 330.76 seconds |
Started | Dec 27 12:45:51 PM PST 23 |
Finished | Dec 27 12:51:29 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-05d4adb8-c855-4103-95cb-4577f9571355 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850406025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_stress_pipeline.850406025 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.179117839 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 806575123 ps |
CPU time | 105.32 seconds |
Started | Dec 27 12:45:13 PM PST 23 |
Finished | Dec 27 12:47:05 PM PST 23 |
Peak memory | 357468 kb |
Host | smart-5d531094-ce3a-47aa-b09a-a92afcf0fb61 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179117839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.179117839 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.162688339 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 4434361049 ps |
CPU time | 253.96 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 12:50:06 PM PST 23 |
Peak memory | 325592 kb |
Host | smart-77cb2af4-11e9-43bf-853c-6a8ff32fc021 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162688339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sram_ctrl_access_during_key_req.162688339 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.1162924501 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 34414117 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:45:39 PM PST 23 |
Finished | Dec 27 12:45:48 PM PST 23 |
Peak memory | 201724 kb |
Host | smart-91620c6c-bac7-4dcb-ac9e-9370b8106bcd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162924501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.1162924501 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.3192791350 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 478575300396 ps |
CPU time | 1707.69 seconds |
Started | Dec 27 12:45:44 PM PST 23 |
Finished | Dec 27 01:14:20 PM PST 23 |
Peak memory | 201768 kb |
Host | smart-a7384723-ddfc-445c-8e71-6dda69c40269 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192791350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .3192791350 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.2301160767 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 3329055264 ps |
CPU time | 242.58 seconds |
Started | Dec 27 12:45:34 PM PST 23 |
Finished | Dec 27 12:49:45 PM PST 23 |
Peak memory | 315496 kb |
Host | smart-b408aea5-41cf-48a6-b7e2-f71fa754b281 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301160767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.2301160767 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.1739321477 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 3363213428 ps |
CPU time | 106.16 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:47:21 PM PST 23 |
Peak memory | 210184 kb |
Host | smart-db938fa1-e7c4-41b6-8b97-de3fe17fe7fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739321477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1739321477 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.171358386 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 3105013946 ps |
CPU time | 95.01 seconds |
Started | Dec 27 12:45:28 PM PST 23 |
Finished | Dec 27 12:47:10 PM PST 23 |
Peak memory | 338056 kb |
Host | smart-394da61c-a7db-41f0-bb7b-38b049167729 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171358386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.sram_ctrl_max_throughput.171358386 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3790193245 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 10624712717 ps |
CPU time | 73.73 seconds |
Started | Dec 27 12:45:43 PM PST 23 |
Finished | Dec 27 12:47:05 PM PST 23 |
Peak memory | 210972 kb |
Host | smart-3b559245-31c2-4674-a5b2-3155600d557e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790193245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.3790193245 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.2136606525 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 53017993212 ps |
CPU time | 313.86 seconds |
Started | Dec 27 12:45:55 PM PST 23 |
Finished | Dec 27 12:51:20 PM PST 23 |
Peak memory | 201940 kb |
Host | smart-b79ce913-473d-4e28-ae40-898e9e779209 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136606525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.2136606525 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.4001567483 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 32130378021 ps |
CPU time | 344.3 seconds |
Started | Dec 27 12:45:43 PM PST 23 |
Finished | Dec 27 12:51:36 PM PST 23 |
Peak memory | 321696 kb |
Host | smart-42dc2379-2840-4ca4-bc1d-1462347ce5c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001567483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.4001567483 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.4039254352 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 971382352 ps |
CPU time | 41.87 seconds |
Started | Dec 27 12:45:30 PM PST 23 |
Finished | Dec 27 12:46:19 PM PST 23 |
Peak memory | 201904 kb |
Host | smart-d71a1bd6-11e9-40b1-95b3-555606adfeba |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039254352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.4039254352 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3147713798 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 8718222200 ps |
CPU time | 252.35 seconds |
Started | Dec 27 12:45:31 PM PST 23 |
Finished | Dec 27 12:49:51 PM PST 23 |
Peak memory | 201988 kb |
Host | smart-eed6750f-4472-4a1c-ae10-096a48af211b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147713798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.3147713798 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.145896980 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 686555319 ps |
CPU time | 13.12 seconds |
Started | Dec 27 12:45:38 PM PST 23 |
Finished | Dec 27 12:45:59 PM PST 23 |
Peak memory | 202176 kb |
Host | smart-a993b03a-fccd-4435-88bc-fa558bacbbd8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145896980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.145896980 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.873782492 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 15403370172 ps |
CPU time | 747.91 seconds |
Started | Dec 27 12:45:21 PM PST 23 |
Finished | Dec 27 12:57:58 PM PST 23 |
Peak memory | 374804 kb |
Host | smart-0996733e-760b-4b30-bcc1-e06ee0765288 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873782492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.873782492 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.3566496970 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 3595586049 ps |
CPU time | 90.12 seconds |
Started | Dec 27 12:45:26 PM PST 23 |
Finished | Dec 27 12:47:04 PM PST 23 |
Peak memory | 334876 kb |
Host | smart-025c7925-8625-40b7-b757-2526004af12d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566496970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3566496970 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.3332939857 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 60746670789 ps |
CPU time | 2580.84 seconds |
Started | Dec 27 12:45:54 PM PST 23 |
Finished | Dec 27 01:29:05 PM PST 23 |
Peak memory | 379028 kb |
Host | smart-286281ee-3191-4fef-928b-32a26050b2b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332939857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.3332939857 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1604078296 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 786002960 ps |
CPU time | 6139.83 seconds |
Started | Dec 27 12:45:50 PM PST 23 |
Finished | Dec 27 02:28:18 PM PST 23 |
Peak memory | 519140 kb |
Host | smart-50a7f1a8-046e-4d04-b3c6-8414d490dda2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1604078296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1604078296 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.259912619 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 4584867332 ps |
CPU time | 373.93 seconds |
Started | Dec 27 12:45:40 PM PST 23 |
Finished | Dec 27 12:52:03 PM PST 23 |
Peak memory | 201952 kb |
Host | smart-7f5e559c-c283-473f-8082-082e40dfbc99 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259912619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_stress_pipeline.259912619 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2678074430 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 811897145 ps |
CPU time | 54.83 seconds |
Started | Dec 27 12:45:20 PM PST 23 |
Finished | Dec 27 12:46:24 PM PST 23 |
Peak memory | 285852 kb |
Host | smart-3533783b-4398-4de2-8045-5b594f9e74b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678074430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2678074430 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4238030069 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 22885351905 ps |
CPU time | 1413.87 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 01:08:21 PM PST 23 |
Peak memory | 380012 kb |
Host | smart-59b2bba1-b97f-4899-82fe-7cb1bea6f17f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238030069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.4238030069 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.180194423 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 22692185 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 12:44:33 PM PST 23 |
Peak memory | 201840 kb |
Host | smart-1cd00c22-9f2d-4717-b395-be5f7f1da8ce |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180194423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.180194423 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.4095825685 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 488788494690 ps |
CPU time | 2022.85 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 01:18:25 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-55e356c9-2e83-4dd5-b6f4-1dee8edd40c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095825685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 4095825685 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.2730831696 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 4290290100 ps |
CPU time | 425.21 seconds |
Started | Dec 27 12:45:07 PM PST 23 |
Finished | Dec 27 12:52:19 PM PST 23 |
Peak memory | 371460 kb |
Host | smart-89b1aff7-81f6-44d1-9c94-ea3d9f0b0f61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730831696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.2730831696 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.779925977 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 3042392758 ps |
CPU time | 55.39 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:45:38 PM PST 23 |
Peak memory | 301292 kb |
Host | smart-45119d79-fdff-4a39-a8f9-3b287fe37243 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779925977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.779925977 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4240601842 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 3530775394 ps |
CPU time | 74.15 seconds |
Started | Dec 27 12:44:59 PM PST 23 |
Finished | Dec 27 12:46:21 PM PST 23 |
Peak memory | 210508 kb |
Host | smart-d982fd90-4b2d-4ff0-bc8b-80c3f7577f09 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240601842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.4240601842 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.348849883 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 8951373528 ps |
CPU time | 147.8 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:47:29 PM PST 23 |
Peak memory | 202072 kb |
Host | smart-e51fe2ba-dc31-4302-bff3-70930c92d358 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348849883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ mem_walk.348849883 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.2680208261 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 5416889860 ps |
CPU time | 835.86 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:58:30 PM PST 23 |
Peak memory | 380020 kb |
Host | smart-29baa9dd-9b9e-46b0-9173-dc4f861f0f5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680208261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.2680208261 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.1548938312 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 515370189 ps |
CPU time | 22.97 seconds |
Started | Dec 27 12:44:44 PM PST 23 |
Finished | Dec 27 12:45:12 PM PST 23 |
Peak memory | 201932 kb |
Host | smart-53bd9019-33fe-4771-8876-07869e95d82b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548938312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.1548938312 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1944823627 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 16216797225 ps |
CPU time | 284.49 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:49:46 PM PST 23 |
Peak memory | 202072 kb |
Host | smart-275a2108-6097-409c-926e-6e5b39acb281 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944823627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1944823627 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.2865647400 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 422891895 ps |
CPU time | 13.34 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 12:45:27 PM PST 23 |
Peak memory | 202292 kb |
Host | smart-d476eb57-87c6-435a-b6a4-bc9e533d3f0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865647400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2865647400 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.3767564910 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 1219329524 ps |
CPU time | 127.62 seconds |
Started | Dec 27 12:45:01 PM PST 23 |
Finished | Dec 27 12:47:16 PM PST 23 |
Peak memory | 329464 kb |
Host | smart-aded7a29-387d-44d5-ad8f-cecca4cdf86f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767564910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3767564910 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.274928277 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 2246653170 ps |
CPU time | 54.7 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:45:48 PM PST 23 |
Peak memory | 299136 kb |
Host | smart-a7735577-ba85-44cc-8602-66519404707d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274928277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.274928277 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1182528040 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 1484786452 ps |
CPU time | 2667.49 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 01:29:39 PM PST 23 |
Peak memory | 777692 kb |
Host | smart-40d90bae-2427-455f-9f81-855afa4d943c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1182528040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1182528040 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1534621921 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 5731346914 ps |
CPU time | 228.29 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:48:45 PM PST 23 |
Peak memory | 202068 kb |
Host | smart-424f8b71-1a3b-4624-ad84-2e62709fbb82 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534621921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.1534621921 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3851122356 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 2882666623 ps |
CPU time | 32.75 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:45:29 PM PST 23 |
Peak memory | 234812 kb |
Host | smart-7db9a7c0-99a3-4964-a7cd-da70b7abc712 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851122356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3851122356 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2550197031 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 10913207901 ps |
CPU time | 613.89 seconds |
Started | Dec 27 12:44:18 PM PST 23 |
Finished | Dec 27 12:54:42 PM PST 23 |
Peak memory | 377532 kb |
Host | smart-bbe5a495-ae00-4ab5-b0c7-3518f9e2d38d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550197031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.2550197031 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.1539672756 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 11277216 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:44:19 PM PST 23 |
Finished | Dec 27 12:44:29 PM PST 23 |
Peak memory | 201720 kb |
Host | smart-2f754409-bcff-4f09-a6f0-0e8cc214d815 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539672756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1539672756 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.1511940181 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 74243988249 ps |
CPU time | 1804.35 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 01:14:58 PM PST 23 |
Peak memory | 202076 kb |
Host | smart-a539ebc1-926b-4bf0-ba9b-aa54d430fbac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511940181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 1511940181 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.451514136 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 13483497746 ps |
CPU time | 575.4 seconds |
Started | Dec 27 12:44:36 PM PST 23 |
Finished | Dec 27 12:54:19 PM PST 23 |
Peak memory | 363136 kb |
Host | smart-2a098492-615d-47e7-ac4d-f5dd43b355a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451514136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable .451514136 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.2775386276 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 12451719252 ps |
CPU time | 120.07 seconds |
Started | Dec 27 12:44:13 PM PST 23 |
Finished | Dec 27 12:46:24 PM PST 23 |
Peak memory | 202116 kb |
Host | smart-40e65dcc-100c-41cb-8fc1-f0d0e41a5329 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775386276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.2775386276 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.4285206441 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 1402399778 ps |
CPU time | 51.29 seconds |
Started | Dec 27 12:44:24 PM PST 23 |
Finished | Dec 27 12:45:25 PM PST 23 |
Peak memory | 283772 kb |
Host | smart-245d5b37-41ae-4e36-b558-aea0e0a7a645 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285206441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.4285206441 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4213933722 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 18280987910 ps |
CPU time | 147.05 seconds |
Started | Dec 27 12:44:14 PM PST 23 |
Finished | Dec 27 12:46:53 PM PST 23 |
Peak memory | 211104 kb |
Host | smart-445fc37c-9200-470b-b120-2849c13ea435 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213933722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.4213933722 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.2881930435 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 5339373598 ps |
CPU time | 125.67 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:46:43 PM PST 23 |
Peak memory | 202052 kb |
Host | smart-3a5430e3-9eff-4a65-b2b5-72e6549eab07 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881930435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.2881930435 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.1843976474 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 81745256086 ps |
CPU time | 843.3 seconds |
Started | Dec 27 12:44:40 PM PST 23 |
Finished | Dec 27 12:58:50 PM PST 23 |
Peak memory | 379396 kb |
Host | smart-96dfc8b8-1b73-4314-82f9-3b68ba07b79c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843976474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.1843976474 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.1935338067 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 2358956546 ps |
CPU time | 9.41 seconds |
Started | Dec 27 12:44:55 PM PST 23 |
Finished | Dec 27 12:45:12 PM PST 23 |
Peak memory | 201976 kb |
Host | smart-a7eff49c-71a1-4cfc-b4ea-a130d59a44c0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935338067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.1935338067 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4001789411 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 25935437558 ps |
CPU time | 577.55 seconds |
Started | Dec 27 12:44:11 PM PST 23 |
Finished | Dec 27 12:54:04 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-99f79188-24d4-470e-96bb-ca217298a463 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001789411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.4001789411 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.3979199484 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 1399786143 ps |
CPU time | 6.15 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:45:00 PM PST 23 |
Peak memory | 202348 kb |
Host | smart-a840d691-8d36-4bef-abf0-bedce4c16343 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979199484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3979199484 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.3232781854 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 13444149465 ps |
CPU time | 483.31 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 12:52:45 PM PST 23 |
Peak memory | 361628 kb |
Host | smart-acc3340f-c7ee-4f93-9808-e283508aea92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232781854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3232781854 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.864288689 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 1325593314 ps |
CPU time | 130.1 seconds |
Started | Dec 27 12:44:13 PM PST 23 |
Finished | Dec 27 12:46:34 PM PST 23 |
Peak memory | 354304 kb |
Host | smart-03b71ade-1903-4c08-a21c-911a2d29a1c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864288689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.864288689 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.583640082 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 471804781973 ps |
CPU time | 2356.11 seconds |
Started | Dec 27 12:44:23 PM PST 23 |
Finished | Dec 27 01:23:48 PM PST 23 |
Peak memory | 372856 kb |
Host | smart-8d4a2f20-ecdc-4c2c-a6d5-9febc6cdba41 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583640082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_stress_all.583640082 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3355628582 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1067579557 ps |
CPU time | 3535.92 seconds |
Started | Dec 27 12:45:08 PM PST 23 |
Finished | Dec 27 01:44:10 PM PST 23 |
Peak memory | 680320 kb |
Host | smart-5759571a-921d-459d-9b4a-634630cef8b5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3355628582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3355628582 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3596894519 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 9490075301 ps |
CPU time | 284.35 seconds |
Started | Dec 27 12:44:11 PM PST 23 |
Finished | Dec 27 12:49:07 PM PST 23 |
Peak memory | 202000 kb |
Host | smart-5cba0d99-5a1f-446c-9e1f-abe3fd1b48c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596894519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.3596894519 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3509710863 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 774227648 ps |
CPU time | 71.65 seconds |
Started | Dec 27 12:44:13 PM PST 23 |
Finished | Dec 27 12:45:35 PM PST 23 |
Peak memory | 314420 kb |
Host | smart-fa27f6d0-ef94-4b5f-b09d-48b189bdd1e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509710863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3509710863 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3088247568 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 13241625917 ps |
CPU time | 1248.44 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 01:05:49 PM PST 23 |
Peak memory | 381012 kb |
Host | smart-ef1f317a-842c-43f5-9bee-dd324a955aa1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088247568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.3088247568 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.3304921326 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 47066514 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:44:14 PM PST 23 |
Finished | Dec 27 12:44:25 PM PST 23 |
Peak memory | 201252 kb |
Host | smart-d82a6220-8766-4513-94cb-20afedb6f861 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304921326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3304921326 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.1880601721 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 221456386822 ps |
CPU time | 971.76 seconds |
Started | Dec 27 12:44:52 PM PST 23 |
Finished | Dec 27 01:01:12 PM PST 23 |
Peak memory | 202060 kb |
Host | smart-1d757654-6c43-4072-a182-fbf78c129870 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880601721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1880601721 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.791706312 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 9806933750 ps |
CPU time | 723.36 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:56:59 PM PST 23 |
Peak memory | 377880 kb |
Host | smart-b710a57e-8afe-4f68-9499-3e96332648b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791706312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable .791706312 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.265485374 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 22454217295 ps |
CPU time | 70.84 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:46:04 PM PST 23 |
Peak memory | 213948 kb |
Host | smart-a4642c41-73cb-4b8d-bd13-5ec7cdab6c82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265485374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esca lation.265485374 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.3346807417 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 741529503 ps |
CPU time | 61.36 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:45:58 PM PST 23 |
Peak memory | 318544 kb |
Host | smart-dd28930b-b473-4c1b-bafd-6d729124744c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346807417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.3346807417 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.346673714 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 19333777126 ps |
CPU time | 131.83 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:46:55 PM PST 23 |
Peak memory | 218344 kb |
Host | smart-e93234e6-5012-4d93-9b96-6312a7808d7d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346673714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_mem_partial_access.346673714 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.3661142822 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 73747588825 ps |
CPU time | 169.45 seconds |
Started | Dec 27 12:44:38 PM PST 23 |
Finished | Dec 27 12:47:35 PM PST 23 |
Peak memory | 202104 kb |
Host | smart-38d88d10-d5d3-481c-abd9-64a05319ab96 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661142822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.3661142822 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.3363615203 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 23826151790 ps |
CPU time | 366.92 seconds |
Started | Dec 27 12:44:16 PM PST 23 |
Finished | Dec 27 12:50:34 PM PST 23 |
Peak memory | 354104 kb |
Host | smart-277402f6-9bde-4e4c-b882-a3d013374539 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363615203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3363615203 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.2761628136 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 4593709733 ps |
CPU time | 24.04 seconds |
Started | Dec 27 12:44:38 PM PST 23 |
Finished | Dec 27 12:45:09 PM PST 23 |
Peak memory | 201992 kb |
Host | smart-1affd2b6-7228-45c4-af55-1f087c33b56a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761628136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.2761628136 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.416580344 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 13923487757 ps |
CPU time | 328.17 seconds |
Started | Dec 27 12:44:50 PM PST 23 |
Finished | Dec 27 12:50:25 PM PST 23 |
Peak memory | 201996 kb |
Host | smart-16966e77-5822-4d17-8733-3c9b3710e7ee |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416580344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.sram_ctrl_partial_access_b2b.416580344 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.224856340 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 2814281425 ps |
CPU time | 6.08 seconds |
Started | Dec 27 12:44:21 PM PST 23 |
Finished | Dec 27 12:44:37 PM PST 23 |
Peak memory | 202352 kb |
Host | smart-27845841-461e-4e00-9dfd-10c4458196fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224856340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.224856340 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.2921958398 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 9455569855 ps |
CPU time | 53.56 seconds |
Started | Dec 27 12:44:22 PM PST 23 |
Finished | Dec 27 12:45:24 PM PST 23 |
Peak memory | 210340 kb |
Host | smart-7173acdf-d4d5-42f3-bacf-b08f62046a00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921958398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2921958398 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.474186014 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 1344666240 ps |
CPU time | 21.54 seconds |
Started | Dec 27 12:45:02 PM PST 23 |
Finished | Dec 27 12:45:31 PM PST 23 |
Peak memory | 201952 kb |
Host | smart-fe046285-6aa4-4f08-b070-71a574d8336f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474186014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.474186014 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1904920959 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 2762265538 ps |
CPU time | 4948.15 seconds |
Started | Dec 27 12:44:30 PM PST 23 |
Finished | Dec 27 02:07:07 PM PST 23 |
Peak memory | 610232 kb |
Host | smart-33ed3cf8-a396-4cbf-9d7f-d365400bdd72 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1904920959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1904920959 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1149683854 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 3329090253 ps |
CPU time | 239.04 seconds |
Started | Dec 27 12:44:37 PM PST 23 |
Finished | Dec 27 12:48:44 PM PST 23 |
Peak memory | 202036 kb |
Host | smart-151a0517-ed98-42b7-b4fd-ebc748eca7d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149683854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.1149683854 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.582891419 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 763813094 ps |
CPU time | 51.8 seconds |
Started | Dec 27 12:44:45 PM PST 23 |
Finished | Dec 27 12:45:42 PM PST 23 |
Peak memory | 287900 kb |
Host | smart-9d13ffe7-8b0d-4b6d-bdad-e985759865d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582891419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.582891419 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3983226811 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 15821761580 ps |
CPU time | 1227.08 seconds |
Started | Dec 27 12:44:08 PM PST 23 |
Finished | Dec 27 01:04:47 PM PST 23 |
Peak memory | 381028 kb |
Host | smart-f082635f-2944-473e-b1d2-81fd2dac51ae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983226811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.3983226811 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.3550368239 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 14041266 ps |
CPU time | 0.63 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:44:37 PM PST 23 |
Peak memory | 201632 kb |
Host | smart-75bcaf5c-1e06-4023-968c-6b51c314f02c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550368239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3550368239 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.3192257304 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 126068773838 ps |
CPU time | 2220.36 seconds |
Started | Dec 27 12:44:14 PM PST 23 |
Finished | Dec 27 01:21:25 PM PST 23 |
Peak memory | 202148 kb |
Host | smart-7faced70-b7cc-4074-92eb-f6d480e29d0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192257304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 3192257304 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.3280419806 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 11631653585 ps |
CPU time | 72.27 seconds |
Started | Dec 27 12:44:11 PM PST 23 |
Finished | Dec 27 12:45:34 PM PST 23 |
Peak memory | 210204 kb |
Host | smart-d3461afb-bb62-46ec-bd81-f4d6d9712e53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280419806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.3280419806 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.1790806492 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 3131996199 ps |
CPU time | 104.58 seconds |
Started | Dec 27 12:44:17 PM PST 23 |
Finished | Dec 27 12:46:12 PM PST 23 |
Peak memory | 352340 kb |
Host | smart-ac32bbe0-6982-4837-8c27-81831ece7e7a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790806492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.1790806492 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3664418923 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 3799557140 ps |
CPU time | 73.09 seconds |
Started | Dec 27 12:44:33 PM PST 23 |
Finished | Dec 27 12:45:55 PM PST 23 |
Peak memory | 211164 kb |
Host | smart-f7b9ea71-3846-4293-b183-30a3368b5b32 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664418923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.3664418923 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.2980000428 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 39412187114 ps |
CPU time | 245.2 seconds |
Started | Dec 27 12:44:53 PM PST 23 |
Finished | Dec 27 12:49:06 PM PST 23 |
Peak memory | 202048 kb |
Host | smart-6f04135b-c8a4-4cb9-82ab-ff75a1655f50 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980000428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.2980000428 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.2505982733 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 30600290892 ps |
CPU time | 855.31 seconds |
Started | Dec 27 12:44:41 PM PST 23 |
Finished | Dec 27 12:59:03 PM PST 23 |
Peak memory | 382100 kb |
Host | smart-3efe63b8-ef6a-42bb-963d-0b748341b703 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505982733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2505982733 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.3979945184 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 814288010 ps |
CPU time | 32.83 seconds |
Started | Dec 27 12:44:12 PM PST 23 |
Finished | Dec 27 12:44:56 PM PST 23 |
Peak memory | 201932 kb |
Host | smart-b341a16f-4b0e-4bf0-8222-17ec52998c7f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979945184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.3979945184 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4279038391 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 111311240615 ps |
CPU time | 427.07 seconds |
Started | Dec 27 12:44:08 PM PST 23 |
Finished | Dec 27 12:51:27 PM PST 23 |
Peak memory | 202092 kb |
Host | smart-13eeda53-30d7-497b-939a-67b02a1c877a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279038391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.4279038391 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3099488848 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 1258988175 ps |
CPU time | 13.21 seconds |
Started | Dec 27 12:44:17 PM PST 23 |
Finished | Dec 27 12:44:41 PM PST 23 |
Peak memory | 202236 kb |
Host | smart-57a48f6b-80bd-49fa-857f-5665197f917c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099488848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3099488848 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.2385478695 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 9175560578 ps |
CPU time | 624.09 seconds |
Started | Dec 27 12:44:28 PM PST 23 |
Finished | Dec 27 12:55:06 PM PST 23 |
Peak memory | 375740 kb |
Host | smart-6e4c9da1-d1b5-49ab-8949-9106d3c90a77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385478695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2385478695 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.2672618108 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 1345320994 ps |
CPU time | 25.4 seconds |
Started | Dec 27 12:44:27 PM PST 23 |
Finished | Dec 27 12:45:01 PM PST 23 |
Peak memory | 201968 kb |
Host | smart-333eaa41-9b63-4d4c-8c9c-95fa6f4e4243 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672618108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2672618108 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.336545757 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1917554911 ps |
CPU time | 3414.33 seconds |
Started | Dec 27 12:44:12 PM PST 23 |
Finished | Dec 27 01:41:18 PM PST 23 |
Peak memory | 528116 kb |
Host | smart-68768192-ed0e-46db-97ba-e22499778c1d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=336545757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.336545757 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2214635930 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 5235395041 ps |
CPU time | 198.55 seconds |
Started | Dec 27 12:44:21 PM PST 23 |
Finished | Dec 27 12:47:49 PM PST 23 |
Peak memory | 202116 kb |
Host | smart-24e3507b-d1a0-400c-8ff7-025bf62a0c2c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214635930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.2214635930 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4158411102 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 3117686806 ps |
CPU time | 175.1 seconds |
Started | Dec 27 12:44:21 PM PST 23 |
Finished | Dec 27 12:47:25 PM PST 23 |
Peak memory | 366928 kb |
Host | smart-9c3cc503-b896-483f-9559-8a26a5dbc6cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158411102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.4158411102 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3307131328 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 13733953359 ps |
CPU time | 980.43 seconds |
Started | Dec 27 12:44:52 PM PST 23 |
Finished | Dec 27 01:01:19 PM PST 23 |
Peak memory | 375944 kb |
Host | smart-3185e6cb-2c3f-4e57-98c3-e600261c94a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307131328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3307131328 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.1435121278 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 14952853 ps |
CPU time | 0.62 seconds |
Started | Dec 27 12:44:43 PM PST 23 |
Finished | Dec 27 12:44:49 PM PST 23 |
Peak memory | 201540 kb |
Host | smart-917724ce-fbf1-476d-afec-f60091a2a055 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435121278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1435121278 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.3214118575 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 768682979927 ps |
CPU time | 1160.83 seconds |
Started | Dec 27 12:44:35 PM PST 23 |
Finished | Dec 27 01:04:04 PM PST 23 |
Peak memory | 202116 kb |
Host | smart-0b2f64ac-13c7-4bc6-81c1-fab24732eafa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214118575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3214118575 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.1010924123 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 2584335473 ps |
CPU time | 74.21 seconds |
Started | Dec 27 12:44:58 PM PST 23 |
Finished | Dec 27 12:46:20 PM PST 23 |
Peak memory | 273644 kb |
Host | smart-16cefbd7-253a-4d9a-ae79-5cb525679ab3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010924123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1010924123 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.3296060788 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 77117097786 ps |
CPU time | 96.06 seconds |
Started | Dec 27 12:44:47 PM PST 23 |
Finished | Dec 27 12:46:29 PM PST 23 |
Peak memory | 210264 kb |
Host | smart-60cc6a6a-27d9-4d1c-8967-0c0b95fe06ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296060788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3296060788 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.4228018197 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 1694181679 ps |
CPU time | 45.01 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:45:47 PM PST 23 |
Peak memory | 270596 kb |
Host | smart-bed0703f-9a32-4647-834b-f26ba7fed820 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228018197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.4228018197 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.187444809 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 6256746088 ps |
CPU time | 133.48 seconds |
Started | Dec 27 12:44:35 PM PST 23 |
Finished | Dec 27 12:46:57 PM PST 23 |
Peak memory | 214320 kb |
Host | smart-4ea6d781-50ba-4a39-9f35-cbcb9c4be45d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187444809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9. sram_ctrl_mem_partial_access.187444809 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.658324180 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 7897016596 ps |
CPU time | 119.96 seconds |
Started | Dec 27 12:44:54 PM PST 23 |
Finished | Dec 27 12:47:02 PM PST 23 |
Peak memory | 201984 kb |
Host | smart-6b7b97bb-da59-4a96-bc26-ec7056a1a05b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658324180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ mem_walk.658324180 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.124578064 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 52934602239 ps |
CPU time | 2177.79 seconds |
Started | Dec 27 12:44:51 PM PST 23 |
Finished | Dec 27 01:21:15 PM PST 23 |
Peak memory | 379952 kb |
Host | smart-3879480c-c835-4cd9-8a4a-d0d09198597f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124578064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multipl e_keys.124578064 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3596433264 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 535604777 ps |
CPU time | 15.17 seconds |
Started | Dec 27 12:45:04 PM PST 23 |
Finished | Dec 27 12:45:26 PM PST 23 |
Peak memory | 243880 kb |
Host | smart-0a98491e-5e04-403a-b1e4-999dcb2e385e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596433264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3596433264 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1759558730 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 27905694506 ps |
CPU time | 149.1 seconds |
Started | Dec 27 12:44:20 PM PST 23 |
Finished | Dec 27 12:46:58 PM PST 23 |
Peak memory | 210204 kb |
Host | smart-cdf0ccd9-df6d-423f-bfb3-67d09253cf86 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759558730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.1759558730 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.1153591760 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 367252136 ps |
CPU time | 13.52 seconds |
Started | Dec 27 12:44:49 PM PST 23 |
Finished | Dec 27 12:45:09 PM PST 23 |
Peak memory | 202360 kb |
Host | smart-96f28bf1-edea-4dd9-9bb4-d5f9ff70e0c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153591760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1153591760 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.3920308295 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 11639583915 ps |
CPU time | 1229.66 seconds |
Started | Dec 27 12:45:00 PM PST 23 |
Finished | Dec 27 01:05:37 PM PST 23 |
Peak memory | 380988 kb |
Host | smart-97f6e81c-7dce-4532-8e42-448051f4ff55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920308295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3920308295 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.1617725538 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 7136848944 ps |
CPU time | 124.97 seconds |
Started | Dec 27 12:44:39 PM PST 23 |
Finished | Dec 27 12:46:51 PM PST 23 |
Peak memory | 375880 kb |
Host | smart-f943c5ff-db82-4b83-a559-f80f438c9f60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617725538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1617725538 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.542965654 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 397818708953 ps |
CPU time | 4793.54 seconds |
Started | Dec 27 12:44:56 PM PST 23 |
Finished | Dec 27 02:04:57 PM PST 23 |
Peak memory | 385100 kb |
Host | smart-6011f2aa-f1ee-45cb-991b-352aed7d83de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542965654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_stress_all.542965654 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1474607654 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 10924894598 ps |
CPU time | 5299.17 seconds |
Started | Dec 27 12:44:57 PM PST 23 |
Finished | Dec 27 02:13:24 PM PST 23 |
Peak memory | 757936 kb |
Host | smart-3e704b98-872b-41bd-a36d-31e51ea54e3e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1474607654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1474607654 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.4090113050 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 5001089984 ps |
CPU time | 377.09 seconds |
Started | Dec 27 12:44:34 PM PST 23 |
Finished | Dec 27 12:51:00 PM PST 23 |
Peak memory | 202112 kb |
Host | smart-e30dcd67-5cd4-4201-ab0c-b34678712c7f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090113050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.4090113050 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.488200220 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 10621243236 ps |
CPU time | 70.36 seconds |
Started | Dec 27 12:44:25 PM PST 23 |
Finished | Dec 27 12:45:49 PM PST 23 |
Peak memory | 317848 kb |
Host | smart-52da0f7d-7a94-4d72-b67a-5d8c15fce58c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488200220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_throughput_w_partial_write.488200220 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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