Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15409071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123753119

1

T1

8048

T2

24370

T3

185823

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	68166721	1			T1	4424		T2	66560		T3	101973
values[0x0]	33970989	1			T1	2115		T2	22841		T3	49137
values[0x1]	37024480	1			T1	2328		T2	44443		T3	53291

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7864391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

131297799

1

T1

8472

T2

79194

T3

195132

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	530164	1			T1	36		T2	469		T3	795
valid_sources[0x01]	492590	1			T1	37		T2	540		T3	770
valid_sources[0x02]	444117	1			T1	54		T2	548		T3	781
valid_sources[0x03]	463192	1			T1	30		T2	519		T3	797
valid_sources[0x04]	463040	1			T1	30		T2	611		T3	692
valid_sources[0x05]	506617	1			T1	38		T2	562		T3	850
valid_sources[0x06]	486013	1			T1	26		T2	491		T3	799
valid_sources[0x07]	462476	1			T1	35		T2	456		T3	801
valid_sources[0x08]	466406	1			T1	37		T2	490		T3	790
valid_sources[0x09]	476083	1			T1	34		T2	530		T3	839
valid_sources[0x0a]	451041	1			T1	42		T2	532		T3	731
valid_sources[0x0b]	477606	1			T1	29		T2	474		T3	745
valid_sources[0x0c]	475876	1			T1	36		T2	468		T3	821
valid_sources[0x0d]	453232	1			T1	38		T2	545		T3	774
valid_sources[0x0e]	475011	1			T1	29		T2	489		T3	759
valid_sources[0x0f]	1700673	1			T1	21		T2	550		T3	744
valid_sources[0x10]	569053	1			T1	29		T2	609		T3	876
valid_sources[0x11]	468768	1			T1	41		T2	499		T3	764
valid_sources[0x12]	452478	1			T1	36		T2	566		T3	836
valid_sources[0x13]	936994	1			T1	32		T2	560		T3	826
valid_sources[0x14]	1523203	1			T1	29		T2	527		T3	755
valid_sources[0x15]	457436	1			T1	33		T2	514		T3	768
valid_sources[0x16]	447795	1			T1	27		T2	446		T3	727
valid_sources[0x17]	469488	1			T1	54		T2	510		T3	725
valid_sources[0x18]	457110	1			T1	28		T2	597		T3	803
valid_sources[0x19]	450702	1			T1	30		T2	546		T3	751
valid_sources[0x1a]	479502	1			T1	32		T2	550		T3	753
valid_sources[0x1b]	449038	1			T1	23		T2	477		T3	854
valid_sources[0x1c]	460044	1			T1	46		T2	511		T3	790
valid_sources[0x1d]	445997	1			T1	44		T2	482		T3	756
valid_sources[0x1e]	445219	1			T1	47		T2	529		T3	843
valid_sources[0x1f]	446739	1			T1	22		T2	507		T3	837
valid_sources[0x20]	504403	1			T1	35		T2	484		T3	792
valid_sources[0x21]	856306	1			T1	35		T2	554		T3	790
valid_sources[0x22]	446627	1			T1	19		T2	562		T3	776
valid_sources[0x23]	485780	1			T1	30		T2	510		T3	696
valid_sources[0x24]	464119	1			T1	38		T2	535		T3	789
valid_sources[0x25]	449972	1			T1	31		T2	470		T3	866
valid_sources[0x26]	469659	1			T1	31		T2	555		T3	832
valid_sources[0x27]	480699	1			T1	31		T2	510		T3	806
valid_sources[0x28]	468877	1			T1	33		T2	523		T3	851
valid_sources[0x29]	477224	1			T1	24		T2	570		T3	893
valid_sources[0x2a]	495963	1			T1	28		T2	538		T3	776
valid_sources[0x2b]	447407	1			T1	34		T2	464		T3	769
valid_sources[0x2c]	497666	1			T1	34		T2	529		T3	799
valid_sources[0x2d]	444687	1			T1	32		T2	565		T3	804
valid_sources[0x2e]	455740	1			T1	25		T2	515		T3	840
valid_sources[0x2f]	466262	1			T1	34		T2	533		T3	889
valid_sources[0x30]	1901081	1			T1	33		T2	514		T3	801
valid_sources[0x31]	1448102	1			T1	38		T2	493		T3	887
valid_sources[0x32]	477820	1			T1	45		T2	476		T3	848
valid_sources[0x33]	464103	1			T1	25		T2	530		T3	807
valid_sources[0x34]	473790	1			T1	32		T2	575		T3	890
valid_sources[0x35]	467663	1			T1	38		T2	444		T3	774
valid_sources[0x36]	526567	1			T1	32		T2	474		T3	774
valid_sources[0x37]	446482	1			T1	31		T2	584		T3	796
valid_sources[0x38]	459801	1			T1	25		T2	542		T3	783
valid_sources[0x39]	467879	1			T1	35		T2	469		T3	760
valid_sources[0x3a]	504561	1			T1	32		T2	462		T3	801
valid_sources[0x3b]	465415	1			T1	38		T2	455		T3	821
valid_sources[0x3c]	456620	1			T1	43		T2	531		T3	806
valid_sources[0x3d]	438985	1			T1	27		T2	500		T3	811
valid_sources[0x3e]	481814	1			T1	31		T2	480		T3	870
valid_sources[0x3f]	656202	1			T1	30		T2	506		T3	808
valid_sources[0x40]	1170312	1			T1	45		T2	511		T3	841
valid_sources[0x41]	449249	1			T1	48		T2	474		T3	741
valid_sources[0x42]	469667	1			T1	27		T2	569		T3	821
valid_sources[0x43]	442454	1			T1	36		T2	488		T3	760
valid_sources[0x44]	450316	1			T1	28		T2	564		T3	806
valid_sources[0x45]	443236	1			T1	22		T2	526		T3	777
valid_sources[0x46]	490156	1			T1	48		T2	537		T3	827
valid_sources[0x47]	451996	1			T1	35		T2	538		T3	848
valid_sources[0x48]	457818	1			T1	41		T2	580		T3	822
valid_sources[0x49]	462517	1			T1	39		T2	529		T3	799
valid_sources[0x4a]	480887	1			T1	37		T2	483		T3	888
valid_sources[0x4b]	494393	1			T1	45		T2	502		T3	773
valid_sources[0x4c]	448995	1			T1	50		T2	547		T3	926
valid_sources[0x4d]	441864	1			T1	46		T2	474		T3	784
valid_sources[0x4e]	455209	1			T1	36		T2	532		T3	827
valid_sources[0x4f]	459932	1			T1	37		T2	548		T3	811
valid_sources[0x50]	465948	1			T1	19		T2	540		T3	757
valid_sources[0x51]	450380	1			T1	39		T2	478		T3	808
valid_sources[0x52]	448633	1			T1	24		T2	600		T3	811
valid_sources[0x53]	449327	1			T1	37		T2	557		T3	775
valid_sources[0x54]	721807	1			T1	32		T2	523		T3	735
valid_sources[0x55]	489682	1			T1	33		T2	506		T3	768
valid_sources[0x56]	506689	1			T1	36		T2	503		T3	782
valid_sources[0x57]	460744	1			T1	21		T2	458		T3	811
valid_sources[0x58]	487171	1			T1	30		T2	523		T3	839
valid_sources[0x59]	454793	1			T1	26		T2	511		T3	798
valid_sources[0x5a]	452629	1			T1	40		T2	547		T3	862
valid_sources[0x5b]	463415	1			T1	40		T2	490		T3	820
valid_sources[0x5c]	456996	1			T1	39		T2	565		T3	785
valid_sources[0x5d]	453606	1			T1	31		T2	562		T3	861
valid_sources[0x5e]	449515	1			T1	32		T2	462		T3	794
valid_sources[0x5f]	456187	1			T1	44		T2	538		T3	820
valid_sources[0x60]	473431	1			T1	38		T2	506		T3	744
valid_sources[0x61]	491308	1			T1	46		T2	527		T3	771
valid_sources[0x62]	451445	1			T1	34		T2	531		T3	796
valid_sources[0x63]	462666	1			T1	37		T2	555		T3	813
valid_sources[0x64]	448834	1			T1	27		T2	527		T3	735
valid_sources[0x65]	464461	1			T1	37		T2	513		T3	732
valid_sources[0x66]	1418773	1			T1	31		T2	560		T3	830
valid_sources[0x67]	470742	1			T1	36		T2	511		T3	723
valid_sources[0x68]	456606	1			T1	31		T2	512		T3	684
valid_sources[0x69]	444990	1			T1	39		T2	452		T3	799
valid_sources[0x6a]	476855	1			T1	45		T2	512		T3	772
valid_sources[0x6b]	518284	1			T1	21		T2	502		T3	735
valid_sources[0x6c]	465741	1			T1	41		T2	483		T3	744
valid_sources[0x6d]	487019	1			T1	48		T2	502		T3	805
valid_sources[0x6e]	453269	1			T1	49		T2	543		T3	700
valid_sources[0x6f]	449457	1			T1	32		T2	577		T3	754
valid_sources[0x70]	446303	1			T1	38		T2	490		T3	870
valid_sources[0x71]	470615	1			T1	35		T2	480		T3	811
valid_sources[0x72]	446256	1			T1	42		T2	566		T3	829
valid_sources[0x73]	472533	1			T1	28		T2	534		T3	855
valid_sources[0x74]	495885	1			T1	34		T2	467		T3	805
valid_sources[0x75]	453963	1			T1	27		T2	498		T3	839
valid_sources[0x76]	452056	1			T1	38		T2	485		T3	746
valid_sources[0x77]	481675	1			T1	36		T2	607		T3	759
valid_sources[0x78]	465349	1			T1	30		T2	571		T3	822
valid_sources[0x79]	493080	1			T1	34		T2	480		T3	853
valid_sources[0x7a]	862679	1			T1	47		T2	509		T3	769
valid_sources[0x7b]	446007	1			T1	42		T2	561		T3	787
valid_sources[0x7c]	493669	1			T1	36		T2	544		T3	773
valid_sources[0x7d]	459577	1			T1	26		T2	512		T3	791
valid_sources[0x7e]	440177	1			T1	44		T2	439		T3	670
valid_sources[0x7f]	457554	1			T1	40		T2	463		T3	795
valid_sources[0x80]	486874	1			T1	28		T2	553		T3	741

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60414792

1

T1

4020

T2

12039

T3

92687

values[0x0]

all_enables

biggest_size

31673534

1

T1

1989

T2

6262

T3

46352

values[0x1]

all_enables

biggest_size

31664793

1

T1

2039

T2

6069

T3

46784

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43657726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

154504

1

T2

1

T3

9

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43681514	1			T1	3608		T2	98418		T3	377053
values[0x0]	63438	1			T2	1		T3	18		T4	5
values[0x1]	67278	1			T1	1		T2	5		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29107247	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14704983

1

T1

1198

T2

32876

T3

126172

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	165956	1			T3	1453		T4	112		T8	83
valid_sources[0x01]	150493	1			T3	1451		T4	80		T8	176
valid_sources[0x02]	225053	1			T3	1448		T4	98		T8	125
valid_sources[0x03]	142870	1			T3	1491		T4	88		T8	99
valid_sources[0x04]	175259	1			T3	1464		T4	97		T8	126
valid_sources[0x05]	129134	1			T3	1389		T4	84		T8	81
valid_sources[0x06]	128245	1			T1	3609		T3	1441		T4	72
valid_sources[0x07]	164314	1			T3	1536		T4	76		T8	105
valid_sources[0x08]	136684	1			T3	1536		T4	74		T8	60
valid_sources[0x09]	388651	1			T3	1411		T4	73		T8	337
valid_sources[0x0a]	289326	1			T3	1468		T4	88		T8	80
valid_sources[0x0b]	160831	1			T3	1424		T4	79		T8	93
valid_sources[0x0c]	126630	1			T3	1470		T4	83		T8	212
valid_sources[0x0d]	130239	1			T3	1419		T4	80		T8	230
valid_sources[0x0e]	129015	1			T3	1438		T4	93		T8	126
valid_sources[0x0f]	191538	1			T3	1468		T4	79		T8	156
valid_sources[0x10]	162500	1			T3	1468		T4	85		T8	114
valid_sources[0x11]	128791	1			T3	1547		T4	81		T8	45
valid_sources[0x12]	140282	1			T3	1467		T4	97		T8	219
valid_sources[0x13]	143208	1			T3	1480		T4	74		T8	130
valid_sources[0x14]	133099	1			T3	1455		T4	97		T8	71
valid_sources[0x15]	143318	1			T3	1535		T4	78		T8	97
valid_sources[0x16]	131064	1			T3	1480		T4	86		T8	117
valid_sources[0x17]	131426	1			T3	1463		T4	90		T8	128
valid_sources[0x18]	159126	1			T3	1463		T4	70		T8	45
valid_sources[0x19]	129517	1			T3	1524		T4	83		T8	78
valid_sources[0x1a]	129490	1			T3	1474		T4	89		T8	72
valid_sources[0x1b]	177937	1			T3	1412		T4	91		T8	107
valid_sources[0x1c]	161491	1			T3	1528		T4	76		T8	93
valid_sources[0x1d]	123699	1			T3	1499		T4	79		T8	147
valid_sources[0x1e]	223600	1			T3	1415		T4	66		T8	264
valid_sources[0x1f]	142600	1			T3	1437		T4	93		T8	88
valid_sources[0x20]	134814	1			T3	1478		T4	104		T8	165
valid_sources[0x21]	148118	1			T3	1524		T4	94		T8	93
valid_sources[0x22]	171988	1			T3	1455		T4	93		T8	105
valid_sources[0x23]	161785	1			T3	1436		T4	80		T8	131
valid_sources[0x24]	125901	1			T3	1395		T4	97		T8	153
valid_sources[0x25]	161161	1			T3	1490		T4	85		T8	255
valid_sources[0x26]	218486	1			T3	1443		T4	87		T8	180
valid_sources[0x27]	225007	1			T3	1495		T4	82		T8	65
valid_sources[0x28]	146124	1			T3	1469		T4	102		T8	122
valid_sources[0x29]	126441	1			T3	1499		T4	94		T8	76
valid_sources[0x2a]	128961	1			T3	1382		T4	90		T8	104
valid_sources[0x2b]	125526	1			T3	1501		T4	66		T8	79
valid_sources[0x2c]	124107	1			T3	1498		T4	98		T8	66
valid_sources[0x2d]	163375	1			T3	1487		T4	93		T8	218
valid_sources[0x2e]	140649	1			T3	1453		T4	80		T8	153
valid_sources[0x2f]	125228	1			T3	1480		T4	89		T8	136
valid_sources[0x30]	128529	1			T3	1452		T4	70		T8	149
valid_sources[0x31]	130395	1			T3	1492		T4	89		T8	154
valid_sources[0x32]	159180	1			T3	1481		T4	81		T8	138
valid_sources[0x33]	216203	1			T3	1559		T4	75		T8	217
valid_sources[0x34]	267076	1			T3	1444		T4	69		T8	171
valid_sources[0x35]	125675	1			T3	1466		T4	92		T8	158
valid_sources[0x36]	142347	1			T3	1481		T4	97		T8	180
valid_sources[0x37]	256951	1			T3	1478		T4	73		T8	56
valid_sources[0x38]	125793	1			T3	1471		T4	70		T8	248
valid_sources[0x39]	395750	1			T3	1513		T4	100		T8	169
valid_sources[0x3a]	141994	1			T3	1389		T4	87		T8	74
valid_sources[0x3b]	147379	1			T3	1478		T4	99		T8	94
valid_sources[0x3c]	126524	1			T3	1464		T4	73		T8	95
valid_sources[0x3d]	127085	1			T3	1574		T4	92		T8	51
valid_sources[0x3e]	196875	1			T3	1496		T4	79		T8	80
valid_sources[0x3f]	128950	1			T3	1489		T4	79		T8	181
valid_sources[0x40]	132266	1			T3	1448		T4	88		T8	33
valid_sources[0x41]	133729	1			T3	1428		T4	76		T8	88
valid_sources[0x42]	136013	1			T3	1448		T4	86		T8	141
valid_sources[0x43]	182285	1			T3	1429		T4	86		T8	169
valid_sources[0x44]	158743	1			T3	1515		T4	94		T8	180
valid_sources[0x45]	125734	1			T3	1491		T4	78		T8	126
valid_sources[0x46]	126958	1			T3	1519		T4	59		T8	176
valid_sources[0x47]	257509	1			T3	1403		T4	101		T8	123
valid_sources[0x48]	182984	1			T3	1477		T4	81		T8	169
valid_sources[0x49]	127397	1			T3	1464		T4	80		T8	55
valid_sources[0x4a]	141076	1			T3	1462		T4	70		T8	139
valid_sources[0x4b]	125114	1			T3	1436		T4	94		T8	110
valid_sources[0x4c]	128168	1			T3	1434		T4	96		T8	104
valid_sources[0x4d]	263727	1			T3	1419		T4	108		T8	117
valid_sources[0x4e]	126073	1			T3	1538		T4	81		T8	94
valid_sources[0x4f]	224908	1			T2	98424		T3	1535		T4	79
valid_sources[0x50]	142017	1			T3	1483		T4	93		T8	124
valid_sources[0x51]	125695	1			T3	1469		T4	76		T8	95
valid_sources[0x52]	563508	1			T3	1537		T4	88		T8	105
valid_sources[0x53]	125431	1			T3	1441		T4	82		T8	186
valid_sources[0x54]	185977	1			T3	1482		T4	83		T8	167
valid_sources[0x55]	127021	1			T3	1506		T4	87		T8	172
valid_sources[0x56]	162899	1			T3	1534		T4	87		T8	142
valid_sources[0x57]	194150	1			T3	1503		T4	72		T8	142
valid_sources[0x58]	191340	1			T3	1486		T4	92		T8	222
valid_sources[0x59]	125628	1			T3	1470		T4	103		T8	101
valid_sources[0x5a]	126775	1			T3	1478		T4	72		T8	153
valid_sources[0x5b]	158678	1			T3	1450		T4	83		T8	148
valid_sources[0x5c]	127083	1			T3	1496		T4	82		T8	113
valid_sources[0x5d]	128360	1			T3	1516		T4	75		T8	69
valid_sources[0x5e]	160159	1			T3	1524		T4	70		T8	184
valid_sources[0x5f]	123867	1			T3	1425		T4	78		T8	109
valid_sources[0x60]	125174	1			T3	1433		T4	105		T8	195
valid_sources[0x61]	487490	1			T3	1528		T4	90		T8	73
valid_sources[0x62]	704421	1			T3	1428		T4	89		T8	94
valid_sources[0x63]	137118	1			T3	1451		T4	80		T8	128
valid_sources[0x64]	518793	1			T3	1529		T4	82		T8	115
valid_sources[0x65]	174397	1			T3	1512		T4	83		T8	185
valid_sources[0x66]	173918	1			T3	1493		T4	83		T8	62
valid_sources[0x67]	127963	1			T3	1443		T4	101		T8	133
valid_sources[0x68]	125124	1			T3	1457		T4	76		T8	93
valid_sources[0x69]	246828	1			T3	1487		T4	79		T8	220
valid_sources[0x6a]	208830	1			T3	1472		T4	71		T8	86
valid_sources[0x6b]	126004	1			T3	1473		T4	75		T8	191
valid_sources[0x6c]	143097	1			T3	1479		T4	76		T8	145
valid_sources[0x6d]	126294	1			T3	1469		T4	107		T8	99
valid_sources[0x6e]	131504	1			T3	1408		T4	100		T8	94
valid_sources[0x6f]	142786	1			T3	1484		T4	99		T8	142
valid_sources[0x70]	278054	1			T3	1488		T4	72		T8	153
valid_sources[0x71]	126477	1			T3	1468		T4	92		T8	57
valid_sources[0x72]	126433	1			T3	1495		T4	68		T8	64
valid_sources[0x73]	131962	1			T3	1539		T4	106		T8	166
valid_sources[0x74]	163453	1			T3	1453		T4	98		T8	225
valid_sources[0x75]	129799	1			T3	1469		T4	87		T8	102
valid_sources[0x76]	127072	1			T3	1478		T4	75		T8	68
valid_sources[0x77]	131014	1			T3	1432		T4	94		T8	96
valid_sources[0x78]	128703	1			T3	1362		T4	81		T8	143
valid_sources[0x79]	162221	1			T3	1478		T4	77		T8	133
valid_sources[0x7a]	361006	1			T3	1481		T4	82		T8	39
valid_sources[0x7b]	196822	1			T3	1354		T4	65		T8	148
valid_sources[0x7c]	123743	1			T3	1525		T4	105		T8	166
valid_sources[0x7d]	147686	1			T3	1449		T4	91		T8	151
valid_sources[0x7e]	126117	1			T3	1384		T4	90		T8	122
valid_sources[0x7f]	186578	1			T3	1415		T4	80		T8	212
valid_sources[0x80]	126461	1			T3	1420		T4	83		T8	98

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41226

1

T12

450

T13

10

T14

12

values[0x0]

all_enables

biggest_size

57313

1

T3

5

T4

1

T12

592

values[0x1]

all_enables

biggest_size

55965

1

T2

1

T3

4

T4

1