Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15456313

1

T1

819

T2

109474

T3

18578

full_word

121886501

1

T1

8048

T2

24370

T3

185823

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	137342524	1			T1	8867		T2	133844		T3	204401
auto[TlIntgErrCmd]	89	1			T45	3		T46	6		T47	6
auto[TlIntgErrData]	98	1			T45	3		T46	7		T47	1
auto[TlIntgErrBoth]	103	1			T45	4		T46	7		T47	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66214842

1

T1

4424

T2

66560

T3

101973

auto[1]

71127972

1

T1

4443

T2

67284

T3

102428

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7617624	1			T1	404		T2	54521		T3	9286
auto[TlIntgErrNone]	partial	auto[1]	7838419	1			T1	415		T2	54953		T3	9292
auto[TlIntgErrNone]	full_word	auto[0]	58597081	1			T1	4020		T2	12039		T3	92687
auto[TlIntgErrNone]	full_word	auto[1]	63289400	1			T1	4028		T2	12331		T3	93136
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T45	1		T46	2		T47	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T45	2		T46	3		T47	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T46	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T120	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T45	2		T46	3		T91	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T45	1		T46	4		T91	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T47	1		T91	1		T89	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T118	1		T117	1		T121	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T45	1		T46	3		T47	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T45	2		T46	3		T47	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T99	1		T118	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T45	1		T46	1		T59	2