Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	838709	1			T9	8167		T14	7260		T15	24982
auto[1]	11007174	1			T1	271		T2	55909		T3	70153
auto[2]	656538	1			T9	5816		T14	3708		T15	21527
auto[3]	10811120	1			T1	258		T2	56589		T3	70715

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13247996	1			T1	351		T2	3686		T3	117391
auto[1]	2240329	1			T1	83		T2	16812		T3	11199
auto[2]	2269987	1			T1	83		T2	16954		T3	11236
auto[3]	5555229	1			T1	12		T2	75046		T3	1042

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8605846

1

T1

529

T3

140866

T4

4

auto[1]

14707695

1

T2

112498

T3

2

T4

19088

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	320547	1			T14	5949		T5	12		T69	2
auto[0]	auto[0]	auto[1]	33333	1			T9	67		T14	625		T69	54
auto[0]	auto[0]	auto[2]	33498	1			T9	94		T14	627		T5	1
auto[0]	auto[0]	auto[3]	109591	1			T9	8003		T14	58		T69	8679
auto[0]	auto[1]	auto[0]	2637751	1			T1	190		T3	58522		T8	1236
auto[0]	auto[1]	auto[1]	286324	1			T1	61		T3	5246		T4	1
auto[0]	auto[1]	auto[2]	318954	1			T1	15		T3	5888		T8	293
auto[0]	auto[1]	auto[3]	686055	1			T1	5		T3	495		T4	2
auto[0]	auto[2]	auto[0]	248042	1			T9	8		T14	3123		T5	13
auto[0]	auto[2]	auto[1]	33227	1			T9	684		T14	322		T69	690
auto[0]	auto[2]	auto[2]	24064	1			T9	49		T14	241		T69	43
auto[0]	auto[2]	auto[3]	77027	1			T9	5075		T14	22		T69	5891
auto[0]	auto[3]	auto[0]	2549999	1			T1	161		T3	58868		T8	1212
auto[0]	auto[3]	auto[1]	303530	1			T1	22		T3	5953		T8	285
auto[0]	auto[3]	auto[2]	326366	1			T1	68		T3	5347		T8	285
auto[0]	auto[3]	auto[3]	617538	1			T1	7		T3	547		T4	1
auto[1]	auto[0]	auto[0]	11276	1			T14	1		T15	823		T109	621
auto[1]	auto[0]	auto[1]	50694	1			T15	3828		T109	2769		T111	5256
auto[1]	auto[0]	auto[2]	50584	1			T15	3729		T109	2829		T111	5191
auto[1]	auto[0]	auto[3]	229186	1			T9	3		T15	16602		T69	5
auto[1]	auto[1]	auto[0]	3735955	1			T2	1816		T3	1		T4	134
auto[1]	auto[1]	auto[1]	757350	1			T2	8309		T4	1630		T67	4434
auto[1]	auto[1]	auto[2]	730717	1			T2	8443		T3	1		T4	523
auto[1]	auto[1]	auto[3]	1854068	1			T2	37341		T4	7237		T67	465
auto[1]	auto[2]	auto[0]	10352	1			T15	769		T70	1		T109	568
auto[1]	auto[2]	auto[1]	46960	1			T15	3452		T109	2485		T111	4866
auto[1]	auto[2]	auto[2]	39030	1			T15	3107		T109	2279		T111	4284
auto[1]	auto[2]	auto[3]	177836	1			T15	14199		T109	10468		T111	19918
auto[1]	auto[3]	auto[0]	3734074	1			T2	1870		T4	122		T16	3
auto[1]	auto[3]	auto[1]	728911	1			T2	8503		T4	515		T67	5029
auto[1]	auto[3]	auto[2]	746774	1			T2	8511		T4	1641		T67	4421
auto[1]	auto[3]	auto[3]	1803928	1			T2	37705		T4	7286		T9	2