Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	927153946	179322	0	0
ctrl_regwen_rd_A	927153946	6515	0	0
exec_rd_A	927153946	6212	0	0
exec_regwen_rd_A	927153946	6683	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	927153946	179322	0	0
T12	84735	1921	0	0
T13	190921	0	0	0
T14	213149	0	0	0
T16	618421	0	0	0
T17	346905	0	0	0
T18	1017	0	0	0
T27	30705	1352	0	0
T28	0	1795	0	0
T44	122416	0	0	0
T45	0	4	0	0
T48	0	612	0	0
T49	0	531	0	0
T50	0	25	0	0
T51	0	15	0	0
T52	0	278	0	0
T53	0	4	0	0
T56	75689	0	0	0
T57	245790	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	927153946	6515	0	0
T12	84735	398	0	0
T13	190921	0	0	0
T14	213149	0	0	0
T16	618421	0	0	0
T17	346905	0	0	0
T18	1017	0	0	0
T27	30705	0	0	0
T29	0	62	0	0
T44	122416	0	0	0
T47	0	33	0	0
T53	0	3	0	0
T55	0	103	0	0
T56	75689	0	0	0
T57	245790	0	0	0
T64	0	53	0	0
T75	0	15	0	0
T99	0	46	0	0
T103	0	15	0	0
T113	0	4	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	927153946	6212	0	0
T12	84735	277	0	0
T13	190921	0	0	0
T14	213149	0	0	0
T16	618421	0	0	0
T17	346905	0	0	0
T18	1017	0	0	0
T27	30705	0	0	0
T29	0	36	0	0
T44	122416	0	0	0
T47	0	20	0	0
T55	0	107	0	0
T56	75689	0	0	0
T57	245790	0	0	0
T64	0	39	0	0
T75	0	19	0	0
T99	0	58	0	0
T103	0	21	0	0
T113	0	9	0	0
T114	0	56	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	927153946	6683	0	0
T12	84735	350	0	0
T13	190921	0	0	0
T14	213149	0	0	0
T16	618421	0	0	0
T17	346905	0	0	0
T18	1017	0	0	0
T27	30705	0	0	0
T29	0	38	0	0
T44	122416	0	0	0
T47	0	39	0	0
T53	0	3	0	0
T55	0	101	0	0
T56	75689	0	0	0
T57	245790	0	0	0
T64	0	52	0	0
T75	0	5	0	0
T99	0	38	0	0
T103	0	13	0	0
T113	0	6	0	0