Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.57			93.57

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr	90.00			90.00
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr	90.00			90.00
tb.dut.u_prim_count	97.14			97.14

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.47	100.00	89.02	100.00		100.00	58.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=15,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
97.14	97.14

tb.dut.u_prim_count

	Total	Covered	Percent
Totals	7	6	85.71
Total Bits	70	68	97.14
Total Bits 0->1	35	34	97.14
Total Bits 1->0	35	34	97.14

Ports	7	6	85.71
Port Bits	70	68	97.14
Port Bits 0->1	35	34	97.14
Port Bits 1->0	35	34	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[14:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[14:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
90.00	90.00

tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORE	TOGGLE
90.00	90.00

tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	20	18	90.00
Total Bits 0->1	10	9	90.00
Total Bits 1->0	10	9	90.00

Ports	8	7	87.50
Port Bits	20	18	90.00
Port Bits 0->1	10	9	90.00
Port Bits 1->0	10	9	90.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
set_cnt_i[0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
incr_en_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cnt_next_o[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	20	18	90.00
Total Bits 0->1	10	9	90.00
Total Bits 1->0	10	9	90.00

Ports	8	7	87.50
Port Bits	20	18	90.00
Port Bits 0->1	10	9	90.00
Port Bits 1->0	10	9	90.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
set_cnt_i[0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
incr_en_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cnt_next_o[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	20	18	90.00
Total Bits 0->1	10	9	90.00
Total Bits 1->0	10	9	90.00

Ports	8	7	87.50
Port Bits	20	18	90.00
Port Bits 0->1	10	9	90.00
Port Bits 1->0	10	9	90.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
set_cnt_i[0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
incr_en_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cnt_next_o[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_prim_count

	Total	Covered	Percent
Totals	7	6	85.71
Total Bits	70	68	97.14
Total Bits 0->1	35	34	97.14
Total Bits 1->0	35	34	97.14

Ports	7	6	85.71
Port Bits	70	68	97.14
Port Bits 0->1	35	34	97.14
Port Bits 1->0	35	34	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[14:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[14:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	No	No		No		OUTPUT