Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.05	100.00	86.90	100.00		100.00	58.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	89.47	100.00	89.02	100.00		100.00	58.33

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	100.00	89.02	100.00		100.00	58.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.93	99.82	96.10	99.72	100.00	98.85	99.11

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_instr_ctrl.u_prim_lc_sync_hw_debug_en	100.00	100.00				100.00	100.00
gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch	100.00	100.00				100.00	100.00
sram_ctrl_regs_csr_assert	100.00						100.00
tlul_assert_device_ram	100.00	100.00				100.00	100.00
tlul_assert_device_regs	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_prim_alert_sender_parity	100.00			100.00
u_prim_count	97.14			97.14
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_prim_ram_1p_scr	98.40	100.00	92.00	100.00		100.00	100.00
u_prim_sync_reqack_data	100.00	100.00	100.00			100.00	100.00
u_reg_regs	99.05	99.61	98.21	99.51		97.94	100.00
u_tlul_adapter_sram	99.11	99.73	96.61	99.07	100.00	99.22	100.00
u_tlul_data_integ_enc	100.00	100.00
u_tlul_lc_gate	96.85	100.00	100.00		100.00	96.77	87.50

Line Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
TOTAL		48	48	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
ALWAYS	212	3	3	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
ALWAYS	274	11	11	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	487	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
130	1	1
133	1	1
137	1	1
140	1	1
172	1	1
174	1	1
182	1	1
188	1	1
196	1	1
205	1	1
208	1	1
212	1	1
213	1	1
215	1	1
224	1	1
225	1	1
248	1	1
249	1	1
260	1	1
261	1	1
265	1	1
266	1	1
270	1	1
271	1	1
274	1	1
275	1	1
278	1	1
279	1	1
281	1	1
282	1	1
283	1	1
284	1	1
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
318	1	1
356	1	1
358	1	1
360	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
487	1	1

---

Cond Coverage for Module : sram_ctrl

	Total	Covered	Percent
Conditions	84	73	86.90
Logical	84	73	86.90
Non-Logical	0	0
Event	0	0

 LINE       130
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T8,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T15,T16

 LINE       140
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       182
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T5,T6,T7

 LINE       188
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T5,T6,T7
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T5,T6,T7

 LINE       205
 EXPRESSION (reg2hw.ctrl.init.q & reg2hw.ctrl.init.qe)
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       208
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       225
 EXPRESSION ((init_cnt == 15'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       225
 SUB-EXPRESSION (init_cnt == 15'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       248
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T6,T7,T19
1	1	1	Covered	T2,T3,T4

 LINE       249
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T3,T4

 LINE       260
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q & reg2hw.ctrl.renew_scr_key.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T17,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       261
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       265
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       469
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       470
 EXPRESSION (sram_gnt & ((~init_req)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       471
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       472
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       473
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       487
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       487
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       487
 SUB-EXPRESSION (tl_gate_resp_pending & tlul_we)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T21,T22

---

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T12,T14	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T9,T14	Yes	T1,T9,T14	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T9,T12	Yes	T1,T9,T12	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T9,T12	Yes	T1,T9,T12	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T1,T14,T23	Yes	T1,T14,T23	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T8,T15,T16	Yes	T8,T15,T16	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T8,T15,T16	Yes	T8,T15,T16	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T12,T24,T23	Yes	T12,T24,T23	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	208	3	3	100.00
TERNARY	261	3	3	100.00
TERNARY	473	2	2	100.00
TERNARY	474	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	487	3	3	100.00
IF	212	2	2	100.00
IF	274	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	208	(init_done) ? 
-2-:	208	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	261	(key_req) ? 
-2-:	261	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	474	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	(key_req_pending_q) ? 
-2-:	487	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	212	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	274	if ((!rst_ni))
-2-:	282	if (key_ack)
-3-:	289	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T5,T6,T7
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	7	58.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	7	58.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	740162550	740098479	0	0
FpvSecCmCntCheck_A	740162550	0	0	0
FpvSecCmFifoRptrCheck_A	740162550	0	0	0
FpvSecCmFifoWptrCheck_A	740162550	0	0	0
FpvSecCmLcGateFsmCheck_A	740162550	0	0	0
FpvSecCmRegWeOnehotCheck_A	740162550	0	0	0
NonceWidthsLessThanSource_A	635	635	0	0
RamTlOutKnown_A	740162550	740098479	0	0
RamTlOutPayLoadKnown_A	740162550	219300576	0	0
RamTlOutPayLoadKnown_AKnownEnable	740162550	740098479	0	0
RegsTlOutKnown_A	740162550	740098479	0	0
SramOtpKeyKnown_A	740162550	740098479	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635	635	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	219300576	0	0
T1	75349	34531	0	0
T2	689298	327680	0	0
T3	619734	78178	0	0
T4	129098	388802	0	0
T8	1171	0	0	0
T9	349994	52612	0	0
T10	588840	119578	0	0
T11	34869	0	0	0
T12	203467	306986	0	0
T13	456156	303207	0	0
T27	0	6083	0	0
T28	0	17164	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		48	48	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
ALWAYS	212	3	3	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
ALWAYS	274	11	11	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	487	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
130	1	1
133	1	1
137	1	1
140	1	1
172	1	1
174	1	1
182	1	1
188	1	1
196	1	1
205	1	1
208	1	1
212	1	1
213	1	1
215	1	1
224	1	1
225	1	1
248	1	1
249	1	1
260	1	1
261	1	1
265	1	1
266	1	1
270	1	1
271	1	1
274	1	1
275	1	1
278	1	1
279	1	1
281	1	1
282	1	1
283	1	1
284	1	1
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
318	1	1
356	1	1
358	1	1
360	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
487	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	82	73	89.02
Logical	82	73	89.02
Non-Logical	0	0
Event	0	0

 LINE       130
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T8,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T15,T16

 LINE       140
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       182
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T5,T6,T7

 LINE       188
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T5,T6,T7
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T5,T6,T7

 LINE       205
 EXPRESSION (reg2hw.ctrl.init.q & reg2hw.ctrl.init.qe)
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       208
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       225
 EXPRESSION ((init_cnt == 15'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       225
 SUB-EXPRESSION (init_cnt == 15'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       248
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[LOWRISK] we don't issue a new init when there is a unfinished init
1	1	0	Covered	T6,T7,T19
1	1	1	Covered	T2,T3,T4

 LINE       249
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T3,T4

 LINE       260
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q & reg2hw.ctrl.renew_scr_key.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T17,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       261
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       265
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[UNSUPPORTED] ACK can't come without REQ
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       469
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       470
 EXPRESSION (sram_gnt & ((~init_req)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       471
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       472
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       473
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       487
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       487
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       487
 SUB-EXPRESSION (tl_gate_resp_pending & tlul_we)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T21,T22

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T12,T14	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T9,T14	Yes	T1,T9,T14	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T9,T12	Yes	T1,T9,T12	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T9,T12	Yes	T1,T9,T12	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T1,T14,T23	Yes	T1,T14,T23	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T8,T15,T16	Yes	T8,T15,T16	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T8,T15,T16	Yes	T8,T15,T16	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T12,T24,T23	Yes	T12,T24,T23	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T11,T25,T26	Yes	T11,T25,T26	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	208	3	3	100.00
TERNARY	261	3	3	100.00
TERNARY	473	2	2	100.00
TERNARY	474	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	487	3	3	100.00
IF	212	2	2	100.00
IF	274	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	208	(init_done) ? 
-2-:	208	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	261	(key_req) ? 
-2-:	261	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	474	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	(key_req_pending_q) ? 
-2-:	487	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	212	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	274	if ((!rst_ni))
-2-:	282	if (key_ack)
-3-:	289	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T5,T6,T7
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	7	58.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	7	58.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	740162550	740098479	0	0
FpvSecCmCntCheck_A	740162550	0	0	0
FpvSecCmFifoRptrCheck_A	740162550	0	0	0
FpvSecCmFifoWptrCheck_A	740162550	0	0	0
FpvSecCmLcGateFsmCheck_A	740162550	0	0	0
FpvSecCmRegWeOnehotCheck_A	740162550	0	0	0
NonceWidthsLessThanSource_A	635	635	0	0
RamTlOutKnown_A	740162550	740098479	0	0
RamTlOutPayLoadKnown_A	740162550	219300576	0	0
RamTlOutPayLoadKnown_AKnownEnable	740162550	740098479	0	0
RegsTlOutKnown_A	740162550	740098479	0	0
SramOtpKeyKnown_A	740162550	740098479	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635	635	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	219300576	0	0
T1	75349	34531	0	0
T2	689298	327680	0	0
T3	619734	78178	0	0
T4	129098	388802	0	0
T8	1171	0	0	0
T9	349994	52612	0	0
T10	588840	119578	0	0
T11	34869	0	0	0
T12	203467	306986	0	0
T13	456156	303207	0	0
T27	0	6083	0	0
T28	0	17164	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740162550	740098479	0	0
T1	75349	75207	0	0
T2	689298	689217	0	0
T3	619734	619670	0	0
T4	129098	129089	0	0
T8	1171	1118	0	0
T9	349994	349916	0	0
T10	588840	588785	0	0
T11	34869	34810	0	0
T12	203467	203462	0	0
T13	456156	456092	0	0