Unified Coverage Report :: Module :: sram_ctrl_regs_reg_top

Module : sram_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.43	100.00	97.70			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	99.43	100.00	97.70			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.43	100.00	97.70			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	99.61	98.21	99.51		97.94	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.47	100.00	89.02	100.00		100.00	58.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl0_qe	100.00	100.00				100.00
u_ctrl_init	100.00	100.00	100.00			100.00
u_ctrl_regwen	100.00	100.00	100.00			100.00
u_ctrl_renew_scr_key	100.00	100.00	100.00			100.00
u_exec	100.00	100.00	100.00			100.00
u_exec_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	94.44	100.00		88.89
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00	100.00			100.00
u_status_escalated	100.00	100.00	100.00			100.00
u_status_init_done	100.00	100.00	100.00			100.00
u_status_init_error	65.83	87.50	50.00			60.00
u_status_scr_key_seed_valid	100.00	100.00	100.00			100.00
u_status_scr_key_valid	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		58	58	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
ALWAYS	495	7	7	100.00
CONT_ASSIGN	504	1	1	100.00
ALWAYS	508	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
ALWAYS	538	7	7	100.00
ALWAYS	549	14	14	100.00
CONT_ASSIGN	592	0	0
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
152	1	1
166	1	1
364	1	1
434	1	1
461	1	1
489	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
504	1	1
508	1	1
518	1	1
520	1	1
521	1	1
523	1	1
524	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534	1	1
538	1	1
539	1	1
540	1	1
541	1	1
542	1	1
543	1	1
544	1	1
549	1	1
550	1	1
552	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
565	1	1
569	1	1
573	1	1
577	1	1
578	1	1
592		unreachable
600	1	1
601	1	1

---

Cond Coverage for Module : sram_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	87	85	97.70
Logical	87	85	97.70
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T14,T23
1	1	Covered	T1,T2,T3

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T34,T35,T36

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T34,T35,T36
1	0	0	Covered	T34,T35,T36

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T35,T36
0	1	0	Covered	T1,T14,T23
1	0	0	Covered	T1,T14,T23

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T14,T23

 LINE       364
 EXPRESSION (exec_we & exec_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T17,T18
1	1	Covered	T12,T24,T17

 LINE       434
 EXPRESSION (ctrl_we & ctrl_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T18,T20
1	1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       497
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       498
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T12

 LINE       499
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T12

 LINE       500
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T12

 LINE       501
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       504
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       504
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       508
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T14,T23

 LINE       508
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T1,T9,T12
0	0	0	0	1	0	Covered	T1,T9,T14
0	0	0	1	0	0	Covered	T1,T9,T14
0	0	1	0	0	0	Covered	T1,T9,T14
0	1	0	0	0	0	Covered	T1,T9,T14
1	0	0	0	0	0	Covered	T1,T9,T14

 LINE       508
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T9,T14

 LINE       508
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T14

 LINE       508
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T9,T12
1	1	Covered	T1,T9,T14

 LINE       508
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T9,T12
1	1	Covered	T1,T9,T14

 LINE       508
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T9,T12
1	1	Covered	T1,T9,T14

 LINE       508
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T12

 LINE       518
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T8,T9
1	1	0	Covered	T1,T14,T23
1	1	1	Covered	T8,T15,T16

 LINE       521
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T9,T12
1	1	0	Covered	T1,T14,T32
1	1	1	Covered	T12,T17,T18

 LINE       524
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T9,T12
1	1	0	Covered	T1,T14,T23
1	1	1	Covered	T12,T24,T17

 LINE       527
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T9,T12
1	1	0	Covered	T1,T14,T23
1	1	1	Covered	T12,T18,T20

 LINE       530
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T12,T15
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T14,T23
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	504	2	2	100.00
IF	71	3	3	100.00
CASE	550	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	504	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	752495593	32697031	0	0
reAfterRv	752495593	32696976	0	0
rePulse	752495593	32677980	0	0
wePulse	752495593	18996	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	32697031	0	0
T1	75349	4190	0	0
T2	689298	16430	0	0
T3	619734	15590	0	0
T4	129098	43167	0	0
T8	1171	7	0	0
T9	349994	131197	0	0
T10	588840	197417	0	0
T11	34869	3188	0	0
T12	203467	14247	0	0
T13	456156	50046	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	32696976	0	0
T1	75349	4189	0	0
T2	689298	16430	0	0
T3	619734	15590	0	0
T4	129098	43167	0	0
T8	1171	7	0	0
T9	349994	131197	0	0
T10	588840	197417	0	0
T11	34869	3188	0	0
T12	203467	14247	0	0
T13	456156	50046	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	32677980	0	0
T1	75349	4143	0	0
T2	689298	16425	0	0
T3	619734	15585	0	0
T4	129098	43158	0	0
T8	1171	0	0	0
T9	349994	131187	0	0
T10	588840	197394	0	0
T11	34869	3187	0	0
T12	203467	14133	0	0
T13	456156	50043	0	0
T27	0	16402	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	18996	0	0
T1	75349	46	0	0
T2	689298	5	0	0
T3	619734	5	0	0
T4	129098	9	0	0
T8	1171	7	0	0
T9	349994	10	0	0
T10	588840	23	0	0
T11	34869	1	0	0
T12	203467	114	0	0
T13	456156	3	0	0