Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.47	100.00	89.02	100.00		100.00	58.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	752495593	132796	0	0
ctrl_regwen_rd_A	752495593	6812	0	0
exec_rd_A	752495593	6560	0	0
exec_regwen_rd_A	752495593	6952	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	132796	0	0
T1	75349	1755	0	0
T2	689298	0	0	0
T3	619734	0	0	0
T4	129098	0	0	0
T8	1171	0	0	0
T9	349994	0	0	0
T10	588840	0	0	0
T11	34869	0	0	0
T12	203467	0	0	0
T13	456156	0	0	0
T14	0	1821	0	0
T23	0	717	0	0
T32	0	5964	0	0
T37	0	858	0	0
T38	0	2922	0	0
T39	0	1520	0	0
T40	0	3241	0	0
T41	0	11606	0	0
T42	0	3402	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	6812	0	0
T1	75349	458	0	0
T2	689298	0	0	0
T3	619734	0	0	0
T4	129098	0	0	0
T8	1171	0	0	0
T9	349994	0	0	0
T10	588840	0	0	0
T11	34869	0	0	0
T12	203467	0	0	0
T13	456156	0	0	0
T14	0	515	0	0
T32	0	903	0	0
T37	0	163	0	0
T47	0	27	0	0
T93	0	26	0	0
T94	0	14	0	0
T101	0	245	0	0
T102	0	327	0	0
T103	0	38	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	6560	0	0
T1	75349	373	0	0
T2	689298	0	0	0
T3	619734	0	0	0
T4	129098	0	0	0
T8	1171	0	0	0
T9	349994	0	0	0
T10	588840	0	0	0
T11	34869	0	0	0
T12	203467	0	0	0
T13	456156	0	0	0
T14	0	456	0	0
T32	0	1007	0	0
T37	0	186	0	0
T47	0	33	0	0
T93	0	71	0	0
T94	0	4	0	0
T101	0	235	0	0
T102	0	290	0	0
T103	0	65	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752495593	6952	0	0
T1	75349	448	0	0
T2	689298	0	0	0
T3	619734	0	0	0
T4	129098	0	0	0
T8	1171	0	0	0
T9	349994	0	0	0
T10	588840	0	0	0
T11	34869	0	0	0
T12	203467	0	0	0
T13	456156	0	0	0
T14	0	398	0	0
T32	0	1080	0	0
T37	0	280	0	0
T47	0	28	0	0
T93	0	102	0	0
T94	0	9	0	0
T101	0	276	0	0
T102	0	343	0	0
T103	0	60	0	0