Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14694460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

129492647

1

T1

2037

T2

148717

T3

602

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	70786974	1			T1	1203		T2	82401		T3	334
values[0x0]	35234306	1			T1	552		T2	39189		T3	160
values[0x1]	38165827	1			T1	706		T2	42258		T3	170

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7494763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136692344

1

T1

2233

T2

156286

T3

633

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	483096	1			T1	4		T2	678		T3	2
valid_sources[0x01]	511914	1			T1	4		T2	662		T3	8
valid_sources[0x02]	492322	1			T1	10		T2	693		T3	7
valid_sources[0x03]	484148	1			T1	12		T2	703		T4	243
valid_sources[0x04]	489900	1			T1	7		T2	611		T4	404
valid_sources[0x05]	496385	1			T2	635		T3	4		T4	263
valid_sources[0x06]	497355	1			T2	601		T3	2		T4	265
valid_sources[0x07]	520221	1			T1	10		T2	593		T3	1
valid_sources[0x08]	485181	1			T2	679		T3	4		T4	307
valid_sources[0x09]	490270	1			T1	16		T2	704		T4	390
valid_sources[0x0a]	503425	1			T1	8		T2	593		T4	256
valid_sources[0x0b]	488705	1			T1	14		T2	629		T3	3
valid_sources[0x0c]	499826	1			T1	17		T2	646		T4	344
valid_sources[0x0d]	487504	1			T2	646		T3	3		T4	314
valid_sources[0x0e]	567894	1			T1	6		T2	584		T4	417
valid_sources[0x0f]	500558	1			T1	17		T2	586		T3	6
valid_sources[0x10]	486159	1			T1	48		T2	683		T3	3
valid_sources[0x11]	580735	1			T1	17		T2	610		T3	2
valid_sources[0x12]	489103	1			T2	640		T3	2		T4	385
valid_sources[0x13]	499199	1			T1	11		T2	616		T4	373
valid_sources[0x14]	2058291	1			T1	8		T2	670		T3	4
valid_sources[0x15]	577787	1			T1	15		T2	651		T3	1
valid_sources[0x16]	491348	1			T2	615		T3	8		T4	262
valid_sources[0x17]	500148	1			T1	7		T2	581		T3	7
valid_sources[0x18]	515633	1			T2	670		T3	7		T4	237
valid_sources[0x19]	512838	1			T1	28		T2	699		T3	1
valid_sources[0x1a]	516768	1			T1	20		T2	581		T3	2
valid_sources[0x1b]	486211	1			T2	617		T3	1		T4	238
valid_sources[0x1c]	486566	1			T1	31		T2	613		T3	2
valid_sources[0x1d]	534994	1			T1	9		T2	711		T3	1
valid_sources[0x1e]	487192	1			T1	23		T2	561		T3	7
valid_sources[0x1f]	523367	1			T1	33		T2	738		T3	3
valid_sources[0x20]	482826	1			T2	591		T3	5		T4	276
valid_sources[0x21]	513648	1			T2	659		T3	1		T4	294
valid_sources[0x22]	488214	1			T1	19		T2	633		T3	1
valid_sources[0x23]	526307	1			T1	48		T2	608		T3	2
valid_sources[0x24]	486610	1			T2	619		T3	2		T4	229
valid_sources[0x25]	500731	1			T1	17		T2	746		T3	3
valid_sources[0x26]	486767	1			T2	596		T3	12		T4	321
valid_sources[0x27]	486815	1			T1	4		T2	587		T4	411
valid_sources[0x28]	507823	1			T2	708		T3	3		T4	320
valid_sources[0x29]	488020	1			T2	642		T4	294		T8	28
valid_sources[0x2a]	499354	1			T1	2		T2	579		T3	2
valid_sources[0x2b]	496294	1			T1	22		T2	719		T3	2
valid_sources[0x2c]	484814	1			T1	9		T2	704		T3	5
valid_sources[0x2d]	1937506	1			T2	663		T3	4		T4	323
valid_sources[0x2e]	515231	1			T2	648		T4	289		T8	50
valid_sources[0x2f]	498702	1			T1	6		T2	654		T3	1
valid_sources[0x30]	481672	1			T1	21		T2	634		T3	7
valid_sources[0x31]	482749	1			T1	2		T2	590		T4	266
valid_sources[0x32]	498633	1			T1	37		T2	596		T3	2
valid_sources[0x33]	509850	1			T1	24		T2	590		T3	1
valid_sources[0x34]	491656	1			T1	4		T2	595		T3	4
valid_sources[0x35]	531961	1			T1	32		T2	644		T4	245
valid_sources[0x36]	491006	1			T1	2		T2	710		T3	5
valid_sources[0x37]	503389	1			T1	1		T2	572		T3	2
valid_sources[0x38]	490525	1			T1	39		T2	594		T4	290
valid_sources[0x39]	481184	1			T1	20		T2	700		T3	1
valid_sources[0x3a]	486677	1			T2	658		T3	5		T4	259
valid_sources[0x3b]	1141731	1			T1	7		T2	669		T3	1
valid_sources[0x3c]	487931	1			T2	563		T3	2		T4	282
valid_sources[0x3d]	499697	1			T1	5		T2	760		T3	1
valid_sources[0x3e]	479019	1			T2	614		T4	258		T8	28
valid_sources[0x3f]	544188	1			T1	2		T2	645		T3	6
valid_sources[0x40]	503737	1			T2	628		T4	227		T8	35
valid_sources[0x41]	519279	1			T1	6		T2	597		T4	251
valid_sources[0x42]	489694	1			T2	572		T3	4		T4	316
valid_sources[0x43]	704062	1			T2	646		T4	300		T8	31
valid_sources[0x44]	495994	1			T1	16		T2	561		T3	1
valid_sources[0x45]	483656	1			T1	5		T2	614		T3	1
valid_sources[0x46]	491782	1			T1	32		T2	699		T3	9
valid_sources[0x47]	482128	1			T1	5		T2	616		T4	272
valid_sources[0x48]	505789	1			T1	10		T2	708		T3	2
valid_sources[0x49]	554764	1			T1	3		T2	650		T4	215
valid_sources[0x4a]	492184	1			T1	19		T2	644		T3	4
valid_sources[0x4b]	503700	1			T2	666		T3	1		T4	256
valid_sources[0x4c]	484640	1			T1	22		T2	620		T3	3
valid_sources[0x4d]	517854	1			T2	601		T4	231		T8	37
valid_sources[0x4e]	536514	1			T1	22		T2	579		T3	2
valid_sources[0x4f]	957864	1			T2	698		T3	1		T4	294
valid_sources[0x50]	536391	1			T2	654		T4	1110		T8	44
valid_sources[0x51]	495579	1			T2	630		T3	2		T4	324
valid_sources[0x52]	1641700	1			T2	677		T3	1		T4	282
valid_sources[0x53]	524331	1			T1	34		T2	563		T3	4
valid_sources[0x54]	523354	1			T1	6		T2	658		T3	1
valid_sources[0x55]	492111	1			T1	2		T2	606		T4	332
valid_sources[0x56]	481307	1			T2	647		T3	5		T4	322
valid_sources[0x57]	508392	1			T2	621		T4	231		T8	34
valid_sources[0x58]	740375	1			T2	678		T3	4		T4	295
valid_sources[0x59]	503656	1			T1	18		T2	705		T3	8
valid_sources[0x5a]	819127	1			T1	7		T2	644		T3	4
valid_sources[0x5b]	527794	1			T1	3		T2	669		T3	3
valid_sources[0x5c]	2169872	1			T1	3		T2	706		T3	3
valid_sources[0x5d]	516121	1			T1	3		T2	631		T3	1
valid_sources[0x5e]	522675	1			T2	550		T3	4		T4	222
valid_sources[0x5f]	481209	1			T1	21		T2	672		T3	2
valid_sources[0x60]	480646	1			T2	660		T3	4		T4	225
valid_sources[0x61]	485439	1			T2	656		T3	1		T4	399
valid_sources[0x62]	483741	1			T2	678		T4	327		T8	43
valid_sources[0x63]	489788	1			T1	29		T2	589		T4	351
valid_sources[0x64]	540503	1			T1	16		T2	636		T3	3
valid_sources[0x65]	523482	1			T1	12		T2	687		T3	3
valid_sources[0x66]	503059	1			T1	10		T2	567		T4	299
valid_sources[0x67]	508490	1			T1	9		T2	661		T4	397
valid_sources[0x68]	544694	1			T1	2		T2	599		T4	288
valid_sources[0x69]	559517	1			T1	55		T2	691		T4	192
valid_sources[0x6a]	490928	1			T1	3		T2	571		T3	3
valid_sources[0x6b]	486102	1			T1	2		T2	698		T3	2
valid_sources[0x6c]	484135	1			T1	17		T2	603		T4	257
valid_sources[0x6d]	508564	1			T1	1		T2	636		T3	7
valid_sources[0x6e]	491754	1			T1	6		T2	658		T3	3
valid_sources[0x6f]	569133	1			T1	8		T2	624		T4	294
valid_sources[0x70]	501448	1			T1	7		T2	540		T3	1
valid_sources[0x71]	494603	1			T1	35		T2	571		T3	2
valid_sources[0x72]	491789	1			T2	741		T3	7		T4	308
valid_sources[0x73]	504992	1			T2	600		T3	1		T4	284
valid_sources[0x74]	594307	1			T1	2		T2	610		T3	3
valid_sources[0x75]	491689	1			T1	34		T2	654		T3	3
valid_sources[0x76]	492324	1			T1	42		T2	601		T3	3
valid_sources[0x77]	500020	1			T1	11		T2	649		T3	1
valid_sources[0x78]	595494	1			T1	26		T2	671		T3	1
valid_sources[0x79]	508254	1			T1	3		T2	658		T4	242
valid_sources[0x7a]	488635	1			T2	623		T3	3		T4	246
valid_sources[0x7b]	486499	1			T1	5		T2	603		T3	6
valid_sources[0x7c]	498509	1			T2	553		T3	6		T4	250
valid_sources[0x7d]	481607	1			T2	691		T4	253		T8	35
valid_sources[0x7e]	504283	1			T2	682		T3	2		T4	253
valid_sources[0x7f]	496141	1			T1	12		T2	651		T3	7
valid_sources[0x80]	500716	1			T1	25		T2	579		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63398633

1

T1

1002

T2

74810

T3

305

values[0x0]

all_enables

biggest_size

33042278

1

T1

475

T2

36975

T3

148

values[0x1]

all_enables

biggest_size

33051736

1

T1

560

T2

36932

T3

149

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45100727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

161552

1

T2

1

T3

6

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	45125768	1			T1	33569		T2	237829		T3	82020
values[0x0]	66165	1			T1	1		T2	17		T3	4
values[0x1]	70346	1			T1	1		T2	11		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30070977	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15191302

1

T1

11282

T2

79457

T3

27558

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	263567	1			T3	294		T4	136		T8	137
valid_sources[0x01]	128338	1			T3	302		T4	109		T8	154
valid_sources[0x02]	129260	1			T3	356		T4	131		T8	134
valid_sources[0x03]	138260	1			T3	335		T4	94		T8	139
valid_sources[0x04]	186399	1			T3	306		T4	111		T8	104
valid_sources[0x05]	224428	1			T3	348		T4	123		T8	187
valid_sources[0x06]	263292	1			T1	33571		T3	352		T4	109
valid_sources[0x07]	202815	1			T3	305		T4	150		T8	138
valid_sources[0x08]	128236	1			T3	326		T4	127		T8	120
valid_sources[0x09]	182059	1			T3	353		T4	135		T8	143
valid_sources[0x0a]	485812	1			T3	341		T4	114		T8	117
valid_sources[0x0b]	172823	1			T3	337		T4	125		T8	149
valid_sources[0x0c]	140630	1			T3	296		T4	118		T8	105
valid_sources[0x0d]	145318	1			T3	322		T4	125		T8	127
valid_sources[0x0e]	135131	1			T3	368		T4	162		T8	147
valid_sources[0x0f]	164590	1			T3	316		T4	115		T8	92
valid_sources[0x10]	166816	1			T3	305		T4	99		T8	149
valid_sources[0x11]	177078	1			T3	329		T4	146		T8	136
valid_sources[0x12]	129653	1			T3	331		T4	96		T8	146
valid_sources[0x13]	136229	1			T3	295		T4	85		T8	151
valid_sources[0x14]	194446	1			T3	334		T4	119		T8	151
valid_sources[0x15]	131875	1			T3	342		T4	135		T8	120
valid_sources[0x16]	140525	1			T3	319		T4	97		T8	103
valid_sources[0x17]	219219	1			T3	323		T4	155		T8	104
valid_sources[0x18]	131587	1			T3	294		T4	111		T8	168
valid_sources[0x19]	146045	1			T3	294		T4	117		T8	194
valid_sources[0x1a]	162755	1			T3	295		T4	114		T8	118
valid_sources[0x1b]	185954	1			T3	317		T4	104		T8	157
valid_sources[0x1c]	138632	1			T3	337		T4	112		T8	128
valid_sources[0x1d]	147347	1			T3	327		T4	98		T8	173
valid_sources[0x1e]	172262	1			T3	322		T4	153		T8	112
valid_sources[0x1f]	137032	1			T3	339		T4	146		T8	123
valid_sources[0x20]	130120	1			T3	295		T4	119		T8	112
valid_sources[0x21]	223889	1			T3	339		T4	140		T8	93
valid_sources[0x22]	164425	1			T3	348		T4	106		T8	135
valid_sources[0x23]	147820	1			T3	330		T4	106		T8	128
valid_sources[0x24]	213072	1			T3	295		T4	114		T8	134
valid_sources[0x25]	133128	1			T3	331		T4	145		T8	123
valid_sources[0x26]	244717	1			T3	299		T4	130		T8	161
valid_sources[0x27]	136891	1			T3	356		T4	136		T8	117
valid_sources[0x28]	477007	1			T3	338		T4	98		T8	120
valid_sources[0x29]	147226	1			T3	340		T4	147		T8	142
valid_sources[0x2a]	147439	1			T3	310		T4	117		T8	132
valid_sources[0x2b]	146297	1			T3	297		T4	138		T8	123
valid_sources[0x2c]	148229	1			T3	358		T4	150		T8	128
valid_sources[0x2d]	136457	1			T3	278		T4	156		T8	133
valid_sources[0x2e]	138600	1			T3	332		T4	120		T8	137
valid_sources[0x2f]	134285	1			T3	330		T4	108		T8	111
valid_sources[0x30]	147419	1			T3	335		T4	143		T8	106
valid_sources[0x31]	128690	1			T3	340		T4	140		T8	145
valid_sources[0x32]	163244	1			T3	341		T4	88		T8	130
valid_sources[0x33]	616925	1			T3	311		T4	131		T8	107
valid_sources[0x34]	131287	1			T3	293		T4	81		T8	158
valid_sources[0x35]	211388	1			T3	300		T4	112		T8	140
valid_sources[0x36]	128965	1			T3	317		T4	133		T8	145
valid_sources[0x37]	136306	1			T3	334		T4	116		T8	138
valid_sources[0x38]	130750	1			T3	311		T4	126		T8	123
valid_sources[0x39]	131010	1			T3	343		T4	107		T8	120
valid_sources[0x3a]	130154	1			T3	322		T4	146		T8	137
valid_sources[0x3b]	297205	1			T3	319		T4	107		T8	126
valid_sources[0x3c]	133209	1			T3	341		T4	97		T8	132
valid_sources[0x3d]	133776	1			T3	326		T4	124		T8	118
valid_sources[0x3e]	233248	1			T3	310		T4	111		T8	128
valid_sources[0x3f]	129606	1			T3	339		T4	161		T8	134
valid_sources[0x40]	250214	1			T3	332		T4	111		T8	113
valid_sources[0x41]	134860	1			T3	321		T4	131		T8	134
valid_sources[0x42]	132761	1			T3	327		T4	94		T8	131
valid_sources[0x43]	661593	1			T3	328		T4	181		T8	135
valid_sources[0x44]	130723	1			T3	373		T4	102		T8	149
valid_sources[0x45]	128056	1			T3	337		T4	111		T8	121
valid_sources[0x46]	130683	1			T3	287		T4	112		T8	117
valid_sources[0x47]	161283	1			T3	319		T4	122		T8	146
valid_sources[0x48]	129923	1			T3	356		T4	127		T8	121
valid_sources[0x49]	132894	1			T3	286		T4	110		T8	145
valid_sources[0x4a]	134372	1			T3	348		T4	111		T8	128
valid_sources[0x4b]	169785	1			T3	322		T4	113		T8	113
valid_sources[0x4c]	162841	1			T3	314		T4	110		T8	149
valid_sources[0x4d]	128809	1			T3	342		T4	105		T8	127
valid_sources[0x4e]	162644	1			T3	326		T4	126		T8	122
valid_sources[0x4f]	134309	1			T3	278		T4	102		T8	136
valid_sources[0x50]	130616	1			T3	302		T4	124		T8	143
valid_sources[0x51]	130446	1			T3	328		T4	149		T8	132
valid_sources[0x52]	146667	1			T3	341		T4	119		T8	147
valid_sources[0x53]	131068	1			T3	337		T4	128		T8	151
valid_sources[0x54]	129780	1			T3	320		T4	128		T8	116
valid_sources[0x55]	330581	1			T3	326		T4	89		T8	138
valid_sources[0x56]	130324	1			T3	307		T4	120		T8	124
valid_sources[0x57]	129898	1			T3	335		T4	128		T8	136
valid_sources[0x58]	449980	1			T3	326		T4	123		T8	91
valid_sources[0x59]	128104	1			T3	318		T4	120		T8	195
valid_sources[0x5a]	130286	1			T3	298		T4	125		T8	108
valid_sources[0x5b]	127129	1			T3	338		T4	128		T8	126
valid_sources[0x5c]	128801	1			T3	327		T4	136		T8	139
valid_sources[0x5d]	218220	1			T3	322		T4	114		T8	125
valid_sources[0x5e]	245755	1			T3	323		T4	129		T8	146
valid_sources[0x5f]	229903	1			T3	331		T4	105		T8	145
valid_sources[0x60]	131445	1			T3	335		T4	108		T8	147
valid_sources[0x61]	160493	1			T3	327		T4	96		T8	121
valid_sources[0x62]	128635	1			T3	318		T4	136		T8	139
valid_sources[0x63]	235555	1			T3	315		T4	110		T8	135
valid_sources[0x64]	162761	1			T3	355		T4	110		T8	129
valid_sources[0x65]	140931	1			T3	321		T4	119		T8	140
valid_sources[0x66]	218081	1			T3	313		T4	133		T8	136
valid_sources[0x67]	131025	1			T3	380		T4	124		T8	186
valid_sources[0x68]	130939	1			T3	302		T4	107		T8	132
valid_sources[0x69]	130274	1			T3	305		T4	143		T8	124
valid_sources[0x6a]	147327	1			T3	299		T4	143		T8	125
valid_sources[0x6b]	131578	1			T3	341		T4	120		T8	132
valid_sources[0x6c]	157292	1			T3	297		T4	121		T8	143
valid_sources[0x6d]	195539	1			T3	354		T4	157		T8	128
valid_sources[0x6e]	147414	1			T3	324		T4	146		T8	130
valid_sources[0x6f]	131975	1			T3	327		T4	105		T8	122
valid_sources[0x70]	151392	1			T3	312		T4	129		T8	147
valid_sources[0x71]	131600	1			T3	312		T4	121		T8	125
valid_sources[0x72]	160344	1			T3	321		T4	104		T8	99
valid_sources[0x73]	144977	1			T3	339		T4	141		T8	122
valid_sources[0x74]	134930	1			T3	318		T4	150		T8	149
valid_sources[0x75]	139974	1			T3	296		T4	97		T8	169
valid_sources[0x76]	170475	1			T3	324		T4	121		T8	146
valid_sources[0x77]	136397	1			T3	319		T4	96		T8	162
valid_sources[0x78]	131145	1			T3	310		T4	125		T8	155
valid_sources[0x79]	129250	1			T3	329		T4	119		T8	106
valid_sources[0x7a]	162375	1			T3	274		T4	122		T8	145
valid_sources[0x7b]	398733	1			T3	316		T4	138		T8	168
valid_sources[0x7c]	146295	1			T3	320		T4	142		T8	166
valid_sources[0x7d]	389474	1			T3	325		T4	104		T8	154
valid_sources[0x7e]	185400	1			T3	305		T4	130		T8	114
valid_sources[0x7f]	130435	1			T3	358		T4	129		T8	146
valid_sources[0x80]	132862	1			T3	332		T4	118		T8	88

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42841

1

T3

3

T6

9

T7

12

values[0x0]

all_enables

biggest_size

59998

1

T3

2

T4

1

T10

1

values[0x1]

all_enables

biggest_size

58713

1

T2

1

T3

1

T10

1