Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14756606

1

T1

424

T2

15131

T3

19

full_word

127654869

1

T1

2037

T2

148717

T3

205

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	142411145	1			T1	2461		T2	163848		T3	224
auto[TlIntgErrCmd]	106	1			T31	8		T50	2		T58	2
auto[TlIntgErrData]	109	1			T31	5		T50	3		T58	4
auto[TlIntgErrBoth]	115	1			T31	7		T50	5		T58	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68861202

1

T1

1203

T2

82401

T3

115

auto[1]

73550273

1

T1

1258

T2

81447

T3

109

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7258778	1			T1	201		T2	7591		T3	11
auto[TlIntgErrNone]	partial	auto[1]	7497530	1			T1	223		T2	7540		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	61602260	1			T1	1002		T2	74810		T3	104
auto[TlIntgErrNone]	full_word	auto[1]	66052577	1			T1	1035		T2	73907		T3	101
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T31	2		T58	1		T69	5
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T31	5		T50	2		T58	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T31	1		T113	1		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T69	1		T117	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T31	1		T50	2		T58	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T31	4		T58	2		T69	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T50	1		T58	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T112	1		T113	2		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T31	4		T58	3		T69	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T31	2		T50	5		T69	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T118	1		T119	1		T116	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T31	1		T58	1		T113	1