Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	743451	1			T4	10458		T7	9		T13	2106
auto[1]	9840962	1			T1	1203		T2	22817		T3	108
auto[2]	579567	1			T4	9748		T6	2		T7	9
auto[3]	9692678	1			T1	1257		T2	22374		T3	98

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13114993	1			T1	1696		T2	37659		T3	179
auto[1]	1905876	1			T1	340		T2	3549		T3	9
auto[2]	1929687	1			T1	349		T2	3621		T3	16
auto[3]	3906102	1			T1	75		T2	362		T3	2

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8633161

1

T1

2459

T2

45191

T3

206

auto[1]

12223497

1

T1

1

T4

1

T48

16509

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	316468	1			T4	8587		T7	8		T18	2459
auto[0]	auto[0]	auto[1]	33084	1			T4	877		T7	1		T13	25
auto[0]	auto[0]	auto[2]	32699	1			T4	906		T13	21		T18	254
auto[0]	auto[0]	auto[3]	81236	1			T4	87		T13	2060		T18	27
auto[0]	auto[1]	auto[0]	2804133	1			T1	843		T2	19036		T3	94
auto[0]	auto[1]	auto[1]	303393	1			T1	159		T2	1655		T3	4
auto[0]	auto[1]	auto[2]	322553	1			T1	168		T2	1925		T3	10
auto[0]	auto[1]	auto[3]	528268	1			T1	33		T2	201		T4	82
auto[0]	auto[2]	auto[0]	240970	1			T4	8066		T6	1		T7	7
auto[0]	auto[2]	auto[1]	30139	1			T4	858		T6	1		T7	1
auto[0]	auto[2]	auto[2]	22454	1			T4	760		T7	1		T13	26
auto[0]	auto[2]	auto[3]	61080	1			T4	64		T13	1942		T18	5
auto[0]	auto[3]	auto[0]	2731965	1			T1	852		T2	18623		T3	85
auto[0]	auto[3]	auto[1]	310948	1			T1	181		T2	1894		T3	5
auto[0]	auto[3]	auto[2]	331176	1			T1	181		T2	1696		T3	6
auto[0]	auto[3]	auto[3]	482595	1			T1	42		T2	161		T3	2
auto[1]	auto[0]	auto[0]	9241	1			T4	1		T102	177		T128	545
auto[1]	auto[0]	auto[1]	41967	1			T102	834		T128	2397		T130	3368
auto[1]	auto[0]	auto[2]	41536	1			T102	839		T128	2377		T130	3329
auto[1]	auto[0]	auto[3]	187220	1			T102	3817		T128	10588		T131	1
auto[1]	auto[1]	auto[0]	3501967	1			T48	89		T19	1		T49	71749
auto[1]	auto[1]	auto[1]	591979	1			T48	1398		T49	7127		T98	3214
auto[1]	auto[1]	auto[2]	562361	1			T48	505		T49	7088		T98	1070
auto[1]	auto[1]	auto[3]	1226308	1			T48	6280		T49	712		T98	14138
auto[1]	auto[2]	auto[0]	8025	1			T102	108		T128	488		T130	672
auto[1]	auto[2]	auto[1]	35426	1			T102	503		T128	2184		T130	2985
auto[1]	auto[2]	auto[2]	32911	1			T102	918		T128	1645		T130	2221
auto[1]	auto[2]	auto[3]	148562	1			T102	4210		T128	7156		T132	1
auto[1]	auto[3]	auto[0]	3502224	1			T1	1		T48	120		T49	71495
auto[1]	auto[3]	auto[1]	558940	1			T48	517		T49	7136		T98	1054
auto[1]	auto[3]	auto[2]	583997	1			T48	1351		T49	7102		T98	3158
auto[1]	auto[3]	auto[3]	1190833	1			T48	6249		T49	733		T98	14271