Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	981017923	178963	0	0
ctrl_regwen_rd_A	981017923	6589	0	0
exec_rd_A	981017923	6288	0	0
exec_regwen_rd_A	981017923	6494	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981017923	178963	0	0
T31	12462	7	0	0
T32	33952	8	0	0
T33	35852	147	0	0
T34	5292	259	0	0
T50	0	3	0	0
T53	0	334	0	0
T54	0	35	0	0
T55	0	5	0	0
T56	0	301	0	0
T57	0	29	0	0
T62	3340	0	0	0
T63	705934	0	0	0
T64	5410	0	0	0
T65	1366	0	0	0
T66	1036	0	0	0
T67	1350	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981017923	6589	0	0
T32	33952	8	0	0
T33	35852	0	0	0
T34	5292	15	0	0
T50	0	39	0	0
T53	0	15	0	0
T56	0	20	0	0
T62	3340	0	0	0
T63	705934	0	0	0
T64	5410	0	0	0
T65	1366	70	0	0
T66	1036	0	0	0
T67	1350	17	0	0
T73	719759	43	0	0
T76	0	66	0	0
T81	0	75	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981017923	6288	0	0
T32	33952	1	0	0
T33	35852	0	0	0
T34	5292	43	0	0
T50	0	32	0	0
T53	0	5	0	0
T56	0	21	0	0
T62	3340	0	0	0
T63	705934	0	0	0
T64	5410	0	0	0
T65	1366	37	0	0
T66	1036	0	0	0
T67	1350	20	0	0
T73	719759	45	0	0
T76	0	80	0	0
T81	0	77	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981017923	6494	0	0
T32	33952	10	0	0
T33	35852	0	0	0
T34	5292	14	0	0
T50	0	29	0	0
T56	0	34	0	0
T58	0	56	0	0
T62	3340	0	0	0
T63	705934	0	0	0
T64	5410	0	0	0
T65	1366	11	0	0
T66	1036	0	0	0
T67	1350	27	0	0
T73	719759	32	0	0
T76	0	83	0	0
T81	0	92	0	0