Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15025936	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

134442182

1

T1

9119

T2

589824

T3

8514

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73346929	1			T1	4959		T2	294912		T3	4231
values[0x0]	36561841	1			T1	2422		T2	147037		T3	2165
values[0x1]	39559348	1			T1	2655		T2	147875		T3	2118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7663970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141804148

1

T1

9575

T2

589824

T3

8514

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	496682	1			T1	24		T3	30		T6	38
valid_sources[0x01]	566926	1			T1	46		T3	35		T6	42
valid_sources[0x02]	711058	1			T1	22		T3	37		T6	31
valid_sources[0x03]	490656	1			T1	19		T3	34		T6	40
valid_sources[0x04]	516107	1			T1	30		T3	33		T6	35
valid_sources[0x05]	613676	1			T1	24		T3	35		T6	35
valid_sources[0x06]	592162	1			T1	48		T3	31		T6	46
valid_sources[0x07]	512298	1			T1	23		T3	41		T6	33
valid_sources[0x08]	496393	1			T1	50		T3	36		T6	32
valid_sources[0x09]	520913	1			T1	40		T3	41		T6	34
valid_sources[0x0a]	570546	1			T1	23		T3	39		T6	36
valid_sources[0x0b]	489333	1			T1	32		T3	22		T6	22
valid_sources[0x0c]	518080	1			T1	24		T3	42		T6	43
valid_sources[0x0d]	504214	1			T1	35		T3	23		T6	37
valid_sources[0x0e]	2792599	1			T1	46		T3	34		T6	43
valid_sources[0x0f]	496767	1			T1	30		T3	21		T6	40
valid_sources[0x10]	497661	1			T1	42		T3	37		T6	43
valid_sources[0x11]	2023271	1			T1	38		T3	35		T6	47
valid_sources[0x12]	530702	1			T1	69		T3	24		T6	26
valid_sources[0x13]	499046	1			T1	34		T3	31		T6	51
valid_sources[0x14]	499012	1			T1	29		T3	31		T6	58
valid_sources[0x15]	507368	1			T1	15		T3	33		T6	43
valid_sources[0x16]	521730	1			T1	61		T3	49		T6	26
valid_sources[0x17]	515027	1			T1	40		T3	35		T6	43
valid_sources[0x18]	501245	1			T1	32		T3	38		T6	38
valid_sources[0x19]	495824	1			T1	40		T3	31		T6	33
valid_sources[0x1a]	536476	1			T1	8		T3	46		T6	47
valid_sources[0x1b]	502465	1			T1	52		T3	36		T6	67
valid_sources[0x1c]	1047461	1			T1	65		T3	40		T6	35
valid_sources[0x1d]	493242	1			T1	46		T3	15		T6	41
valid_sources[0x1e]	523343	1			T1	59		T3	30		T6	34
valid_sources[0x1f]	524764	1			T1	38		T3	35		T6	44
valid_sources[0x20]	539427	1			T1	55		T3	29		T6	57
valid_sources[0x21]	497898	1			T1	31		T3	33		T6	33
valid_sources[0x22]	511909	1			T1	52		T3	27		T6	40
valid_sources[0x23]	506674	1			T1	26		T3	32		T6	43
valid_sources[0x24]	495443	1			T1	25		T3	32		T6	34
valid_sources[0x25]	517073	1			T1	72		T3	24		T6	27
valid_sources[0x26]	537822	1			T1	55		T3	24		T6	28
valid_sources[0x27]	495925	1			T1	46		T3	18		T6	45
valid_sources[0x28]	506206	1			T1	30		T3	31		T6	36
valid_sources[0x29]	494647	1			T1	39		T3	29		T6	54
valid_sources[0x2a]	494248	1			T1	36		T3	33		T6	36
valid_sources[0x2b]	517669	1			T1	47		T3	34		T6	51
valid_sources[0x2c]	498486	1			T1	40		T3	29		T6	39
valid_sources[0x2d]	528620	1			T1	34		T3	37		T6	40
valid_sources[0x2e]	504018	1			T1	34		T3	30		T6	37
valid_sources[0x2f]	503297	1			T1	42		T3	36		T6	53
valid_sources[0x30]	524989	1			T1	43		T3	27		T6	29
valid_sources[0x31]	497836	1			T1	20		T3	35		T6	55
valid_sources[0x32]	2203366	1			T1	43		T3	25		T6	41
valid_sources[0x33]	506557	1			T1	49		T3	22		T6	32
valid_sources[0x34]	497368	1			T1	16		T3	30		T6	41
valid_sources[0x35]	491600	1			T1	29		T3	39		T6	34
valid_sources[0x36]	543120	1			T1	26		T3	40		T6	34
valid_sources[0x37]	539627	1			T1	121		T3	37		T6	32
valid_sources[0x38]	512991	1			T1	46		T3	33		T6	57
valid_sources[0x39]	497190	1			T1	25		T3	39		T6	39
valid_sources[0x3a]	490913	1			T1	21		T3	25		T6	35
valid_sources[0x3b]	508571	1			T1	34		T3	24		T6	40
valid_sources[0x3c]	528559	1			T1	36		T3	27		T6	49
valid_sources[0x3d]	572231	1			T1	37		T3	39		T6	27
valid_sources[0x3e]	520617	1			T1	42		T3	28		T6	56
valid_sources[0x3f]	512605	1			T1	56		T3	23		T6	44
valid_sources[0x40]	531604	1			T1	87		T3	34		T6	59
valid_sources[0x41]	489928	1			T1	37		T3	32		T6	34
valid_sources[0x42]	493337	1			T1	52		T3	42		T6	48
valid_sources[0x43]	492522	1			T1	27		T3	30		T6	41
valid_sources[0x44]	528671	1			T1	29		T3	39		T6	47
valid_sources[0x45]	533606	1			T1	66		T3	31		T6	42
valid_sources[0x46]	491875	1			T1	53		T3	26		T6	29
valid_sources[0x47]	501944	1			T1	40		T3	30		T6	41
valid_sources[0x48]	515125	1			T1	38		T3	40		T6	36
valid_sources[0x49]	1030639	1			T1	58		T3	27		T6	44
valid_sources[0x4a]	546069	1			T1	22		T3	31		T6	46
valid_sources[0x4b]	2223592	1			T1	29		T3	19		T6	43
valid_sources[0x4c]	492772	1			T1	35		T3	31		T6	39
valid_sources[0x4d]	593525	1			T1	32		T3	21		T6	37
valid_sources[0x4e]	496229	1			T1	89		T3	22		T6	36
valid_sources[0x4f]	508645	1			T1	21		T3	45		T6	34
valid_sources[0x50]	542786	1			T1	57		T3	24		T6	49
valid_sources[0x51]	503096	1			T1	65		T3	26		T6	32
valid_sources[0x52]	515258	1			T1	67		T3	30		T6	48
valid_sources[0x53]	496231	1			T1	24		T3	32		T6	29
valid_sources[0x54]	494924	1			T1	39		T3	43		T6	37
valid_sources[0x55]	531644	1			T1	34		T3	24		T6	39
valid_sources[0x56]	533474	1			T1	42		T3	33		T6	46
valid_sources[0x57]	494910	1			T1	10		T3	33		T6	32
valid_sources[0x58]	528474	1			T1	40		T3	44		T6	45
valid_sources[0x59]	627128	1			T1	43		T3	37		T6	36
valid_sources[0x5a]	509790	1			T1	30		T3	34		T6	40
valid_sources[0x5b]	522556	1			T1	23		T3	34		T6	33
valid_sources[0x5c]	576912	1			T1	68		T3	25		T6	65
valid_sources[0x5d]	500387	1			T1	10		T3	36		T6	43
valid_sources[0x5e]	491302	1			T1	40		T3	27		T6	53
valid_sources[0x5f]	622599	1			T1	42		T3	27		T6	41
valid_sources[0x60]	1692984	1			T1	47		T3	36		T6	51
valid_sources[0x61]	491713	1			T1	23		T3	25		T6	46
valid_sources[0x62]	494397	1			T1	65		T3	40		T6	39
valid_sources[0x63]	522811	1			T1	31		T3	31		T6	23
valid_sources[0x64]	504608	1			T1	42		T3	33		T6	46
valid_sources[0x65]	521473	1			T1	36		T3	35		T6	42
valid_sources[0x66]	553086	1			T1	24		T3	40		T6	63
valid_sources[0x67]	529644	1			T1	56		T3	22		T6	31
valid_sources[0x68]	507499	1			T1	36		T3	37		T6	46
valid_sources[0x69]	618405	1			T1	35		T3	27		T6	42
valid_sources[0x6a]	496656	1			T1	28		T3	36		T6	39
valid_sources[0x6b]	514543	1			T1	32		T3	40		T6	36
valid_sources[0x6c]	494770	1			T1	51		T3	42		T6	24
valid_sources[0x6d]	501165	1			T1	31		T3	29		T6	29
valid_sources[0x6e]	499503	1			T1	62		T3	39		T6	37
valid_sources[0x6f]	492744	1			T1	39		T3	36		T6	36
valid_sources[0x70]	504862	1			T1	23		T3	41		T6	38
valid_sources[0x71]	503934	1			T1	62		T3	31		T6	38
valid_sources[0x72]	1371272	1			T1	43		T3	25		T6	40
valid_sources[0x73]	526055	1			T1	68		T3	41		T6	49
valid_sources[0x74]	523156	1			T1	37		T3	38		T6	35
valid_sources[0x75]	524329	1			T1	42		T3	34		T6	44
valid_sources[0x76]	489805	1			T1	40		T3	43		T6	48
valid_sources[0x77]	498550	1			T1	33		T3	23		T6	45
valid_sources[0x78]	534454	1			T1	23		T3	18		T6	40
valid_sources[0x79]	497585	1			T1	46		T3	44		T6	31
valid_sources[0x7a]	502474	1			T1	18		T3	36		T6	60
valid_sources[0x7b]	509875	1			T1	23		T3	36		T6	37
valid_sources[0x7c]	519779	1			T1	33		T3	28		T6	53
valid_sources[0x7d]	612546	1			T1	49		T3	37		T6	24
valid_sources[0x7e]	501437	1			T1	75		T3	32		T6	40
valid_sources[0x7f]	525835	1			T1	26		T3	29		T6	39
valid_sources[0x80]	507183	1			T1	16		T3	31		T6	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65790430

1

T1

4512

T2

294912

T3

4231

values[0x0]

all_enables

biggest_size

34321035

1

T1

2285

T2

147037

T3

2165

values[0x1]

all_enables

biggest_size

34330717

1

T1

2322

T2

147875

T3

2118

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43325844	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

141310

1

T2

2

T10

1

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43346455	1			T1	32812		T2	3126		T3	33066
values[0x0]	58763	1			T1	1		T2	8		T10	1
values[0x1]	61936	1			T1	1		T2	1		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28888406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14578748

1

T1

10906

T2

1087

T3

11119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	391485	1			T1	116		T2	18		T10	13
valid_sources[0x01]	131982	1			T1	115		T2	7		T10	34
valid_sources[0x02]	128747	1			T1	140		T2	19		T10	4
valid_sources[0x03]	128255	1			T1	144		T2	20		T10	20
valid_sources[0x04]	129693	1			T1	130		T2	10		T10	17
valid_sources[0x05]	132575	1			T1	109		T2	22		T10	14
valid_sources[0x06]	130884	1			T1	114		T2	14		T10	17
valid_sources[0x07]	146223	1			T1	130		T2	13		T10	21
valid_sources[0x08]	228853	1			T1	102		T2	14		T10	30
valid_sources[0x09]	493162	1			T1	122		T2	12		T10	10
valid_sources[0x0a]	135006	1			T1	133		T2	12		T10	17
valid_sources[0x0b]	130918	1			T1	125		T2	16		T10	14
valid_sources[0x0c]	131239	1			T1	111		T2	9		T10	3
valid_sources[0x0d]	130969	1			T1	142		T2	11		T10	34
valid_sources[0x0e]	133956	1			T1	130		T2	6		T10	12
valid_sources[0x0f]	144689	1			T1	123		T2	9		T10	14
valid_sources[0x10]	484007	1			T1	118		T2	18		T10	18
valid_sources[0x11]	211893	1			T1	130		T2	10		T3	33068
valid_sources[0x12]	128963	1			T1	130		T2	13		T10	19
valid_sources[0x13]	131300	1			T1	122		T2	14		T10	6
valid_sources[0x14]	180878	1			T1	129		T2	8		T10	6
valid_sources[0x15]	267430	1			T1	120		T2	19		T10	9
valid_sources[0x16]	135527	1			T1	137		T2	4		T10	5
valid_sources[0x17]	131152	1			T1	129		T2	22		T10	18
valid_sources[0x18]	129304	1			T1	106		T2	12		T10	15
valid_sources[0x19]	213047	1			T1	138		T2	10		T10	13
valid_sources[0x1a]	142799	1			T1	128		T2	15		T10	28
valid_sources[0x1b]	130032	1			T1	128		T2	5		T10	60
valid_sources[0x1c]	130698	1			T1	104		T2	16		T10	23
valid_sources[0x1d]	203543	1			T1	132		T2	13		T10	6
valid_sources[0x1e]	128915	1			T1	112		T2	4		T10	28
valid_sources[0x1f]	178978	1			T1	148		T2	13		T10	7
valid_sources[0x20]	130020	1			T1	138		T2	8		T10	10
valid_sources[0x21]	156617	1			T1	124		T2	26		T10	29
valid_sources[0x22]	130172	1			T1	125		T2	11		T10	12
valid_sources[0x23]	195540	1			T1	128		T2	12		T10	13
valid_sources[0x24]	144357	1			T1	141		T2	8		T10	17
valid_sources[0x25]	130388	1			T1	129		T2	5		T10	20
valid_sources[0x26]	129707	1			T1	133		T2	7		T10	24
valid_sources[0x27]	130166	1			T1	104		T2	10		T10	16
valid_sources[0x28]	128898	1			T1	117		T2	15		T10	30
valid_sources[0x29]	140014	1			T1	133		T2	19		T10	12
valid_sources[0x2a]	215039	1			T1	138		T2	8		T10	22
valid_sources[0x2b]	168888	1			T1	140		T2	12		T10	18
valid_sources[0x2c]	128886	1			T1	117		T2	21		T10	15
valid_sources[0x2d]	131024	1			T1	139		T2	13		T10	13
valid_sources[0x2e]	129353	1			T1	132		T2	10		T10	30
valid_sources[0x2f]	132856	1			T1	117		T2	8		T10	16
valid_sources[0x30]	162113	1			T1	144		T2	15		T10	5
valid_sources[0x31]	130589	1			T1	132		T2	6		T10	21
valid_sources[0x32]	164878	1			T1	126		T2	11		T10	27
valid_sources[0x33]	475087	1			T1	109		T2	19		T10	18
valid_sources[0x34]	221861	1			T1	128		T2	7		T10	20
valid_sources[0x35]	168585	1			T1	138		T2	13		T10	21
valid_sources[0x36]	129796	1			T1	124		T2	8		T10	15
valid_sources[0x37]	129653	1			T1	128		T2	11		T10	29
valid_sources[0x38]	135944	1			T1	123		T2	12		T10	2
valid_sources[0x39]	164996	1			T1	142		T2	9		T10	5
valid_sources[0x3a]	163928	1			T1	148		T2	12		T10	38
valid_sources[0x3b]	144304	1			T1	135		T2	17		T10	9
valid_sources[0x3c]	154216	1			T1	151		T2	19		T10	6
valid_sources[0x3d]	412196	1			T1	118		T2	7		T10	38
valid_sources[0x3e]	139949	1			T1	119		T2	23		T10	9
valid_sources[0x3f]	129875	1			T1	127		T2	9		T10	29
valid_sources[0x40]	133928	1			T1	116		T2	14		T10	29
valid_sources[0x41]	130507	1			T1	122		T2	11		T10	3
valid_sources[0x42]	242909	1			T1	131		T2	13		T10	13
valid_sources[0x43]	134779	1			T1	123		T2	13		T10	22
valid_sources[0x44]	129961	1			T1	124		T2	8		T10	22
valid_sources[0x45]	129970	1			T1	113		T2	11		T10	35
valid_sources[0x46]	243693	1			T1	109		T2	19		T10	12
valid_sources[0x47]	146169	1			T1	126		T2	9		T10	10
valid_sources[0x48]	129882	1			T1	142		T2	7		T10	2
valid_sources[0x49]	167267	1			T1	131		T2	13		T10	28
valid_sources[0x4a]	143827	1			T1	110		T2	19		T10	17
valid_sources[0x4b]	130637	1			T1	129		T2	10		T10	7
valid_sources[0x4c]	130954	1			T1	121		T2	15		T10	29
valid_sources[0x4d]	157258	1			T1	115		T2	22		T10	26
valid_sources[0x4e]	145899	1			T1	128		T2	17		T10	11
valid_sources[0x4f]	128858	1			T1	119		T2	19		T10	14
valid_sources[0x50]	137886	1			T1	118		T2	9		T10	27
valid_sources[0x51]	133634	1			T1	118		T2	22		T10	24
valid_sources[0x52]	135656	1			T1	126		T2	17		T10	5
valid_sources[0x53]	136437	1			T1	140		T2	7		T10	22
valid_sources[0x54]	128815	1			T1	117		T2	9		T10	23
valid_sources[0x55]	129687	1			T1	118		T2	8		T10	27
valid_sources[0x56]	141032	1			T1	129		T2	9		T10	6
valid_sources[0x57]	129123	1			T1	136		T2	14		T10	27
valid_sources[0x58]	179276	1			T1	131		T2	11		T10	18
valid_sources[0x59]	129715	1			T1	119		T2	7		T10	15
valid_sources[0x5a]	129246	1			T1	148		T2	12		T10	37
valid_sources[0x5b]	136525	1			T1	120		T2	10		T10	13
valid_sources[0x5c]	137572	1			T1	139		T2	12		T10	8
valid_sources[0x5d]	216224	1			T1	111		T2	11		T10	11
valid_sources[0x5e]	141878	1			T1	118		T2	16		T10	13
valid_sources[0x5f]	147001	1			T1	124		T2	22		T10	35
valid_sources[0x60]	128782	1			T1	118		T2	14		T10	8
valid_sources[0x61]	344370	1			T1	113		T2	16		T10	15
valid_sources[0x62]	132491	1			T1	139		T2	10		T10	13
valid_sources[0x63]	165480	1			T1	123		T2	7		T10	17
valid_sources[0x64]	146868	1			T1	129		T2	9		T10	15
valid_sources[0x65]	579514	1			T1	130		T2	6		T10	34
valid_sources[0x66]	376107	1			T1	128		T2	15		T10	18
valid_sources[0x67]	132981	1			T1	135		T2	10		T10	15
valid_sources[0x68]	130039	1			T1	131		T2	8		T10	22
valid_sources[0x69]	134050	1			T1	139		T2	9		T10	31
valid_sources[0x6a]	128842	1			T1	133		T2	12		T10	36
valid_sources[0x6b]	131883	1			T1	141		T2	16		T10	11
valid_sources[0x6c]	183861	1			T1	141		T2	22		T10	6
valid_sources[0x6d]	195762	1			T1	117		T2	16		T10	1
valid_sources[0x6e]	131610	1			T1	111		T2	9		T10	11
valid_sources[0x6f]	150373	1			T1	127		T2	9		T10	13
valid_sources[0x70]	163017	1			T1	137		T2	17		T10	18
valid_sources[0x71]	228329	1			T1	142		T2	13		T10	46
valid_sources[0x72]	329473	1			T1	124		T2	8		T10	28
valid_sources[0x73]	162030	1			T1	140		T2	15		T10	17
valid_sources[0x74]	129265	1			T1	113		T2	19		T10	4
valid_sources[0x75]	133800	1			T1	143		T2	5		T10	20
valid_sources[0x76]	167100	1			T1	130		T2	7		T10	8
valid_sources[0x77]	132541	1			T1	140		T2	16		T10	19
valid_sources[0x78]	135002	1			T1	139		T2	14		T10	30
valid_sources[0x79]	147308	1			T1	134		T2	8		T10	17
valid_sources[0x7a]	129206	1			T1	116		T2	15		T10	14
valid_sources[0x7b]	539618	1			T1	116		T2	11		T10	7
valid_sources[0x7c]	261444	1			T1	122		T2	9		T10	22
valid_sources[0x7d]	149177	1			T1	137		T2	7		T10	25
valid_sources[0x7e]	276299	1			T1	145		T2	13		T10	21
valid_sources[0x7f]	129897	1			T1	133		T2	8		T10	10
valid_sources[0x80]	134180	1			T1	123		T2	18		T10	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38087

1

T23

564

T24

611

T25

24

values[0x0]

all_enables

biggest_size

52445

1

T2

2

T10

1

T6

1

values[0x1]

all_enables

biggest_size

50778

1

T5

1

T18

1

T23

723