Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15020731

1

T1

917

T4

935

T5

192876

full_word

132301815

1

T1

9119

T2

589824

T3

8514

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	147322256	1			T1	10036		T2	589824		T3	8514
auto[TlIntgErrCmd]	96	1			T53	4		T54	7		T55	5
auto[TlIntgErrData]	85	1			T53	2		T54	4		T55	4
auto[TlIntgErrBoth]	109	1			T53	4		T54	9		T55	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71088356

1

T1

4959

T2

294912

T3

4231

auto[1]

76234190

1

T1

5077

T2

294912

T3

4283

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7389490	1			T1	447		T4	447		T5	96920
auto[TlIntgErrNone]	partial	auto[1]	7630982	1			T1	470		T4	488		T5	95956
auto[TlIntgErrNone]	full_word	auto[0]	63698741	1			T1	4512		T2	294912		T3	4231
auto[TlIntgErrNone]	full_word	auto[1]	68603043	1			T1	4607		T2	294912		T3	4283
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T54	4		T55	3		T96	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T53	4		T54	3		T55	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T96	1		T129	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T125	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T53	1		T54	1		T55	2
auto[TlIntgErrData]	partial	auto[1]	37	1			T53	1		T54	3		T55	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T131	1		T132	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T55	1		T96	1		T129	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T53	1		T54	5		T66	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T53	3		T54	4		T55	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T125	1		T130	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T96	2		T135	1		T131	1