Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	949609	1			T4	2		T14	468		T15	8908
auto[1]	10467866	1			T1	4909		T3	4230		T6	4943
auto[2]	710114	1			T4	1		T14	354		T15	6693
auto[3]	10242329	1			T1	5039		T3	4282		T6	5051

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13233217	1			T1	8284		T3	8512		T6	9994
auto[1]	2140636	1			T1	785		T5	29504		T13	1357
auto[2]	2156456	1			T1	806		T5	29499		T13	1319
auto[3]	4839609	1			T1	73		T5	132536		T13	115

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8293001

1

T1

9948

T3

8512

T6

9994

auto[1]

14076917

1

T5

198116

T19

99053

T15

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	413759	1			T4	2		T14	372		T15	2
auto[0]	auto[0]	auto[1]	43578	1			T14	33		T15	69		T16	511
auto[0]	auto[0]	auto[2]	43501	1			T14	57		T15	80		T16	486
auto[0]	auto[0]	auto[3]	140553	1			T14	6		T15	8755		T16	51
auto[0]	auto[1]	auto[0]	2601842	1			T1	4102		T3	4230		T6	4943
auto[0]	auto[1]	auto[1]	287368	1			T1	361		T13	697		T14	61
auto[0]	auto[1]	auto[2]	295805	1			T1	416		T13	659		T14	23
auto[0]	auto[1]	auto[3]	492972	1			T1	30		T13	55		T14	5
auto[0]	auto[2]	auto[0]	294891	1			T4	1		T14	270		T15	7
auto[0]	auto[2]	auto[1]	41358	1			T14	32		T15	741		T16	301
auto[0]	auto[2]	auto[2]	31322	1			T14	47		T15	38		T16	557
auto[0]	auto[2]	auto[3]	96209	1			T14	5		T15	5907		T16	46
auto[0]	auto[3]	auto[0]	2490154	1			T1	4182		T3	4282		T6	5051
auto[0]	auto[3]	auto[1]	279976	1			T1	424		T13	660		T14	11
auto[0]	auto[3]	auto[2]	309004	1			T1	390		T13	660		T14	47
auto[0]	auto[3]	auto[3]	430709	1			T1	43		T13	60		T14	4
auto[1]	auto[0]	auto[0]	10178	1			T146	1		T140	1		T147	1
auto[1]	auto[0]	auto[1]	45462	1			T148	3554		T149	2806		T150	3201
auto[1]	auto[0]	auto[2]	46129	1			T148	3598		T149	2868		T150	3316
auto[1]	auto[0]	auto[3]	206449	1			T15	2		T144	2		T145	3
auto[1]	auto[1]	auto[0]	3706525	1			T5	3309		T19	40688		T21	1
auto[1]	auto[1]	auto[1]	712674	1			T5	14783		T19	4219		T75	9673
auto[1]	auto[1]	auto[2]	692298	1			T5	14757		T19	4115		T22	1
auto[1]	auto[1]	auto[3]	1678382	1			T5	66651		T19	425		T22	1
auto[1]	auto[2]	auto[0]	9136	1			T151	1		T148	755		T149	588
auto[1]	auto[2]	auto[1]	41281	1			T147	1		T148	3315		T149	2600
auto[1]	auto[2]	auto[2]	35295	1			T151	1		T148	2356		T149	1872
auto[1]	auto[2]	auto[3]	160622	1			T148	10836		T149	8685		T150	12495
auto[1]	auto[3]	auto[0]	3706732	1			T5	3268		T19	41055		T26	4
auto[1]	auto[3]	auto[1]	688939	1			T5	14721		T19	4058		T21	1
auto[1]	auto[3]	auto[2]	703102	1			T5	14742		T19	4066		T75	9638
auto[1]	auto[3]	auto[3]	1633713	1			T5	65885		T19	427		T15	1