Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	990181502	157645	0	0
ctrl_regwen_rd_A	990181502	8908	0	0
exec_rd_A	990181502	8671	0	0
exec_regwen_rd_A	990181502	8917	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990181502	157645	0	0
T15	489404	0	0	0
T16	165036	0	0	0
T20	67537	0	0	0
T21	579504	0	0	0
T23	55159	1803	0	0
T24	174077	2781	0	0
T36	0	2817	0	0
T39	36346	0	0	0
T53	0	4	0	0
T54	0	5	0	0
T55	0	2	0	0
T56	0	1039	0	0
T57	0	3474	0	0
T58	0	109	0	0
T59	0	42	0	0
T63	688260	0	0	0
T64	94905	0	0	0
T65	97170	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990181502	8908	0	0
T37	14813	446	0	0
T53	8186	11	0	0
T56	45949	165	0	0
T57	50253	0	0	0
T60	8686	75	0	0
T61	2733	0	0	0
T62	0	92	0	0
T66	9034	0	0	0
T71	1443	11	0	0
T72	1893	28	0	0
T81	369650	0	0	0
T96	0	74	0	0
T99	0	1	0	0
T100	0	98	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990181502	8671	0	0
T37	14813	493	0	0
T53	8186	21	0	0
T56	45949	191	0	0
T57	50253	0	0	0
T60	8686	64	0	0
T61	2733	0	0	0
T62	0	111	0	0
T66	9034	0	0	0
T71	1443	0	0	0
T72	1893	17	0	0
T81	369650	0	0	0
T96	0	65	0	0
T99	0	7	0	0
T100	0	152	0	0
T125	0	49	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990181502	8917	0	0
T37	14813	470	0	0
T53	8186	35	0	0
T56	45949	131	0	0
T57	50253	0	0	0
T60	8686	51	0	0
T61	2733	0	0	0
T62	0	52	0	0
T66	9034	0	0	0
T71	1443	3	0	0
T72	1893	11	0	0
T81	369650	0	0	0
T96	0	81	0	0
T99	0	28	0	0
T100	0	184	0	0