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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total test records in report: 986
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T755 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2274875641 Jan 17 02:45:02 PM PST 24 Jan 17 02:51:29 PM PST 24 5245855851 ps
T756 /workspace/coverage/default/38.sram_ctrl_mem_walk.1687834255 Jan 17 02:44:00 PM PST 24 Jan 17 02:46:39 PM PST 24 10359807196 ps
T757 /workspace/coverage/default/29.sram_ctrl_executable.1878745261 Jan 17 02:41:10 PM PST 24 Jan 17 02:49:25 PM PST 24 40209668652 ps
T758 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2714532439 Jan 17 02:33:30 PM PST 24 Jan 17 02:41:10 PM PST 24 6160473658 ps
T759 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3130658048 Jan 17 02:43:49 PM PST 24 Jan 17 02:46:03 PM PST 24 1776414523 ps
T760 /workspace/coverage/default/23.sram_ctrl_mem_walk.474795668 Jan 17 02:39:18 PM PST 24 Jan 17 02:44:09 PM PST 24 13917450231 ps
T761 /workspace/coverage/default/18.sram_ctrl_bijection.2543622360 Jan 17 02:37:00 PM PST 24 Jan 17 02:58:12 PM PST 24 115441570112 ps
T762 /workspace/coverage/default/36.sram_ctrl_ram_cfg.823463428 Jan 17 02:43:21 PM PST 24 Jan 17 02:43:36 PM PST 24 1459154409 ps
T763 /workspace/coverage/default/5.sram_ctrl_regwen.3390538693 Jan 17 02:33:32 PM PST 24 Jan 17 02:48:12 PM PST 24 3571053989 ps
T764 /workspace/coverage/default/13.sram_ctrl_bijection.3902922329 Jan 17 02:34:40 PM PST 24 Jan 17 03:13:16 PM PST 24 69021201630 ps
T765 /workspace/coverage/default/18.sram_ctrl_multiple_keys.130322684 Jan 17 02:37:02 PM PST 24 Jan 17 02:49:44 PM PST 24 35100210374 ps
T766 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2389620127 Jan 17 02:35:47 PM PST 24 Jan 17 02:56:14 PM PST 24 7915419898 ps
T767 /workspace/coverage/default/46.sram_ctrl_partial_access.1242806903 Jan 17 02:46:35 PM PST 24 Jan 17 02:47:23 PM PST 24 784373120 ps
T768 /workspace/coverage/default/10.sram_ctrl_bijection.4261623510 Jan 17 02:35:03 PM PST 24 Jan 17 02:54:01 PM PST 24 76502979570 ps
T769 /workspace/coverage/default/37.sram_ctrl_lc_escalation.879633452 Jan 17 02:43:30 PM PST 24 Jan 17 02:45:04 PM PST 24 20356683638 ps
T770 /workspace/coverage/default/1.sram_ctrl_bijection.3683673391 Jan 17 02:32:40 PM PST 24 Jan 17 03:20:52 PM PST 24 351959739422 ps
T771 /workspace/coverage/default/39.sram_ctrl_alert_test.3733166759 Jan 17 02:44:17 PM PST 24 Jan 17 02:44:18 PM PST 24 15660739 ps
T772 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3389830744 Jan 17 02:46:13 PM PST 24 Jan 17 02:48:05 PM PST 24 16289964327 ps
T773 /workspace/coverage/default/27.sram_ctrl_mem_walk.2730720606 Jan 17 02:40:38 PM PST 24 Jan 17 02:44:57 PM PST 24 23187253153 ps
T774 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3556415480 Jan 17 02:46:15 PM PST 24 Jan 17 02:50:19 PM PST 24 12545328121 ps
T775 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1945641906 Jan 17 02:39:13 PM PST 24 Jan 17 02:45:12 PM PST 24 18582977986 ps
T776 /workspace/coverage/default/2.sram_ctrl_bijection.3967015754 Jan 17 02:32:26 PM PST 24 Jan 17 02:42:11 PM PST 24 105790287727 ps
T777 /workspace/coverage/default/21.sram_ctrl_partial_access.1606557667 Jan 17 02:38:33 PM PST 24 Jan 17 02:38:56 PM PST 24 398407511 ps
T778 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1452267188 Jan 17 02:43:31 PM PST 24 Jan 17 02:47:07 PM PST 24 2975156859 ps
T779 /workspace/coverage/default/31.sram_ctrl_stress_all.803643354 Jan 17 02:41:57 PM PST 24 Jan 17 03:53:23 PM PST 24 56972452090 ps
T780 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1005657171 Jan 17 02:39:54 PM PST 24 Jan 17 02:49:10 PM PST 24 18622260717 ps
T781 /workspace/coverage/default/17.sram_ctrl_bijection.1364690027 Jan 17 02:36:30 PM PST 24 Jan 17 03:13:36 PM PST 24 31806456594 ps
T782 /workspace/coverage/default/15.sram_ctrl_partial_access.3539533000 Jan 17 02:35:40 PM PST 24 Jan 17 02:36:15 PM PST 24 630057558 ps
T783 /workspace/coverage/default/30.sram_ctrl_alert_test.2474951804 Jan 17 02:41:41 PM PST 24 Jan 17 02:41:43 PM PST 24 19794994 ps
T784 /workspace/coverage/default/49.sram_ctrl_regwen.2385224505 Jan 17 02:47:44 PM PST 24 Jan 17 03:09:26 PM PST 24 14172560880 ps
T785 /workspace/coverage/default/10.sram_ctrl_mem_walk.4284966623 Jan 17 02:34:45 PM PST 24 Jan 17 02:38:58 PM PST 24 15765427377 ps
T786 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2933757553 Jan 17 02:47:00 PM PST 24 Jan 17 04:12:32 PM PST 24 433409878 ps
T787 /workspace/coverage/default/15.sram_ctrl_alert_test.1492616638 Jan 17 02:37:36 PM PST 24 Jan 17 02:37:43 PM PST 24 37962376 ps
T788 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.591876536 Jan 17 02:40:20 PM PST 24 Jan 17 04:08:05 PM PST 24 19465020752 ps
T789 /workspace/coverage/default/46.sram_ctrl_max_throughput.1967709914 Jan 17 02:46:31 PM PST 24 Jan 17 02:46:59 PM PST 24 2672332422 ps
T790 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1815234288 Jan 17 02:39:21 PM PST 24 Jan 17 02:40:47 PM PST 24 17387362793 ps
T791 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.886443544 Jan 17 02:38:44 PM PST 24 Jan 17 03:09:46 PM PST 24 1098886155 ps
T792 /workspace/coverage/default/21.sram_ctrl_stress_all.1153786797 Jan 17 02:38:46 PM PST 24 Jan 17 03:58:39 PM PST 24 444271764614 ps
T793 /workspace/coverage/default/36.sram_ctrl_multiple_keys.2308819429 Jan 17 02:43:07 PM PST 24 Jan 17 03:33:11 PM PST 24 35236307023 ps
T794 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1732692600 Jan 17 02:44:03 PM PST 24 Jan 17 04:42:38 PM PST 24 1453462535 ps
T795 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.230376629 Jan 17 02:37:37 PM PST 24 Jan 17 02:42:35 PM PST 24 8538250812 ps
T796 /workspace/coverage/default/41.sram_ctrl_alert_test.3375683677 Jan 17 02:45:03 PM PST 24 Jan 17 02:45:06 PM PST 24 33511483 ps
T797 /workspace/coverage/default/16.sram_ctrl_multiple_keys.3900961867 Jan 17 02:36:03 PM PST 24 Jan 17 02:46:00 PM PST 24 9065996501 ps
T798 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2230483235 Jan 17 02:33:01 PM PST 24 Jan 17 02:34:23 PM PST 24 4663206858 ps
T799 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3439344765 Jan 17 02:40:13 PM PST 24 Jan 17 03:03:22 PM PST 24 13649099709 ps
T800 /workspace/coverage/default/1.sram_ctrl_max_throughput.1880073017 Jan 17 02:32:21 PM PST 24 Jan 17 02:34:40 PM PST 24 3138310663 ps
T801 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3908020458 Jan 17 02:45:21 PM PST 24 Jan 17 02:54:41 PM PST 24 54951515363 ps
T802 /workspace/coverage/default/5.sram_ctrl_stress_all.3802681155 Jan 17 02:35:08 PM PST 24 Jan 17 04:23:20 PM PST 24 88810785598 ps
T803 /workspace/coverage/default/7.sram_ctrl_multiple_keys.3966413525 Jan 17 02:35:07 PM PST 24 Jan 17 02:50:17 PM PST 24 8354828369 ps
T804 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.240263474 Jan 17 02:33:31 PM PST 24 Jan 17 03:13:58 PM PST 24 790737507 ps
T805 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.848590728 Jan 17 02:34:35 PM PST 24 Jan 17 02:41:16 PM PST 24 13792006222 ps
T806 /workspace/coverage/default/21.sram_ctrl_executable.398582701 Jan 17 02:38:38 PM PST 24 Jan 17 02:45:17 PM PST 24 8072864683 ps
T807 /workspace/coverage/default/4.sram_ctrl_smoke.3402440436 Jan 17 02:35:02 PM PST 24 Jan 17 02:35:19 PM PST 24 3097283824 ps
T91 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2863232116 Jan 17 02:44:58 PM PST 24 Jan 17 02:47:37 PM PST 24 20406303082 ps
T808 /workspace/coverage/default/31.sram_ctrl_ram_cfg.259660668 Jan 17 02:41:59 PM PST 24 Jan 17 02:42:13 PM PST 24 345560856 ps
T809 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.490006922 Jan 17 02:43:31 PM PST 24 Jan 17 02:44:11 PM PST 24 2841199112 ps
T810 /workspace/coverage/default/26.sram_ctrl_smoke.3472582107 Jan 17 02:40:00 PM PST 24 Jan 17 02:40:34 PM PST 24 4078151096 ps
T811 /workspace/coverage/default/22.sram_ctrl_smoke.939430403 Jan 17 02:38:48 PM PST 24 Jan 17 02:40:03 PM PST 24 1723862165 ps
T812 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1203126612 Jan 17 02:37:59 PM PST 24 Jan 17 02:38:28 PM PST 24 685489444 ps
T813 /workspace/coverage/default/32.sram_ctrl_alert_test.559172919 Jan 17 02:42:25 PM PST 24 Jan 17 02:42:27 PM PST 24 14304844 ps
T814 /workspace/coverage/default/43.sram_ctrl_executable.3713618505 Jan 17 02:45:37 PM PST 24 Jan 17 03:03:29 PM PST 24 26658359857 ps
T815 /workspace/coverage/default/15.sram_ctrl_stress_all.933687579 Jan 17 02:38:02 PM PST 24 Jan 17 03:47:00 PM PST 24 241124405800 ps
T816 /workspace/coverage/default/28.sram_ctrl_partial_access.429168525 Jan 17 02:40:50 PM PST 24 Jan 17 02:41:18 PM PST 24 5634167627 ps
T817 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3148637783 Jan 17 02:42:08 PM PST 24 Jan 17 02:43:11 PM PST 24 3461613245 ps
T818 /workspace/coverage/default/31.sram_ctrl_mem_walk.1342159208 Jan 17 02:41:58 PM PST 24 Jan 17 02:44:40 PM PST 24 41251930432 ps
T819 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1230141864 Jan 17 02:32:08 PM PST 24 Jan 17 02:38:46 PM PST 24 5043537873 ps
T820 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3834851929 Jan 17 02:45:36 PM PST 24 Jan 17 03:37:47 PM PST 24 1737108676 ps
T821 /workspace/coverage/default/40.sram_ctrl_regwen.1017469649 Jan 17 02:44:36 PM PST 24 Jan 17 03:01:53 PM PST 24 33479723384 ps
T822 /workspace/coverage/default/0.sram_ctrl_mem_walk.2101285111 Jan 17 02:32:11 PM PST 24 Jan 17 02:34:32 PM PST 24 28642996633 ps
T823 /workspace/coverage/default/27.sram_ctrl_executable.3043236668 Jan 17 02:41:19 PM PST 24 Jan 17 03:16:17 PM PST 24 43104437608 ps
T824 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2123810562 Jan 17 02:42:52 PM PST 24 Jan 17 03:15:08 PM PST 24 4111056930 ps
T825 /workspace/coverage/default/7.sram_ctrl_alert_test.320673224 Jan 17 02:33:39 PM PST 24 Jan 17 02:33:41 PM PST 24 11668206 ps
T826 /workspace/coverage/default/48.sram_ctrl_ram_cfg.1032759784 Jan 17 02:47:21 PM PST 24 Jan 17 02:47:35 PM PST 24 707169509 ps
T827 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3260329289 Jan 17 02:39:55 PM PST 24 Jan 17 02:45:14 PM PST 24 12442577927 ps
T828 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.958518363 Jan 17 02:44:05 PM PST 24 Jan 17 02:50:55 PM PST 24 7960760065 ps
T829 /workspace/coverage/default/12.sram_ctrl_mem_walk.3268220946 Jan 17 02:34:32 PM PST 24 Jan 17 02:38:53 PM PST 24 7880290528 ps
T830 /workspace/coverage/default/3.sram_ctrl_bijection.2152576117 Jan 17 02:34:10 PM PST 24 Jan 17 03:03:38 PM PST 24 25351542869 ps
T831 /workspace/coverage/default/5.sram_ctrl_lc_escalation.1621034869 Jan 17 02:32:57 PM PST 24 Jan 17 02:36:23 PM PST 24 17735393158 ps
T832 /workspace/coverage/default/43.sram_ctrl_max_throughput.1745752124 Jan 17 02:45:37 PM PST 24 Jan 17 02:46:06 PM PST 24 695475881 ps
T833 /workspace/coverage/default/1.sram_ctrl_partial_access.1485917387 Jan 17 02:33:18 PM PST 24 Jan 17 02:33:48 PM PST 24 1470878709 ps
T834 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2979836339 Jan 17 02:38:37 PM PST 24 Jan 17 02:39:52 PM PST 24 742057898 ps
T835 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1695323177 Jan 17 02:35:03 PM PST 24 Jan 17 02:39:48 PM PST 24 3319393660 ps
T836 /workspace/coverage/default/43.sram_ctrl_multiple_keys.3251071969 Jan 17 02:45:31 PM PST 24 Jan 17 02:53:48 PM PST 24 10586914410 ps
T837 /workspace/coverage/default/5.sram_ctrl_partial_access.1158318850 Jan 17 02:32:58 PM PST 24 Jan 17 02:34:06 PM PST 24 479846979 ps
T838 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.723423876 Jan 17 02:43:09 PM PST 24 Jan 17 02:43:49 PM PST 24 2766722486 ps
T839 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3102840835 Jan 17 02:34:40 PM PST 24 Jan 17 02:56:25 PM PST 24 9358166870 ps
T840 /workspace/coverage/default/14.sram_ctrl_lc_escalation.3580602470 Jan 17 02:35:18 PM PST 24 Jan 17 02:36:49 PM PST 24 34013686088 ps
T841 /workspace/coverage/default/19.sram_ctrl_max_throughput.2640527918 Jan 17 02:37:32 PM PST 24 Jan 17 02:40:51 PM PST 24 804118880 ps
T842 /workspace/coverage/default/3.sram_ctrl_multiple_keys.3816087927 Jan 17 02:32:25 PM PST 24 Jan 17 02:57:35 PM PST 24 21215268820 ps
T843 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1074514098 Jan 17 02:46:14 PM PST 24 Jan 17 02:51:39 PM PST 24 11593348749 ps
T844 /workspace/coverage/default/10.sram_ctrl_max_throughput.3363660139 Jan 17 02:37:39 PM PST 24 Jan 17 02:38:08 PM PST 24 696918266 ps
T845 /workspace/coverage/default/27.sram_ctrl_partial_access.2683581596 Jan 17 02:40:22 PM PST 24 Jan 17 02:40:48 PM PST 24 3217916878 ps
T846 /workspace/coverage/default/12.sram_ctrl_regwen.2920665961 Jan 17 02:34:33 PM PST 24 Jan 17 02:50:27 PM PST 24 16682684247 ps
T847 /workspace/coverage/default/20.sram_ctrl_bijection.1575186572 Jan 17 02:37:54 PM PST 24 Jan 17 02:51:26 PM PST 24 346660260161 ps
T848 /workspace/coverage/default/41.sram_ctrl_multiple_keys.3560660345 Jan 17 02:44:51 PM PST 24 Jan 17 02:51:19 PM PST 24 2670278675 ps
T849 /workspace/coverage/default/48.sram_ctrl_smoke.180725494 Jan 17 02:47:00 PM PST 24 Jan 17 02:48:01 PM PST 24 1166348690 ps
T850 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3827060781 Jan 17 02:45:36 PM PST 24 Jan 17 02:48:06 PM PST 24 8855067367 ps
T851 /workspace/coverage/default/16.sram_ctrl_executable.3164697826 Jan 17 02:36:27 PM PST 24 Jan 17 02:44:05 PM PST 24 5288178332 ps
T852 /workspace/coverage/default/47.sram_ctrl_regwen.3038220942 Jan 17 02:46:55 PM PST 24 Jan 17 02:58:38 PM PST 24 45794806310 ps
T853 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.157945696 Jan 17 02:32:55 PM PST 24 Jan 17 02:40:13 PM PST 24 17597583560 ps
T854 /workspace/coverage/default/43.sram_ctrl_partial_access.3089911075 Jan 17 02:45:30 PM PST 24 Jan 17 02:45:53 PM PST 24 751068861 ps
T40 /workspace/coverage/default/1.sram_ctrl_sec_cm.72501594 Jan 17 02:32:36 PM PST 24 Jan 17 02:32:40 PM PST 24 371408349 ps
T855 /workspace/coverage/default/6.sram_ctrl_smoke.2172148667 Jan 17 02:34:16 PM PST 24 Jan 17 02:37:02 PM PST 24 793553094 ps
T856 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.586925407 Jan 17 02:40:49 PM PST 24 Jan 17 02:41:22 PM PST 24 998761129 ps
T857 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2332825405 Jan 17 02:41:24 PM PST 24 Jan 17 03:03:08 PM PST 24 31900573144 ps
T858 /workspace/coverage/default/41.sram_ctrl_partial_access.3051085561 Jan 17 02:44:58 PM PST 24 Jan 17 02:45:26 PM PST 24 3040021804 ps
T859 /workspace/coverage/default/14.sram_ctrl_multiple_keys.890065761 Jan 17 02:35:09 PM PST 24 Jan 17 02:48:19 PM PST 24 20829501213 ps
T860 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3657927509 Jan 17 02:35:24 PM PST 24 Jan 17 02:36:05 PM PST 24 2799321487 ps
T861 /workspace/coverage/default/13.sram_ctrl_partial_access.2242867495 Jan 17 02:34:45 PM PST 24 Jan 17 02:35:18 PM PST 24 623342387 ps
T862 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1611756215 Jan 17 02:44:09 PM PST 24 Jan 17 03:03:27 PM PST 24 40731111421 ps
T863 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.976769744 Jan 17 02:38:53 PM PST 24 Jan 17 02:43:25 PM PST 24 4248558128 ps
T864 /workspace/coverage/default/18.sram_ctrl_partial_access.1096154237 Jan 17 02:37:10 PM PST 24 Jan 17 02:40:01 PM PST 24 2111903699 ps
T865 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.167610304 Jan 17 02:37:14 PM PST 24 Jan 17 04:13:51 PM PST 24 861462746 ps
T866 /workspace/coverage/default/27.sram_ctrl_alert_test.3385468921 Jan 17 02:40:37 PM PST 24 Jan 17 02:40:46 PM PST 24 23969967 ps
T867 /workspace/coverage/default/37.sram_ctrl_partial_access.3610160443 Jan 17 02:43:30 PM PST 24 Jan 17 02:43:57 PM PST 24 1347457135 ps
T868 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4059761670 Jan 17 02:46:30 PM PST 24 Jan 17 02:50:47 PM PST 24 21347765425 ps
T869 /workspace/coverage/default/11.sram_ctrl_alert_test.2406235463 Jan 17 02:38:19 PM PST 24 Jan 17 02:38:21 PM PST 24 17527771 ps
T870 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.122260715 Jan 17 02:44:23 PM PST 24 Jan 17 02:49:53 PM PST 24 45425217703 ps
T871 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3482714110 Jan 17 02:45:22 PM PST 24 Jan 17 02:46:45 PM PST 24 3309793300 ps
T872 /workspace/coverage/default/46.sram_ctrl_mem_walk.203627069 Jan 17 02:46:39 PM PST 24 Jan 17 02:49:13 PM PST 24 10322338759 ps
T873 /workspace/coverage/default/5.sram_ctrl_smoke.2593319934 Jan 17 02:34:05 PM PST 24 Jan 17 02:36:45 PM PST 24 783650935 ps
T874 /workspace/coverage/default/16.sram_ctrl_ram_cfg.190178381 Jan 17 02:37:39 PM PST 24 Jan 17 02:37:49 PM PST 24 1350383951 ps
T875 /workspace/coverage/default/10.sram_ctrl_smoke.1797193901 Jan 17 02:35:17 PM PST 24 Jan 17 02:35:50 PM PST 24 985186817 ps
T876 /workspace/coverage/default/1.sram_ctrl_mem_walk.2259970462 Jan 17 02:32:16 PM PST 24 Jan 17 02:34:26 PM PST 24 2021926825 ps
T92 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1069726228 Jan 17 02:46:22 PM PST 24 Jan 17 02:47:44 PM PST 24 6485749749 ps
T877 /workspace/coverage/default/21.sram_ctrl_max_throughput.958135496 Jan 17 02:38:38 PM PST 24 Jan 17 02:39:11 PM PST 24 3753591306 ps
T878 /workspace/coverage/default/25.sram_ctrl_bijection.633819828 Jan 17 02:39:49 PM PST 24 Jan 17 02:59:52 PM PST 24 260902386715 ps
T879 /workspace/coverage/default/9.sram_ctrl_smoke.2083535000 Jan 17 02:33:47 PM PST 24 Jan 17 02:34:23 PM PST 24 6512384684 ps
T880 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.813069323 Jan 17 02:40:20 PM PST 24 Jan 17 02:42:52 PM PST 24 5049271088 ps
T881 /workspace/coverage/default/29.sram_ctrl_partial_access.1757029195 Jan 17 02:41:03 PM PST 24 Jan 17 02:41:31 PM PST 24 720734400 ps
T882 /workspace/coverage/default/3.sram_ctrl_mem_walk.842795187 Jan 17 02:33:11 PM PST 24 Jan 17 02:35:40 PM PST 24 6959257734 ps
T883 /workspace/coverage/default/0.sram_ctrl_partial_access.1528764046 Jan 17 02:32:06 PM PST 24 Jan 17 02:32:24 PM PST 24 1527395695 ps
T884 /workspace/coverage/default/48.sram_ctrl_partial_access.2604636271 Jan 17 02:47:11 PM PST 24 Jan 17 02:47:45 PM PST 24 1604584238 ps
T885 /workspace/coverage/default/6.sram_ctrl_stress_all.3984786994 Jan 17 02:34:20 PM PST 24 Jan 17 03:53:03 PM PST 24 73679436953 ps
T886 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.278824008 Jan 17 02:38:43 PM PST 24 Jan 17 02:40:19 PM PST 24 9035278481 ps
T887 /workspace/coverage/default/32.sram_ctrl_stress_all.1328918495 Jan 17 02:42:08 PM PST 24 Jan 17 03:49:54 PM PST 24 164915056761 ps
T888 /workspace/coverage/default/47.sram_ctrl_bijection.1296607714 Jan 17 02:46:47 PM PST 24 Jan 17 03:19:07 PM PST 24 58090797218 ps
T889 /workspace/coverage/default/20.sram_ctrl_multiple_keys.3669221341 Jan 17 02:37:52 PM PST 24 Jan 17 02:52:52 PM PST 24 40238539070 ps
T890 /workspace/coverage/default/9.sram_ctrl_multiple_keys.2662493017 Jan 17 02:34:58 PM PST 24 Jan 17 02:49:15 PM PST 24 50889841568 ps
T891 /workspace/coverage/default/18.sram_ctrl_mem_walk.1653860071 Jan 17 02:37:13 PM PST 24 Jan 17 02:41:30 PM PST 24 3943653895 ps
T892 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2685887408 Jan 17 02:37:34 PM PST 24 Jan 17 02:38:26 PM PST 24 2847863318 ps
T893 /workspace/coverage/default/32.sram_ctrl_smoke.384022845 Jan 17 02:41:57 PM PST 24 Jan 17 02:42:10 PM PST 24 4801343105 ps
T894 /workspace/coverage/default/6.sram_ctrl_regwen.3219569119 Jan 17 02:33:07 PM PST 24 Jan 17 02:58:50 PM PST 24 4901124289 ps
T895 /workspace/coverage/default/32.sram_ctrl_multiple_keys.95724961 Jan 17 02:41:59 PM PST 24 Jan 17 03:04:34 PM PST 24 96967828152 ps
T896 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3895560071 Jan 17 02:47:34 PM PST 24 Jan 17 02:48:02 PM PST 24 699645736 ps
T897 /workspace/coverage/default/3.sram_ctrl_partial_access.2590895415 Jan 17 02:34:18 PM PST 24 Jan 17 02:34:58 PM PST 24 5476082577 ps
T898 /workspace/coverage/default/7.sram_ctrl_mem_walk.923643947 Jan 17 02:33:42 PM PST 24 Jan 17 02:38:52 PM PST 24 53013371144 ps
T899 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1866200546 Jan 17 02:46:04 PM PST 24 Jan 17 02:47:24 PM PST 24 2399680744 ps
T900 /workspace/coverage/default/38.sram_ctrl_stress_all.3785288391 Jan 17 02:44:04 PM PST 24 Jan 17 04:07:41 PM PST 24 53644627845 ps
T901 /workspace/coverage/default/30.sram_ctrl_max_throughput.1302415387 Jan 17 02:41:19 PM PST 24 Jan 17 02:42:04 PM PST 24 1435741884 ps
T902 /workspace/coverage/default/30.sram_ctrl_lc_escalation.4008574309 Jan 17 02:41:24 PM PST 24 Jan 17 02:43:59 PM PST 24 15840007936 ps
T903 /workspace/coverage/default/35.sram_ctrl_mem_walk.157920312 Jan 17 02:43:07 PM PST 24 Jan 17 02:48:23 PM PST 24 21512041927 ps
T904 /workspace/coverage/default/35.sram_ctrl_lc_escalation.3936300779 Jan 17 02:43:05 PM PST 24 Jan 17 02:44:54 PM PST 24 27832171879 ps
T905 /workspace/coverage/default/8.sram_ctrl_stress_all.2570506124 Jan 17 02:33:44 PM PST 24 Jan 17 04:25:56 PM PST 24 313388239110 ps
T906 /workspace/coverage/default/27.sram_ctrl_stress_all.3614445196 Jan 17 02:40:38 PM PST 24 Jan 17 04:03:15 PM PST 24 369638129097 ps
T907 /workspace/coverage/default/44.sram_ctrl_max_throughput.3393881127 Jan 17 02:45:56 PM PST 24 Jan 17 02:46:24 PM PST 24 687743985 ps
T908 /workspace/coverage/default/1.sram_ctrl_multiple_keys.1727921631 Jan 17 02:32:27 PM PST 24 Jan 17 03:06:28 PM PST 24 31195060763 ps
T909 /workspace/coverage/default/48.sram_ctrl_mem_walk.932517122 Jan 17 02:47:20 PM PST 24 Jan 17 02:51:30 PM PST 24 16421377540 ps
T910 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1777075111 Jan 17 02:36:05 PM PST 24 Jan 17 02:40:08 PM PST 24 11420838081 ps
T911 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.984458549 Jan 17 02:34:07 PM PST 24 Jan 17 02:40:09 PM PST 24 51491938646 ps
T912 /workspace/coverage/default/44.sram_ctrl_alert_test.163324306 Jan 17 02:46:12 PM PST 24 Jan 17 02:46:14 PM PST 24 13990260 ps
T913 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3444719197 Jan 17 02:37:16 PM PST 24 Jan 17 02:37:30 PM PST 24 1361833839 ps
T914 /workspace/coverage/default/27.sram_ctrl_multiple_keys.2886921973 Jan 17 02:40:19 PM PST 24 Jan 17 02:55:07 PM PST 24 74974796671 ps
T915 /workspace/coverage/default/12.sram_ctrl_max_throughput.3598853962 Jan 17 02:34:34 PM PST 24 Jan 17 02:37:02 PM PST 24 775800456 ps
T916 /workspace/coverage/default/45.sram_ctrl_alert_test.3431187330 Jan 17 02:46:35 PM PST 24 Jan 17 02:46:36 PM PST 24 18579389 ps
T917 /workspace/coverage/default/18.sram_ctrl_alert_test.465195281 Jan 17 02:37:18 PM PST 24 Jan 17 02:37:19 PM PST 24 42507726 ps
T918 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3615513161 Jan 17 02:39:05 PM PST 24 Jan 17 02:57:38 PM PST 24 3021318204 ps
T919 /workspace/coverage/default/10.sram_ctrl_lc_escalation.3735433778 Jan 17 02:36:08 PM PST 24 Jan 17 02:40:59 PM PST 24 47254544302 ps
T920 /workspace/coverage/default/26.sram_ctrl_multiple_keys.2461198938 Jan 17 02:40:08 PM PST 24 Jan 17 03:01:46 PM PST 24 9445524770 ps
T921 /workspace/coverage/default/24.sram_ctrl_max_throughput.2006119294 Jan 17 02:39:33 PM PST 24 Jan 17 02:40:24 PM PST 24 821669709 ps
T922 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2054131497 Jan 17 02:38:13 PM PST 24 Jan 17 02:39:34 PM PST 24 1971489106 ps
T923 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.966123824 Jan 17 02:33:55 PM PST 24 Jan 17 02:39:21 PM PST 24 4865386139 ps
T924 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2678291436 Jan 17 02:45:21 PM PST 24 Jan 17 02:46:47 PM PST 24 17458180257 ps
T925 /workspace/coverage/default/29.sram_ctrl_lc_escalation.156832464 Jan 17 02:41:02 PM PST 24 Jan 17 02:43:17 PM PST 24 38546360521 ps
T926 /workspace/coverage/default/19.sram_ctrl_alert_test.3749487622 Jan 17 02:37:56 PM PST 24 Jan 17 02:37:57 PM PST 24 23530513 ps
T927 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3187757561 Jan 17 02:46:56 PM PST 24 Jan 17 02:53:18 PM PST 24 15135116746 ps
T928 /workspace/coverage/default/26.sram_ctrl_partial_access.2440427712 Jan 17 02:40:05 PM PST 24 Jan 17 02:41:35 PM PST 24 479842514 ps
T929 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1062100387 Jan 17 02:38:04 PM PST 24 Jan 17 02:55:02 PM PST 24 35366512864 ps
T930 /workspace/coverage/default/17.sram_ctrl_smoke.4209940025 Jan 17 02:36:29 PM PST 24 Jan 17 02:38:28 PM PST 24 1230863976 ps
T931 /workspace/coverage/default/40.sram_ctrl_ram_cfg.1567268375 Jan 17 02:44:36 PM PST 24 Jan 17 02:44:42 PM PST 24 709416713 ps
T932 /workspace/coverage/default/44.sram_ctrl_multiple_keys.3529215263 Jan 17 02:45:49 PM PST 24 Jan 17 03:09:57 PM PST 24 26228575847 ps
T933 /workspace/coverage/default/45.sram_ctrl_partial_access.1211970792 Jan 17 02:46:14 PM PST 24 Jan 17 02:48:54 PM PST 24 875160097 ps
T934 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3773768220 Jan 17 02:44:58 PM PST 24 Jan 17 03:07:09 PM PST 24 23566989312 ps
T935 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4049887194 Jan 17 02:42:16 PM PST 24 Jan 17 02:46:37 PM PST 24 8460517061 ps
T936 /workspace/coverage/default/25.sram_ctrl_alert_test.1850504079 Jan 17 02:40:00 PM PST 24 Jan 17 02:40:14 PM PST 24 23691349 ps
T937 /workspace/coverage/default/15.sram_ctrl_bijection.3414048438 Jan 17 02:35:33 PM PST 24 Jan 17 02:48:04 PM PST 24 45097017085 ps
T938 /workspace/coverage/default/15.sram_ctrl_multiple_keys.3019169565 Jan 17 02:35:33 PM PST 24 Jan 17 02:51:39 PM PST 24 50895016400 ps
T939 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.170446454 Jan 17 02:32:14 PM PST 24 Jan 17 03:19:36 PM PST 24 4231455995 ps
T940 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1093341049 Jan 17 02:35:36 PM PST 24 Jan 17 02:42:20 PM PST 24 33203414487 ps
T941 /workspace/coverage/default/22.sram_ctrl_ram_cfg.3764235008 Jan 17 02:39:01 PM PST 24 Jan 17 02:39:16 PM PST 24 349381141 ps
T942 /workspace/coverage/default/17.sram_ctrl_stress_all.485889370 Jan 17 02:36:57 PM PST 24 Jan 17 04:02:44 PM PST 24 73066814856 ps
T943 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2944185531 Jan 17 02:41:56 PM PST 24 Jan 17 02:43:13 PM PST 24 4334481288 ps
T944 /workspace/coverage/default/22.sram_ctrl_alert_test.1729049564 Jan 17 02:39:08 PM PST 24 Jan 17 02:39:10 PM PST 24 48957969 ps
T945 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3345096990 Jan 17 02:39:29 PM PST 24 Jan 17 02:42:47 PM PST 24 2969089725 ps
T946 /workspace/coverage/default/24.sram_ctrl_bijection.4016923495 Jan 17 02:39:25 PM PST 24 Jan 17 02:55:43 PM PST 24 56011913833 ps
T947 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.786770278 Jan 17 02:40:55 PM PST 24 Jan 17 02:58:14 PM PST 24 9298607842 ps
T948 /workspace/coverage/default/40.sram_ctrl_executable.2041478543 Jan 17 02:44:37 PM PST 24 Jan 17 03:03:16 PM PST 24 6014235978 ps
T949 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4018342429 Jan 17 02:39:31 PM PST 24 Jan 17 02:44:17 PM PST 24 4490070418 ps
T950 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3130744979 Jan 17 02:43:44 PM PST 24 Jan 17 02:49:17 PM PST 24 168507021344 ps
T951 /workspace/coverage/default/14.sram_ctrl_alert_test.2262801274 Jan 17 02:35:25 PM PST 24 Jan 17 02:35:27 PM PST 24 11661254 ps
T952 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4193897008 Jan 17 02:34:17 PM PST 24 Jan 17 02:41:47 PM PST 24 22784165103 ps
T953 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3398596412 Jan 17 02:47:38 PM PST 24 Jan 17 02:51:22 PM PST 24 8240565830 ps
T954 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.727008470 Jan 17 02:39:14 PM PST 24 Jan 17 02:41:18 PM PST 24 3033634608 ps
T955 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3980950910 Jan 17 02:40:05 PM PST 24 Jan 17 02:44:34 PM PST 24 4146866920 ps
T956 /workspace/coverage/default/40.sram_ctrl_partial_access.1508589027 Jan 17 02:44:23 PM PST 24 Jan 17 02:44:53 PM PST 24 772105478 ps
T957 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3449789275 Jan 17 02:34:00 PM PST 24 Jan 17 02:41:31 PM PST 24 2432146949 ps
T958 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2984539552 Jan 17 02:39:20 PM PST 24 Jan 17 02:39:30 PM PST 24 1459594495 ps
T959 /workspace/coverage/default/12.sram_ctrl_smoke.3864563781 Jan 17 02:34:20 PM PST 24 Jan 17 02:34:51 PM PST 24 3071047445 ps
T960 /workspace/coverage/default/13.sram_ctrl_mem_walk.1552057528 Jan 17 02:34:57 PM PST 24 Jan 17 02:37:25 PM PST 24 7239119753 ps
T961 /workspace/coverage/default/29.sram_ctrl_max_throughput.1262955537 Jan 17 02:41:02 PM PST 24 Jan 17 02:42:31 PM PST 24 762872185 ps
T962 /workspace/coverage/default/7.sram_ctrl_smoke.211502428 Jan 17 02:33:10 PM PST 24 Jan 17 02:33:40 PM PST 24 5284593228 ps
T963 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3073686511 Jan 17 02:32:23 PM PST 24 Jan 17 02:32:31 PM PST 24 369542171 ps
T964 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3218367551 Jan 17 02:43:05 PM PST 24 Jan 17 02:46:47 PM PST 24 2054656390 ps
T965 /workspace/coverage/default/17.sram_ctrl_ram_cfg.4018941476 Jan 17 02:36:48 PM PST 24 Jan 17 02:37:03 PM PST 24 357147643 ps
T966 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.755676759 Jan 17 02:42:16 PM PST 24 Jan 17 02:46:21 PM PST 24 80458088454 ps
T967 /workspace/coverage/default/2.sram_ctrl_max_throughput.2780350644 Jan 17 02:32:53 PM PST 24 Jan 17 02:34:04 PM PST 24 757964156 ps
T968 /workspace/coverage/default/39.sram_ctrl_partial_access.2288889998 Jan 17 02:44:03 PM PST 24 Jan 17 02:44:39 PM PST 24 1191127341 ps
T969 /workspace/coverage/default/9.sram_ctrl_stress_all.2520096985 Jan 17 02:34:09 PM PST 24 Jan 17 05:10:42 PM PST 24 344694711804 ps
T970 /workspace/coverage/default/39.sram_ctrl_multiple_keys.2447528226 Jan 17 02:44:03 PM PST 24 Jan 17 02:56:44 PM PST 24 12036674835 ps
T971 /workspace/coverage/default/9.sram_ctrl_max_throughput.4192572335 Jan 17 02:34:19 PM PST 24 Jan 17 02:34:54 PM PST 24 3460388667 ps
T972 /workspace/coverage/default/26.sram_ctrl_ram_cfg.2052685590 Jan 17 02:40:20 PM PST 24 Jan 17 02:40:28 PM PST 24 363052508 ps
T973 /workspace/coverage/default/23.sram_ctrl_stress_all.1876263640 Jan 17 02:39:21 PM PST 24 Jan 17 04:00:22 PM PST 24 87755773241 ps
T974 /workspace/coverage/default/42.sram_ctrl_mem_walk.2808936845 Jan 17 02:45:23 PM PST 24 Jan 17 02:50:12 PM PST 24 37252665845 ps
T975 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2660488783 Jan 17 02:40:50 PM PST 24 Jan 17 02:47:02 PM PST 24 44894737180 ps
T976 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1990768176 Jan 17 02:32:26 PM PST 24 Jan 17 02:50:12 PM PST 24 29558366919 ps
T977 /workspace/coverage/default/45.sram_ctrl_executable.3302437879 Jan 17 02:46:23 PM PST 24 Jan 17 02:51:01 PM PST 24 6810904673 ps
T978 /workspace/coverage/default/25.sram_ctrl_multiple_keys.2084684534 Jan 17 02:39:50 PM PST 24 Jan 17 02:59:46 PM PST 24 19351379441 ps
T41 /workspace/coverage/default/4.sram_ctrl_sec_cm.749810374 Jan 17 02:33:39 PM PST 24 Jan 17 02:33:44 PM PST 24 869698957 ps
T979 /workspace/coverage/default/9.sram_ctrl_regwen.1265297814 Jan 17 02:37:41 PM PST 24 Jan 17 02:45:23 PM PST 24 9900721430 ps
T980 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1594175619 Jan 17 02:32:32 PM PST 24 Jan 17 02:41:25 PM PST 24 52055165295 ps
T981 /workspace/coverage/default/27.sram_ctrl_max_throughput.2596769042 Jan 17 02:40:30 PM PST 24 Jan 17 02:42:45 PM PST 24 10755211300 ps
T982 /workspace/coverage/default/38.sram_ctrl_alert_test.1766332237 Jan 17 02:44:03 PM PST 24 Jan 17 02:44:07 PM PST 24 11504031 ps
T983 /workspace/coverage/default/22.sram_ctrl_regwen.944720333 Jan 17 02:39:03 PM PST 24 Jan 17 03:05:25 PM PST 24 64478459859 ps
T984 /workspace/coverage/default/4.sram_ctrl_ram_cfg.1455658716 Jan 17 02:34:21 PM PST 24 Jan 17 02:34:31 PM PST 24 363631098 ps
T985 /workspace/coverage/default/48.sram_ctrl_lc_escalation.385759964 Jan 17 02:47:14 PM PST 24 Jan 17 02:49:51 PM PST 24 48227974890 ps
T986 /workspace/coverage/default/36.sram_ctrl_max_throughput.1478009348 Jan 17 02:43:14 PM PST 24 Jan 17 02:44:02 PM PST 24 2419860137 ps

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.53285938
Short name T13
Test name
Test status
Simulation time 2194437506 ps
CPU time 184.27 seconds
Started Jan 17 02:36:46 PM PST 24
Finished Jan 17 02:39:51 PM PST 24
Peak memory 347080 kb
Host smart-f6a5bdc8-8b3d-4bdc-8b52-8fa6731da6db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53285938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.sram_ctrl_access_during_key_req.53285938
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.567255026
Short name T7
Test name
Test status
Simulation time 275412597845 ps
CPU time 4474.69 seconds
Started Jan 17 02:39:44 PM PST 24
Finished Jan 17 03:54:26 PM PST 24
Peak memory 388324 kb
Host smart-a6b5438a-eb41-4006-864a-f4333f8cb073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567255026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_stress_all.567255026
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.192037293
Short name T23
Test name
Test status
Simulation time 1173654538 ps
CPU time 6136.59 seconds
Started Jan 17 02:45:24 PM PST 24
Finished Jan 17 04:27:43 PM PST 24
Peak memory 676580 kb
Host smart-0d67b6b5-82cf-4449-92ba-1baef888aa24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=192037293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.192037293
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.685718936
Short name T53
Test name
Test status
Simulation time 355940826 ps
CPU time 1.55 seconds
Started Jan 17 03:53:13 PM PST 24
Finished Jan 17 03:53:16 PM PST 24
Peak memory 202516 kb
Host smart-9b41af08-e2f3-4bfa-8f4a-01b4db4f1270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685718936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.sram_ctrl_tl_intg_err.685718936
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.931066499
Short name T15
Test name
Test status
Simulation time 5098150832 ps
CPU time 158.4 seconds
Started Jan 17 02:36:24 PM PST 24
Finished Jan 17 02:39:03 PM PST 24
Peak memory 213500 kb
Host smart-a1e16902-a19b-4307-8560-ce1574559fe6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931066499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.sram_ctrl_mem_partial_access.931066499
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.3029820148
Short name T31
Test name
Test status
Simulation time 222070964 ps
CPU time 3.21 seconds
Started Jan 17 02:33:24 PM PST 24
Finished Jan 17 02:33:28 PM PST 24
Peak memory 221088 kb
Host smart-51b8540d-cbb5-4e0c-9f01-382ceb49f3fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029820148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.3029820148
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.2154448149
Short name T35
Test name
Test status
Simulation time 156711993447 ps
CPU time 1410.33 seconds
Started Jan 17 02:32:54 PM PST 24
Finished Jan 17 02:56:25 PM PST 24
Peak memory 375988 kb
Host smart-7f5befdd-dc3d-428a-a0c4-6639855f91f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154448149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.2154448149
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1303238627
Short name T129
Test name
Test status
Simulation time 1247603045 ps
CPU time 2.04 seconds
Started Jan 17 03:53:09 PM PST 24
Finished Jan 17 03:53:16 PM PST 24
Peak memory 202448 kb
Host smart-6bbca08a-b492-4c86-ac95-5b85d4cdf8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303238627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.1303238627
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.752103300
Short name T5
Test name
Test status
Simulation time 23131689758 ps
CPU time 400.45 seconds
Started Jan 17 02:41:00 PM PST 24
Finished Jan 17 02:47:57 PM PST 24
Peak memory 202188 kb
Host smart-bfd2064c-ec54-4638-ab1e-14d7b24d08ee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752103300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.sram_ctrl_partial_access_b2b.752103300
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1294568963
Short name T576
Test name
Test status
Simulation time 12510052198 ps
CPU time 293.01 seconds
Started Jan 17 02:38:33 PM PST 24
Finished Jan 17 02:43:27 PM PST 24
Peak memory 202120 kb
Host smart-9ceda8ac-a93f-421a-a903-5d2acd49cde1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294568963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1294568963
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.907552427
Short name T67
Test name
Test status
Simulation time 28155523785 ps
CPU time 271.72 seconds
Started Jan 17 03:53:02 PM PST 24
Finished Jan 17 03:57:35 PM PST 24
Peak memory 202524 kb
Host smart-8f2fab93-8573-4efe-a555-49f306ae8cbc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907552427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.907552427
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.2144936970
Short name T12
Test name
Test status
Simulation time 348989186 ps
CPU time 13.74 seconds
Started Jan 17 02:32:41 PM PST 24
Finished Jan 17 02:32:56 PM PST 24
Peak memory 202420 kb
Host smart-19ab1804-51f9-4393-b5d3-d6fa3bc64c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144936970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2144936970
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2395068917
Short name T131
Test name
Test status
Simulation time 353817499 ps
CPU time 2.19 seconds
Started Jan 17 03:52:56 PM PST 24
Finished Jan 17 03:52:59 PM PST 24
Peak memory 202452 kb
Host smart-5615864d-6b87-4933-971e-589858d32af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395068917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2395068917
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.4134859872
Short name T308
Test name
Test status
Simulation time 32421812 ps
CPU time 0.71 seconds
Started Jan 17 02:40:17 PM PST 24
Finished Jan 17 02:40:19 PM PST 24
Peak memory 201392 kb
Host smart-c48da91f-adc7-4818-ba92-6424d5b16e49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134859872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.4134859872
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2664239765
Short name T130
Test name
Test status
Simulation time 162896296 ps
CPU time 2.03 seconds
Started Jan 17 03:52:38 PM PST 24
Finished Jan 17 03:52:43 PM PST 24
Peak memory 202460 kb
Host smart-e90d2932-8ccd-4c72-ade0-f5069489ed61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664239765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.2664239765
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1406838752
Short name T109
Test name
Test status
Simulation time 1407747508 ps
CPU time 13.63 seconds
Started Jan 17 03:53:13 PM PST 24
Finished Jan 17 03:53:28 PM PST 24
Peak memory 210724 kb
Host smart-95124c2a-99ce-42ee-ae91-ba020bdf3111
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406838752 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1406838752
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.2189107846
Short name T494
Test name
Test status
Simulation time 52393443117 ps
CPU time 811.04 seconds
Started Jan 17 02:32:23 PM PST 24
Finished Jan 17 02:45:56 PM PST 24
Peak memory 370924 kb
Host smart-9d70d5dc-41ec-432e-88d4-815ebd9001dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189107846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2189107846
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.515996007
Short name T90
Test name
Test status
Simulation time 25657302 ps
CPU time 0.69 seconds
Started Jan 17 03:52:32 PM PST 24
Finished Jan 17 03:52:34 PM PST 24
Peak memory 202112 kb
Host smart-7d9fb255-9022-4c20-96c1-78c42794410d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515996007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_aliasing.515996007
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.63717851
Short name T37
Test name
Test status
Simulation time 155940674 ps
CPU time 2.03 seconds
Started Jan 17 03:52:33 PM PST 24
Finished Jan 17 03:52:36 PM PST 24
Peak memory 201676 kb
Host smart-3dca3153-72a9-47ac-9ef7-dccc7e341597
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63717851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_bit_bash.63717851
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.6229872
Short name T216
Test name
Test status
Simulation time 118562966 ps
CPU time 0.64 seconds
Started Jan 17 03:52:38 PM PST 24
Finished Jan 17 03:52:42 PM PST 24
Peak memory 202168 kb
Host smart-15e172ef-65f9-4a3d-ba70-ab843b99bd91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6229872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_csr_hw_reset.6229872
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3275608353
Short name T180
Test name
Test status
Simulation time 454395140 ps
CPU time 5.65 seconds
Started Jan 17 03:52:40 PM PST 24
Finished Jan 17 03:52:47 PM PST 24
Peak memory 202420 kb
Host smart-132604c5-aedb-475f-9315-1ec7baa3ce61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275608353 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3275608353
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2403511452
Short name T188
Test name
Test status
Simulation time 12411361 ps
CPU time 0.64 seconds
Started Jan 17 03:52:33 PM PST 24
Finished Jan 17 03:52:39 PM PST 24
Peak memory 201440 kb
Host smart-e81c3212-1e8e-436d-93fd-ca5bb7fccd75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403511452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.2403511452
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.343942941
Short name T93
Test name
Test status
Simulation time 4449829162 ps
CPU time 153.11 seconds
Started Jan 17 03:52:31 PM PST 24
Finished Jan 17 03:55:06 PM PST 24
Peak memory 210716 kb
Host smart-0a6ffbc1-4286-4e2d-ab8e-09efecebef37
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343942941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.343942941
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2029586975
Short name T213
Test name
Test status
Simulation time 16646415 ps
CPU time 0.66 seconds
Started Jan 17 03:52:33 PM PST 24
Finished Jan 17 03:52:39 PM PST 24
Peak memory 202264 kb
Host smart-6f1fcdd7-a93c-47e7-8d51-b730dbd7d9d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029586975 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2029586975
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3644593523
Short name T60
Test name
Test status
Simulation time 163924768 ps
CPU time 2.81 seconds
Started Jan 17 03:52:38 PM PST 24
Finished Jan 17 03:52:44 PM PST 24
Peak memory 202376 kb
Host smart-ddafae78-2a44-40e1-9264-9353347b5bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644593523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3644593523
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.560627960
Short name T189
Test name
Test status
Simulation time 258255801 ps
CPU time 1.4 seconds
Started Jan 17 03:52:40 PM PST 24
Finished Jan 17 03:52:43 PM PST 24
Peak memory 202472 kb
Host smart-37c32e6a-4612-4a0a-9762-275bbbf64132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560627960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.sram_ctrl_tl_intg_err.560627960
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1698929515
Short name T199
Test name
Test status
Simulation time 85798557 ps
CPU time 0.7 seconds
Started Jan 17 03:52:40 PM PST 24
Finished Jan 17 03:52:42 PM PST 24
Peak memory 202120 kb
Host smart-3e506da4-2d1c-4075-b888-ed5a9df28ab1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698929515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.1698929515
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3773701918
Short name T102
Test name
Test status
Simulation time 393190710 ps
CPU time 2.11 seconds
Started Jan 17 03:52:38 PM PST 24
Finished Jan 17 03:52:43 PM PST 24
Peak memory 202152 kb
Host smart-6d87a64e-5728-4567-b9e1-ff5a9867f019
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773701918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.3773701918
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.398120546
Short name T232
Test name
Test status
Simulation time 55988911 ps
CPU time 0.66 seconds
Started Jan 17 03:52:41 PM PST 24
Finished Jan 17 03:52:43 PM PST 24
Peak memory 201632 kb
Host smart-64d71bf9-0326-42f0-a2be-30292798fb5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398120546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_hw_reset.398120546
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3666796585
Short name T201
Test name
Test status
Simulation time 369214629 ps
CPU time 4.79 seconds
Started Jan 17 03:52:39 PM PST 24
Finished Jan 17 03:52:46 PM PST 24
Peak memory 202476 kb
Host smart-36dde64e-a0bd-458c-ace3-0139787d32d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666796585 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3666796585
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2473092607
Short name T113
Test name
Test status
Simulation time 53909339 ps
CPU time 0.64 seconds
Started Jan 17 03:52:39 PM PST 24
Finished Jan 17 03:52:42 PM PST 24
Peak memory 202168 kb
Host smart-bf56b0d6-2e40-4299-85bf-d4ed9073a5a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473092607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.2473092607
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1411899020
Short name T200
Test name
Test status
Simulation time 12373084656 ps
CPU time 140.08 seconds
Started Jan 17 03:52:38 PM PST 24
Finished Jan 17 03:55:01 PM PST 24
Peak memory 210732 kb
Host smart-035cfaf6-1aa4-4910-80a7-510cab4f7eb1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411899020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1411899020
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2353483064
Short name T78
Test name
Test status
Simulation time 23529584 ps
CPU time 0.75 seconds
Started Jan 17 03:52:38 PM PST 24
Finished Jan 17 03:52:42 PM PST 24
Peak memory 202188 kb
Host smart-96662a2d-7e0c-4862-aa2f-5b76978d26dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353483064 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.2353483064
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2794089058
Short name T231
Test name
Test status
Simulation time 22133755 ps
CPU time 1.84 seconds
Started Jan 17 03:52:36 PM PST 24
Finished Jan 17 03:52:43 PM PST 24
Peak memory 202712 kb
Host smart-339ae3dd-d342-4003-aee8-dc1134beb857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794089058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2794089058
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2363368363
Short name T212
Test name
Test status
Simulation time 25443380 ps
CPU time 0.64 seconds
Started Jan 17 03:53:10 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 202180 kb
Host smart-815f9ac4-f4b7-4766-a6c3-e3df1189d4c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363368363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.2363368363
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.527534666
Short name T229
Test name
Test status
Simulation time 18485943797 ps
CPU time 56.76 seconds
Started Jan 17 03:53:10 PM PST 24
Finished Jan 17 03:54:11 PM PST 24
Peak memory 210708 kb
Host smart-6c9b2bfb-fb9a-40b6-81bd-257a1eb87a1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527534666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.527534666
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4116969627
Short name T182
Test name
Test status
Simulation time 42057480 ps
CPU time 0.68 seconds
Started Jan 17 03:53:10 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 202248 kb
Host smart-a089ec31-6fe4-45af-a818-5bff1be69edf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116969627 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.4116969627
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1630263235
Short name T184
Test name
Test status
Simulation time 136503658 ps
CPU time 4.05 seconds
Started Jan 17 03:53:13 PM PST 24
Finished Jan 17 03:53:18 PM PST 24
Peak memory 202408 kb
Host smart-94e1f998-a160-4988-a765-46fc52022b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630263235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.1630263235
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3197369384
Short name T55
Test name
Test status
Simulation time 95249990 ps
CPU time 1.43 seconds
Started Jan 17 03:53:10 PM PST 24
Finished Jan 17 03:53:16 PM PST 24
Peak memory 202452 kb
Host smart-88c35f65-b31c-431a-903e-80d6e244ec0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197369384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.3197369384
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.855878840
Short name T218
Test name
Test status
Simulation time 712009745 ps
CPU time 6.44 seconds
Started Jan 17 03:53:13 PM PST 24
Finished Jan 17 03:53:21 PM PST 24
Peak memory 210680 kb
Host smart-b44d88bd-bf4d-4925-bf1b-4066d86cee69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855878840 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.855878840
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1021368744
Short name T164
Test name
Test status
Simulation time 36391751 ps
CPU time 0.64 seconds
Started Jan 17 03:53:16 PM PST 24
Finished Jan 17 03:53:17 PM PST 24
Peak memory 201556 kb
Host smart-be959aa3-d070-408a-b8f5-77649873a9b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021368744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.1021368744
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.944006017
Short name T103
Test name
Test status
Simulation time 28500908301 ps
CPU time 50.83 seconds
Started Jan 17 03:53:12 PM PST 24
Finished Jan 17 03:54:05 PM PST 24
Peak memory 210764 kb
Host smart-8dec900e-1672-406f-84c7-e92a8fc7872b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944006017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.944006017
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1079665348
Short name T79
Test name
Test status
Simulation time 20749147 ps
CPU time 0.69 seconds
Started Jan 17 03:53:13 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 201856 kb
Host smart-af3130d7-d6bf-44b2-88b4-dee26d618b55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079665348 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1079665348
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.716931300
Short name T226
Test name
Test status
Simulation time 128594687 ps
CPU time 3.54 seconds
Started Jan 17 03:53:15 PM PST 24
Finished Jan 17 03:53:19 PM PST 24
Peak memory 202432 kb
Host smart-2a6e23d1-5f04-4a17-91da-674bdb8d6c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716931300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.716931300
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.740291125
Short name T110
Test name
Test status
Simulation time 479970962 ps
CPU time 1.84 seconds
Started Jan 17 03:53:13 PM PST 24
Finished Jan 17 03:53:16 PM PST 24
Peak memory 202444 kb
Host smart-ed446300-5357-4776-a264-53f5f5626f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740291125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.sram_ctrl_tl_intg_err.740291125
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1781200280
Short name T224
Test name
Test status
Simulation time 3218149220 ps
CPU time 6.83 seconds
Started Jan 17 03:53:24 PM PST 24
Finished Jan 17 03:53:32 PM PST 24
Peak memory 210756 kb
Host smart-ac82d11a-c9c6-4994-a5e9-e20bc41e45e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781200280 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1781200280
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1101854271
Short name T111
Test name
Test status
Simulation time 38138234 ps
CPU time 0.64 seconds
Started Jan 17 03:53:24 PM PST 24
Finished Jan 17 03:53:25 PM PST 24
Peak memory 202164 kb
Host smart-73c10b33-25b8-4ca1-bb2b-a173bf09b554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101854271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.1101854271
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.415746590
Short name T179
Test name
Test status
Simulation time 28174078140 ps
CPU time 127.53 seconds
Started Jan 17 03:53:16 PM PST 24
Finished Jan 17 03:55:25 PM PST 24
Peak memory 202480 kb
Host smart-d1be4ed5-7902-4913-bb67-13628a2b9f99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415746590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.415746590
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.341343870
Short name T198
Test name
Test status
Simulation time 140459390 ps
CPU time 0.65 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:53:28 PM PST 24
Peak memory 201788 kb
Host smart-ca64b420-9a54-4273-8172-0914854cba2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341343870 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.341343870
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3411436651
Short name T108
Test name
Test status
Simulation time 72468801 ps
CPU time 2.47 seconds
Started Jan 17 03:53:14 PM PST 24
Finished Jan 17 03:53:17 PM PST 24
Peak memory 202432 kb
Host smart-b200a05c-e5b7-448f-8291-0e5e98382cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411436651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.3411436651
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.517539274
Short name T183
Test name
Test status
Simulation time 238026442 ps
CPU time 1.34 seconds
Started Jan 17 03:53:16 PM PST 24
Finished Jan 17 03:53:18 PM PST 24
Peak memory 202372 kb
Host smart-5a833ea7-363d-43f0-a437-7d90baabdd14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517539274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.sram_ctrl_tl_intg_err.517539274
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1202450485
Short name T105
Test name
Test status
Simulation time 682998559 ps
CPU time 12.05 seconds
Started Jan 17 03:53:24 PM PST 24
Finished Jan 17 03:53:37 PM PST 24
Peak memory 202488 kb
Host smart-d48fa40c-263e-4445-99d0-453da0127039
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202450485 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1202450485
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3391900918
Short name T71
Test name
Test status
Simulation time 14461847 ps
CPU time 0.68 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:53:27 PM PST 24
Peak memory 201596 kb
Host smart-158c51f0-6c60-4ec9-a26b-65387dcfcd17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391900918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.3391900918
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2168161253
Short name T114
Test name
Test status
Simulation time 100496798219 ps
CPU time 155.3 seconds
Started Jan 17 03:53:25 PM PST 24
Finished Jan 17 03:56:01 PM PST 24
Peak memory 211756 kb
Host smart-c42ecf4b-b1e1-4859-8ed7-09d09f8740fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168161253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2168161253
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3619059823
Short name T233
Test name
Test status
Simulation time 20932280 ps
CPU time 0.66 seconds
Started Jan 17 03:53:25 PM PST 24
Finished Jan 17 03:53:27 PM PST 24
Peak memory 202292 kb
Host smart-3367c899-6aa0-4cab-af81-31b5d1fd9119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619059823 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3619059823
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.133983930
Short name T208
Test name
Test status
Simulation time 238867017 ps
CPU time 2.41 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:53:28 PM PST 24
Peak memory 202732 kb
Host smart-593960c5-f78a-4adb-a143-4a0db5f3335a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133983930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_tl_errors.133983930
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1903270670
Short name T209
Test name
Test status
Simulation time 111238837 ps
CPU time 1.49 seconds
Started Jan 17 03:53:27 PM PST 24
Finished Jan 17 03:53:29 PM PST 24
Peak memory 202420 kb
Host smart-e4349f37-3e31-40fd-bc76-4c519c78939f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903270670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.1903270670
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.712308193
Short name T97
Test name
Test status
Simulation time 1374955825 ps
CPU time 12.5 seconds
Started Jan 17 03:53:30 PM PST 24
Finished Jan 17 03:53:45 PM PST 24
Peak memory 210628 kb
Host smart-313acd9f-b3fa-41b3-8a68-3c6daa5831b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712308193 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.712308193
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2042043165
Short name T173
Test name
Test status
Simulation time 23037281 ps
CPU time 0.65 seconds
Started Jan 17 03:53:29 PM PST 24
Finished Jan 17 03:53:33 PM PST 24
Peak memory 202244 kb
Host smart-58bcb0f6-8cbb-4b01-84f8-c72e683141fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042043165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.2042043165
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.907847730
Short name T106
Test name
Test status
Simulation time 7578330389 ps
CPU time 141.09 seconds
Started Jan 17 03:53:27 PM PST 24
Finished Jan 17 03:55:52 PM PST 24
Peak memory 202576 kb
Host smart-b469846e-8a06-4459-85f5-a6b3f68fd9ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907847730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.907847730
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3891411158
Short name T172
Test name
Test status
Simulation time 33074870 ps
CPU time 0.72 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:53:28 PM PST 24
Peak memory 202196 kb
Host smart-3d988dc1-3813-46f0-848e-32c2e8aa9a5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891411158 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3891411158
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.816304752
Short name T205
Test name
Test status
Simulation time 300694754 ps
CPU time 2.85 seconds
Started Jan 17 03:53:29 PM PST 24
Finished Jan 17 03:53:35 PM PST 24
Peak memory 202384 kb
Host smart-d06d0286-e5ca-4d32-8b38-6a9c64c6f123
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816304752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_tl_errors.816304752
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3501422474
Short name T66
Test name
Test status
Simulation time 376501820 ps
CPU time 1.49 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:53:28 PM PST 24
Peak memory 202500 kb
Host smart-845c10e6-af13-4a5c-be77-40c13911e11c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501422474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3501422474
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1393342140
Short name T95
Test name
Test status
Simulation time 356939994 ps
CPU time 6.09 seconds
Started Jan 17 03:53:28 PM PST 24
Finished Jan 17 03:53:37 PM PST 24
Peak memory 210720 kb
Host smart-95d022e5-15d5-4931-8a2b-f7d20b65e8a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393342140 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1393342140
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2928481468
Short name T215
Test name
Test status
Simulation time 33229564 ps
CPU time 0.64 seconds
Started Jan 17 03:53:30 PM PST 24
Finished Jan 17 03:53:34 PM PST 24
Peak memory 201440 kb
Host smart-77f376e8-c30d-4b7b-8cd9-4c934ee0758d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928481468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.2928481468
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2838486959
Short name T87
Test name
Test status
Simulation time 8205043879 ps
CPU time 145.15 seconds
Started Jan 17 03:53:29 PM PST 24
Finished Jan 17 03:55:58 PM PST 24
Peak memory 202616 kb
Host smart-34fe1d49-9044-4e6e-9018-571e56f118fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838486959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2838486959
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2215973528
Short name T190
Test name
Test status
Simulation time 27808089 ps
CPU time 0.76 seconds
Started Jan 17 03:53:25 PM PST 24
Finished Jan 17 03:53:27 PM PST 24
Peak memory 202256 kb
Host smart-96856652-90f5-4e22-8811-0098f58084bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215973528 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2215973528
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2236405537
Short name T214
Test name
Test status
Simulation time 157616228 ps
CPU time 1.82 seconds
Started Jan 17 03:53:27 PM PST 24
Finished Jan 17 03:53:31 PM PST 24
Peak memory 202408 kb
Host smart-e97b36a2-6322-41be-be29-a92425433ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236405537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.2236405537
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2934901669
Short name T128
Test name
Test status
Simulation time 91726502 ps
CPU time 1.44 seconds
Started Jan 17 03:53:30 PM PST 24
Finished Jan 17 03:53:34 PM PST 24
Peak memory 202452 kb
Host smart-560c9492-61ab-40cd-9a6d-d505144cda56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934901669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2934901669
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1615076882
Short name T58
Test name
Test status
Simulation time 1446431460 ps
CPU time 13.88 seconds
Started Jan 17 03:53:28 PM PST 24
Finished Jan 17 03:53:45 PM PST 24
Peak memory 210636 kb
Host smart-48bbd0c1-7d02-425a-ab54-3ca4444db200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615076882 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1615076882
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2586479879
Short name T70
Test name
Test status
Simulation time 32421379 ps
CPU time 0.65 seconds
Started Jan 17 03:53:31 PM PST 24
Finished Jan 17 03:53:34 PM PST 24
Peak memory 202164 kb
Host smart-8a2764a9-157c-4155-9779-58b846f96697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586479879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.2586479879
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3739831863
Short name T116
Test name
Test status
Simulation time 14104605480 ps
CPU time 101.75 seconds
Started Jan 17 03:53:30 PM PST 24
Finished Jan 17 03:55:15 PM PST 24
Peak memory 202576 kb
Host smart-d7c28388-32c9-4fa4-94c6-9af640550afc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739831863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.3739831863
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1710518611
Short name T221
Test name
Test status
Simulation time 94183159 ps
CPU time 0.76 seconds
Started Jan 17 03:53:30 PM PST 24
Finished Jan 17 03:53:33 PM PST 24
Peak memory 202140 kb
Host smart-26fe9909-a53b-4143-bde0-423964c2991c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710518611 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1710518611
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1660914782
Short name T222
Test name
Test status
Simulation time 31677539 ps
CPU time 3.3 seconds
Started Jan 17 03:53:32 PM PST 24
Finished Jan 17 03:53:37 PM PST 24
Peak memory 202376 kb
Host smart-1dd6155b-c134-4abe-8cf6-26cbbe06232e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660914782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.1660914782
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1159534807
Short name T133
Test name
Test status
Simulation time 139676220 ps
CPU time 1.58 seconds
Started Jan 17 03:53:28 PM PST 24
Finished Jan 17 03:53:32 PM PST 24
Peak memory 202412 kb
Host smart-a53be4a4-3077-4b0c-a4af-44591b1fdb5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159534807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1159534807
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.859196246
Short name T107
Test name
Test status
Simulation time 770999966 ps
CPU time 4.75 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:53:32 PM PST 24
Peak memory 202452 kb
Host smart-7ba27914-2734-4e98-8f0c-a9dfeb65bab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859196246 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.859196246
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4185480844
Short name T175
Test name
Test status
Simulation time 16109703 ps
CPU time 0.66 seconds
Started Jan 17 03:53:28 PM PST 24
Finished Jan 17 03:53:32 PM PST 24
Peak memory 201264 kb
Host smart-c5fea422-6c11-4317-939a-8cab6a9bc7cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185480844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.4185480844
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.787195697
Short name T81
Test name
Test status
Simulation time 16802531303 ps
CPU time 65.66 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:54:32 PM PST 24
Peak memory 211816 kb
Host smart-784fe3a4-fe18-4baf-bebd-a50e6e446784
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787195697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.787195697
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1270524391
Short name T228
Test name
Test status
Simulation time 31783859 ps
CPU time 0.72 seconds
Started Jan 17 03:53:25 PM PST 24
Finished Jan 17 03:53:26 PM PST 24
Peak memory 202228 kb
Host smart-1c857895-4004-4e8a-bbbe-fe5693895f6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270524391 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1270524391
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1129622503
Short name T174
Test name
Test status
Simulation time 94657951 ps
CPU time 1.99 seconds
Started Jan 17 03:53:30 PM PST 24
Finished Jan 17 03:53:35 PM PST 24
Peak memory 202424 kb
Host smart-6d71a801-93c6-4843-80ba-269301f022a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129622503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1129622503
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3525826199
Short name T98
Test name
Test status
Simulation time 106393792 ps
CPU time 1.39 seconds
Started Jan 17 03:53:26 PM PST 24
Finished Jan 17 03:53:29 PM PST 24
Peak memory 202464 kb
Host smart-85aefae9-757e-42ee-84c2-55bfd595208e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525826199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.3525826199
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2359999076
Short name T202
Test name
Test status
Simulation time 386476707 ps
CPU time 13.83 seconds
Started Jan 17 03:53:31 PM PST 24
Finished Jan 17 03:53:48 PM PST 24
Peak memory 210608 kb
Host smart-aa8c76f8-29ef-4779-8e03-89ba3914da58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359999076 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2359999076
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1233023002
Short name T117
Test name
Test status
Simulation time 62666982 ps
CPU time 0.63 seconds
Started Jan 17 03:53:33 PM PST 24
Finished Jan 17 03:53:35 PM PST 24
Peak memory 202152 kb
Host smart-159c1c13-ae8a-4b17-9427-aecf60d4cb65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233023002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.1233023002
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3272034334
Short name T80
Test name
Test status
Simulation time 35192614119 ps
CPU time 270.73 seconds
Started Jan 17 03:53:51 PM PST 24
Finished Jan 17 03:58:23 PM PST 24
Peak memory 202576 kb
Host smart-db08a137-6929-46df-b2bc-0a22c3494f3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272034334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3272034334
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3822360309
Short name T170
Test name
Test status
Simulation time 23857204 ps
CPU time 0.69 seconds
Started Jan 17 03:53:37 PM PST 24
Finished Jan 17 03:53:42 PM PST 24
Peak memory 202276 kb
Host smart-64d75bf4-f4d8-49b9-ade7-66733eb2776e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822360309 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3822360309
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1978850589
Short name T197
Test name
Test status
Simulation time 432712767 ps
CPU time 3.55 seconds
Started Jan 17 03:53:32 PM PST 24
Finished Jan 17 03:53:37 PM PST 24
Peak memory 202416 kb
Host smart-4a817e26-861d-4c96-b0c5-51bfe3c1ecd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978850589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.1978850589
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1998451110
Short name T96
Test name
Test status
Simulation time 780892345 ps
CPU time 2.28 seconds
Started Jan 17 03:53:41 PM PST 24
Finished Jan 17 03:53:44 PM PST 24
Peak memory 202564 kb
Host smart-a1da05e4-a13f-4e13-98b9-2253df4d6a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998451110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.1998451110
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.853090455
Short name T225
Test name
Test status
Simulation time 1423481990 ps
CPU time 12.81 seconds
Started Jan 17 03:53:35 PM PST 24
Finished Jan 17 03:53:54 PM PST 24
Peak memory 210628 kb
Host smart-fd091b3e-8209-4f55-ac34-a588bafb4996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853090455 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.853090455
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2453004702
Short name T211
Test name
Test status
Simulation time 22088081 ps
CPU time 0.69 seconds
Started Jan 17 03:53:36 PM PST 24
Finished Jan 17 03:53:42 PM PST 24
Peak memory 201368 kb
Host smart-0f8a368a-6fd5-4884-898c-77235e363b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453004702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.2453004702
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3129408651
Short name T115
Test name
Test status
Simulation time 7362539608 ps
CPU time 97.92 seconds
Started Jan 17 03:53:32 PM PST 24
Finished Jan 17 03:55:12 PM PST 24
Peak memory 202548 kb
Host smart-88766e0b-d4c4-4923-b4e2-e6b53c280e30
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129408651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3129408651
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.261852625
Short name T204
Test name
Test status
Simulation time 16286401 ps
CPU time 0.69 seconds
Started Jan 17 03:53:37 PM PST 24
Finished Jan 17 03:53:42 PM PST 24
Peak memory 202256 kb
Host smart-89e959c1-d7a8-4a98-b3e9-66d678bf54bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261852625 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.261852625
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2510173648
Short name T176
Test name
Test status
Simulation time 668831492 ps
CPU time 3.05 seconds
Started Jan 17 03:53:32 PM PST 24
Finished Jan 17 03:53:37 PM PST 24
Peak memory 202504 kb
Host smart-87d5caf4-6cbd-44f3-a0c7-85e3ec54acb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510173648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.2510173648
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3193137628
Short name T125
Test name
Test status
Simulation time 2182721408 ps
CPU time 3.28 seconds
Started Jan 17 03:53:34 PM PST 24
Finished Jan 17 03:53:44 PM PST 24
Peak memory 202524 kb
Host smart-e33c75a9-00c4-4c07-a5e3-739e08a58d33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193137628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3193137628
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1130432167
Short name T203
Test name
Test status
Simulation time 14501501 ps
CPU time 0.69 seconds
Started Jan 17 03:52:46 PM PST 24
Finished Jan 17 03:52:50 PM PST 24
Peak memory 202180 kb
Host smart-30e6aff3-8c95-42ab-98d8-10b6a10ab0d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130432167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.1130432167
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3000578254
Short name T163
Test name
Test status
Simulation time 218113431 ps
CPU time 1.17 seconds
Started Jan 17 03:52:47 PM PST 24
Finished Jan 17 03:52:51 PM PST 24
Peak memory 202404 kb
Host smart-d5b6f40d-571e-4605-80d8-60d980986a60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000578254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.3000578254
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2001884520
Short name T101
Test name
Test status
Simulation time 48625264 ps
CPU time 0.73 seconds
Started Jan 17 03:52:44 PM PST 24
Finished Jan 17 03:52:47 PM PST 24
Peak memory 201352 kb
Host smart-135d8722-100c-40a6-88f2-1e88e30c064b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001884520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2001884520
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4257496961
Short name T171
Test name
Test status
Simulation time 3381694018 ps
CPU time 5.41 seconds
Started Jan 17 03:52:47 PM PST 24
Finished Jan 17 03:52:56 PM PST 24
Peak memory 202472 kb
Host smart-dd115f6d-1ab7-4b77-9ee5-45edd4c7030b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257496961 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.4257496961
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.925164534
Short name T220
Test name
Test status
Simulation time 32652012 ps
CPU time 0.65 seconds
Started Jan 17 03:52:44 PM PST 24
Finished Jan 17 03:52:47 PM PST 24
Peak memory 202216 kb
Host smart-04f12bec-63df-4011-896b-77159fd50e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925164534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_csr_rw.925164534
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2962592072
Short name T219
Test name
Test status
Simulation time 14203700849 ps
CPU time 60.07 seconds
Started Jan 17 03:52:38 PM PST 24
Finished Jan 17 03:53:41 PM PST 24
Peak memory 202560 kb
Host smart-f2e30c04-d999-4040-9749-ded785f042f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962592072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.2962592072
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2228739706
Short name T118
Test name
Test status
Simulation time 38545123 ps
CPU time 0.65 seconds
Started Jan 17 03:52:45 PM PST 24
Finished Jan 17 03:52:50 PM PST 24
Peak memory 201588 kb
Host smart-9dfd788f-92bc-429b-9736-70cd9a91888c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228739706 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.2228739706
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1297009468
Short name T169
Test name
Test status
Simulation time 136836535 ps
CPU time 1.94 seconds
Started Jan 17 03:52:43 PM PST 24
Finished Jan 17 03:52:46 PM PST 24
Peak memory 202480 kb
Host smart-3e916b4d-68b9-43e8-a19f-dde6c62bc984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297009468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.1297009468
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2668191714
Short name T54
Test name
Test status
Simulation time 206815746 ps
CPU time 2.11 seconds
Started Jan 17 03:52:43 PM PST 24
Finished Jan 17 03:52:46 PM PST 24
Peak memory 202464 kb
Host smart-646ff09c-a079-42e5-923f-d85df9572b76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668191714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2668191714
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3411721266
Short name T195
Test name
Test status
Simulation time 40485151 ps
CPU time 0.75 seconds
Started Jan 17 03:52:54 PM PST 24
Finished Jan 17 03:52:55 PM PST 24
Peak memory 202232 kb
Host smart-fc9c0861-63b3-4503-b8b0-af0151372807
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411721266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.3411721266
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1663093945
Short name T104
Test name
Test status
Simulation time 351306267 ps
CPU time 1.38 seconds
Started Jan 17 03:52:48 PM PST 24
Finished Jan 17 03:52:52 PM PST 24
Peak memory 202296 kb
Host smart-6ab5cb88-fe81-456a-aa73-dada1c53d76b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663093945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1663093945
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3603665577
Short name T206
Test name
Test status
Simulation time 32178448 ps
CPU time 0.67 seconds
Started Jan 17 03:52:55 PM PST 24
Finished Jan 17 03:52:56 PM PST 24
Peak memory 201488 kb
Host smart-58cb859b-8517-495e-a1a6-d1bea95f1116
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603665577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.3603665577
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1420232448
Short name T217
Test name
Test status
Simulation time 366313168 ps
CPU time 12.92 seconds
Started Jan 17 03:52:55 PM PST 24
Finished Jan 17 03:53:09 PM PST 24
Peak memory 202460 kb
Host smart-f853ac89-33eb-42a7-bc87-76bbf906fa68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420232448 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1420232448
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3677373175
Short name T186
Test name
Test status
Simulation time 30617816 ps
CPU time 0.63 seconds
Started Jan 17 03:52:50 PM PST 24
Finished Jan 17 03:52:52 PM PST 24
Peak memory 201364 kb
Host smart-8736be43-2eee-490f-bd0f-bd1ee37dbe69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677373175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.3677373175
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3135218620
Short name T86
Test name
Test status
Simulation time 16760208250 ps
CPU time 147.21 seconds
Started Jan 17 03:52:47 PM PST 24
Finished Jan 17 03:55:17 PM PST 24
Peak memory 210776 kb
Host smart-eb0edc84-3844-4a21-b92d-32880bdb7ec6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135218620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3135218620
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1894697666
Short name T68
Test name
Test status
Simulation time 84193866 ps
CPU time 0.77 seconds
Started Jan 17 03:52:55 PM PST 24
Finished Jan 17 03:52:56 PM PST 24
Peak memory 202252 kb
Host smart-2c50d121-e88c-4836-a01b-b65bed0b4c4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894697666 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1894697666
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3696421566
Short name T223
Test name
Test status
Simulation time 143023749 ps
CPU time 4.23 seconds
Started Jan 17 03:52:45 PM PST 24
Finished Jan 17 03:52:51 PM PST 24
Peak memory 202444 kb
Host smart-b959a58b-9e5d-4508-9b45-b4050dc628ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696421566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.3696421566
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.464546752
Short name T135
Test name
Test status
Simulation time 106398090 ps
CPU time 1.42 seconds
Started Jan 17 03:52:47 PM PST 24
Finished Jan 17 03:52:52 PM PST 24
Peak memory 202464 kb
Host smart-a99fd5c7-7798-413e-9713-e6078c130123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464546752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.sram_ctrl_tl_intg_err.464546752
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.48501555
Short name T69
Test name
Test status
Simulation time 15512635 ps
CPU time 0.67 seconds
Started Jan 17 03:52:58 PM PST 24
Finished Jan 17 03:53:00 PM PST 24
Peak memory 201400 kb
Host smart-9cf99225-0c20-4072-b98f-10eeb03e3ecb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48501555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_aliasing.48501555
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3356704425
Short name T100
Test name
Test status
Simulation time 284728757 ps
CPU time 1.36 seconds
Started Jan 17 03:52:52 PM PST 24
Finished Jan 17 03:52:54 PM PST 24
Peak memory 202340 kb
Host smart-47a21644-dad0-4c99-9bbd-a4a74eb8e2a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356704425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3356704425
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3334378608
Short name T165
Test name
Test status
Simulation time 13827059 ps
CPU time 0.64 seconds
Started Jan 17 03:52:51 PM PST 24
Finished Jan 17 03:52:52 PM PST 24
Peak memory 201416 kb
Host smart-c9ffae59-a203-4195-bc45-6f2e86b46ef1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334378608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3334378608
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2244160361
Short name T181
Test name
Test status
Simulation time 347967726 ps
CPU time 6.09 seconds
Started Jan 17 03:52:59 PM PST 24
Finished Jan 17 03:53:08 PM PST 24
Peak memory 210756 kb
Host smart-5b202f7d-41a6-44af-9aeb-28101c380567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244160361 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2244160361
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3609924168
Short name T89
Test name
Test status
Simulation time 32287708 ps
CPU time 0.7 seconds
Started Jan 17 03:52:55 PM PST 24
Finished Jan 17 03:52:56 PM PST 24
Peak memory 202112 kb
Host smart-e22038af-d032-492c-b3a5-5bc75f409c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609924168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3609924168
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2308372168
Short name T88
Test name
Test status
Simulation time 3792757825 ps
CPU time 133.91 seconds
Started Jan 17 03:52:53 PM PST 24
Finished Jan 17 03:55:08 PM PST 24
Peak memory 202556 kb
Host smart-3acb3b08-e336-408b-b0eb-951b4c1e68c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308372168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2308372168
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3826223746
Short name T196
Test name
Test status
Simulation time 65288736 ps
CPU time 0.72 seconds
Started Jan 17 03:53:03 PM PST 24
Finished Jan 17 03:53:05 PM PST 24
Peak memory 201648 kb
Host smart-ea911e72-baea-4dd5-9d48-4c365ba6d65d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826223746 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3826223746
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4189222296
Short name T112
Test name
Test status
Simulation time 79108931 ps
CPU time 2.23 seconds
Started Jan 17 03:52:55 PM PST 24
Finished Jan 17 03:52:58 PM PST 24
Peak memory 210568 kb
Host smart-b08d8f07-929e-4caf-91f5-cdb3748fb142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189222296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.4189222296
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1116277399
Short name T134
Test name
Test status
Simulation time 471892351 ps
CPU time 1.78 seconds
Started Jan 17 03:52:52 PM PST 24
Finished Jan 17 03:52:55 PM PST 24
Peak memory 202424 kb
Host smart-7585bb6f-5c57-4cb4-87db-4caa78226517
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116277399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.1116277399
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2649211529
Short name T59
Test name
Test status
Simulation time 1415796049 ps
CPU time 13.03 seconds
Started Jan 17 03:53:00 PM PST 24
Finished Jan 17 03:53:16 PM PST 24
Peak memory 210856 kb
Host smart-babcee92-6a0b-4b3f-99a9-319a651e53c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649211529 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2649211529
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3530964598
Short name T177
Test name
Test status
Simulation time 16559533 ps
CPU time 0.64 seconds
Started Jan 17 03:52:59 PM PST 24
Finished Jan 17 03:53:02 PM PST 24
Peak memory 202168 kb
Host smart-8a071c09-fc11-41a7-913f-0e4bfe7d76bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530964598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3530964598
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1415107959
Short name T77
Test name
Test status
Simulation time 7389675294 ps
CPU time 270.16 seconds
Started Jan 17 03:53:03 PM PST 24
Finished Jan 17 03:57:34 PM PST 24
Peak memory 202544 kb
Host smart-10894447-255d-49ff-ac15-1272902b3de2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415107959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1415107959
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.290727019
Short name T178
Test name
Test status
Simulation time 22387692 ps
CPU time 0.75 seconds
Started Jan 17 03:53:00 PM PST 24
Finished Jan 17 03:53:03 PM PST 24
Peak memory 202320 kb
Host smart-4791cd08-3ec1-41a0-96ed-1544106a875c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290727019 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.290727019
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1427782675
Short name T61
Test name
Test status
Simulation time 28496502 ps
CPU time 2.08 seconds
Started Jan 17 03:53:00 PM PST 24
Finished Jan 17 03:53:05 PM PST 24
Peak memory 202480 kb
Host smart-f25482bd-5256-4214-b7fe-80fb71aa1cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427782675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.1427782675
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3733549113
Short name T132
Test name
Test status
Simulation time 199281837 ps
CPU time 2.4 seconds
Started Jan 17 03:52:59 PM PST 24
Finished Jan 17 03:53:04 PM PST 24
Peak memory 202456 kb
Host smart-f5b13eb6-1fd5-48f6-a359-08cc34e39d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733549113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.3733549113
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.464190390
Short name T167
Test name
Test status
Simulation time 1913072167 ps
CPU time 5.16 seconds
Started Jan 17 03:53:04 PM PST 24
Finished Jan 17 03:53:19 PM PST 24
Peak memory 202568 kb
Host smart-0955d140-d906-4428-96b9-17a649494697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464190390 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.464190390
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1418805174
Short name T122
Test name
Test status
Simulation time 18626233 ps
CPU time 0.61 seconds
Started Jan 17 03:52:57 PM PST 24
Finished Jan 17 03:52:59 PM PST 24
Peak memory 202092 kb
Host smart-e1bb5945-8664-41a0-8472-529307f7ab4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418805174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.1418805174
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3020877586
Short name T84
Test name
Test status
Simulation time 8109877127 ps
CPU time 107.69 seconds
Started Jan 17 03:52:58 PM PST 24
Finished Jan 17 03:54:47 PM PST 24
Peak memory 202560 kb
Host smart-bb1b881e-4f28-4d0b-b1a6-288a34cd2751
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020877586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3020877586
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.935357363
Short name T230
Test name
Test status
Simulation time 20052960 ps
CPU time 0.66 seconds
Started Jan 17 03:53:05 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 202288 kb
Host smart-5fb51194-432c-4aea-99a7-e8794dbccc3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935357363 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.935357363
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.31442805
Short name T194
Test name
Test status
Simulation time 108274939 ps
CPU time 3.84 seconds
Started Jan 17 03:53:01 PM PST 24
Finished Jan 17 03:53:07 PM PST 24
Peak memory 202492 kb
Host smart-07ec81c5-3997-4670-84d8-dfa9fd09757a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31442805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_tl_errors.31442805
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1098617088
Short name T185
Test name
Test status
Simulation time 1437683844 ps
CPU time 6.41 seconds
Started Jan 17 03:53:04 PM PST 24
Finished Jan 17 03:53:11 PM PST 24
Peak memory 202552 kb
Host smart-dc569778-a666-4e02-98b6-cad2181591ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098617088 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1098617088
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.593139860
Short name T227
Test name
Test status
Simulation time 46505076 ps
CPU time 0.65 seconds
Started Jan 17 03:53:03 PM PST 24
Finished Jan 17 03:53:05 PM PST 24
Peak memory 201772 kb
Host smart-a1a4381a-34c8-4215-98cc-2ef52e5a0684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593139860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_csr_rw.593139860
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3747623953
Short name T193
Test name
Test status
Simulation time 4193568091 ps
CPU time 50.98 seconds
Started Jan 17 03:53:03 PM PST 24
Finished Jan 17 03:53:55 PM PST 24
Peak memory 202464 kb
Host smart-087beb90-223d-484c-8caa-b313c6026dac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747623953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3747623953
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1154335250
Short name T99
Test name
Test status
Simulation time 54628268 ps
CPU time 0.67 seconds
Started Jan 17 03:53:03 PM PST 24
Finished Jan 17 03:53:05 PM PST 24
Peak memory 202160 kb
Host smart-25ddfbe9-d60f-401b-ae50-c0be46cd04cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154335250 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1154335250
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4096712959
Short name T168
Test name
Test status
Simulation time 145706630 ps
CPU time 5.08 seconds
Started Jan 17 03:53:06 PM PST 24
Finished Jan 17 03:53:19 PM PST 24
Peak memory 202452 kb
Host smart-cf803044-3304-4fcb-abbc-d6e63763ae08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096712959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.4096712959
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1621197995
Short name T210
Test name
Test status
Simulation time 411167772 ps
CPU time 2.69 seconds
Started Jan 17 03:53:07 PM PST 24
Finished Jan 17 03:53:17 PM PST 24
Peak memory 202456 kb
Host smart-5d1f95b0-0107-43fb-8dad-624e7fa26d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621197995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.1621197995
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1274136936
Short name T192
Test name
Test status
Simulation time 445041144 ps
CPU time 5.76 seconds
Started Jan 17 03:53:08 PM PST 24
Finished Jan 17 03:53:20 PM PST 24
Peak memory 202548 kb
Host smart-b5dd798a-fcde-43de-8611-37e5d46999c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274136936 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1274136936
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3554053657
Short name T94
Test name
Test status
Simulation time 32312087 ps
CPU time 0.65 seconds
Started Jan 17 03:53:08 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 201480 kb
Host smart-80ffa67a-019c-48de-8584-72a82ac22bdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554053657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.3554053657
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4222804199
Short name T72
Test name
Test status
Simulation time 39454903 ps
CPU time 0.72 seconds
Started Jan 17 03:53:07 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 202084 kb
Host smart-16b4a8cc-502b-4150-93ea-29918f767eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222804199 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.4222804199
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2076490308
Short name T62
Test name
Test status
Simulation time 497000982 ps
CPU time 4.32 seconds
Started Jan 17 03:53:09 PM PST 24
Finished Jan 17 03:53:18 PM PST 24
Peak memory 202432 kb
Host smart-11423764-b8f7-48f6-a196-2d203dae6d84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076490308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.2076490308
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.613666706
Short name T187
Test name
Test status
Simulation time 389383270 ps
CPU time 5.1 seconds
Started Jan 17 03:53:13 PM PST 24
Finished Jan 17 03:53:19 PM PST 24
Peak memory 202384 kb
Host smart-5f719049-2b22-4a5f-a2af-a8a2de74e933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613666706 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.613666706
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1664372521
Short name T191
Test name
Test status
Simulation time 17876303 ps
CPU time 0.64 seconds
Started Jan 17 03:53:09 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 201424 kb
Host smart-0147e0f0-4936-4c51-83b6-2b67f2f288d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664372521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1664372521
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2698107599
Short name T85
Test name
Test status
Simulation time 41297655350 ps
CPU time 306.36 seconds
Started Jan 17 03:53:09 PM PST 24
Finished Jan 17 03:58:21 PM PST 24
Peak memory 210708 kb
Host smart-69a584bc-6bf2-4923-a908-09dc71592437
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698107599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2698107599
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3317691894
Short name T166
Test name
Test status
Simulation time 91583457 ps
CPU time 0.69 seconds
Started Jan 17 03:53:08 PM PST 24
Finished Jan 17 03:53:15 PM PST 24
Peak memory 202216 kb
Host smart-1ad8041b-8723-4104-8001-6ec5bb8fa44b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317691894 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3317691894
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.153557280
Short name T207
Test name
Test status
Simulation time 23866156 ps
CPU time 2.14 seconds
Started Jan 17 03:53:10 PM PST 24
Finished Jan 17 03:53:16 PM PST 24
Peak memory 202496 kb
Host smart-39005658-fc0b-4532-b5ec-3744ca630a38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153557280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_tl_errors.153557280
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1955470390
Short name T402
Test name
Test status
Simulation time 9387263083 ps
CPU time 1062.28 seconds
Started Jan 17 02:32:12 PM PST 24
Finished Jan 17 02:49:56 PM PST 24
Peak memory 376000 kb
Host smart-7d052009-08cc-49c6-af26-e6c3510023de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955470390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1955470390
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.383921829
Short name T575
Test name
Test status
Simulation time 13546774 ps
CPU time 0.63 seconds
Started Jan 17 02:33:18 PM PST 24
Finished Jan 17 02:33:21 PM PST 24
Peak memory 201856 kb
Host smart-ab4f253b-b68b-41eb-8525-3eff48dc0202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383921829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.383921829
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.2208646122
Short name T728
Test name
Test status
Simulation time 792807489603 ps
CPU time 2837.18 seconds
Started Jan 17 02:32:07 PM PST 24
Finished Jan 17 03:19:25 PM PST 24
Peak memory 202136 kb
Host smart-8fd58438-2f08-4e40-8283-7012d2798009
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208646122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
2208646122
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.3153043083
Short name T271
Test name
Test status
Simulation time 59266350630 ps
CPU time 454.82 seconds
Started Jan 17 02:32:13 PM PST 24
Finished Jan 17 02:39:49 PM PST 24
Peak memory 371884 kb
Host smart-d8852fc6-85b8-4731-9780-67a069fa938a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153043083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.3153043083
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.1688058161
Short name T656
Test name
Test status
Simulation time 784317109 ps
CPU time 119.1 seconds
Started Jan 17 02:32:13 PM PST 24
Finished Jan 17 02:34:13 PM PST 24
Peak memory 341236 kb
Host smart-68352d12-4b28-47dd-a9b8-93c6f0bf117e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688058161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.1688058161
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3613817657
Short name T426
Test name
Test status
Simulation time 10569949336 ps
CPU time 153.11 seconds
Started Jan 17 02:32:12 PM PST 24
Finished Jan 17 02:34:46 PM PST 24
Peak memory 218528 kb
Host smart-ec1c8b86-a744-4da1-a8be-70b5b772c5fa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613817657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.3613817657
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2101285111
Short name T822
Test name
Test status
Simulation time 28642996633 ps
CPU time 139.74 seconds
Started Jan 17 02:32:11 PM PST 24
Finished Jan 17 02:34:32 PM PST 24
Peak memory 202100 kb
Host smart-3c01768d-4ffe-4836-8cda-45c802e36cb1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101285111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2101285111
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.1065246475
Short name T348
Test name
Test status
Simulation time 35110573929 ps
CPU time 1681.88 seconds
Started Jan 17 02:32:13 PM PST 24
Finished Jan 17 03:00:16 PM PST 24
Peak memory 379128 kb
Host smart-b0a6143d-d3b5-447d-9164-4b29e161f363
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065246475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.1065246475
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.1528764046
Short name T883
Test name
Test status
Simulation time 1527395695 ps
CPU time 17.25 seconds
Started Jan 17 02:32:06 PM PST 24
Finished Jan 17 02:32:24 PM PST 24
Peak memory 202084 kb
Host smart-36a1e19e-25e4-443a-b0a7-6af6f4c42076
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528764046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.1528764046
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1764842303
Short name T670
Test name
Test status
Simulation time 3239214024 ps
CPU time 216.93 seconds
Started Jan 17 02:32:08 PM PST 24
Finished Jan 17 02:35:46 PM PST 24
Peak memory 202152 kb
Host smart-2375eaaa-4836-4062-a301-55b73bdb5869
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764842303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1764842303
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.844835020
Short name T609
Test name
Test status
Simulation time 1890476700 ps
CPU time 14.71 seconds
Started Jan 17 02:32:22 PM PST 24
Finished Jan 17 02:32:38 PM PST 24
Peak memory 202412 kb
Host smart-244cfe60-06d2-4958-9282-4c5541269432
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844835020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.844835020
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2631827747
Short name T628
Test name
Test status
Simulation time 2307845172 ps
CPU time 74.83 seconds
Started Jan 17 02:32:12 PM PST 24
Finished Jan 17 02:33:27 PM PST 24
Peak memory 314688 kb
Host smart-df897339-08cc-4ed1-b3a0-58bb24ce3704
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631827747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2631827747
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.2938787222
Short name T432
Test name
Test status
Simulation time 54162273585 ps
CPU time 3194.18 seconds
Started Jan 17 02:32:12 PM PST 24
Finished Jan 17 03:25:28 PM PST 24
Peak memory 380144 kb
Host smart-a1c80deb-4438-4f9d-8b1c-ba8c8607413f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938787222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.2938787222
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.170446454
Short name T939
Test name
Test status
Simulation time 4231455995 ps
CPU time 2840.87 seconds
Started Jan 17 02:32:14 PM PST 24
Finished Jan 17 03:19:36 PM PST 24
Peak memory 699204 kb
Host smart-8260b5d9-c7e3-4f12-ba10-ef29f13246e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=170446454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.170446454
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1230141864
Short name T819
Test name
Test status
Simulation time 5043537873 ps
CPU time 396.52 seconds
Started Jan 17 02:32:08 PM PST 24
Finished Jan 17 02:38:46 PM PST 24
Peak memory 202084 kb
Host smart-8a2d7cb2-9a1e-45fe-a6c3-09477add0da2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230141864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.1230141864
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3156235280
Short name T504
Test name
Test status
Simulation time 698712719 ps
CPU time 27.46 seconds
Started Jan 17 02:32:10 PM PST 24
Finished Jan 17 02:32:38 PM PST 24
Peak memory 210364 kb
Host smart-8daafb0e-d99a-4bb6-8814-8fb26be347ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156235280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3156235280
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1622911137
Short name T236
Test name
Test status
Simulation time 27453014884 ps
CPU time 550.78 seconds
Started Jan 17 02:32:37 PM PST 24
Finished Jan 17 02:41:49 PM PST 24
Peak memory 379080 kb
Host smart-b913c30d-c4b0-465f-b43f-c2743e637c41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622911137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.1622911137
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3680182787
Short name T705
Test name
Test status
Simulation time 26237230 ps
CPU time 0.64 seconds
Started Jan 17 02:33:37 PM PST 24
Finished Jan 17 02:33:40 PM PST 24
Peak memory 201844 kb
Host smart-64d24f05-1131-4db5-a65e-4b779d4cf915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680182787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.3680182787
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.3683673391
Short name T770
Test name
Test status
Simulation time 351959739422 ps
CPU time 2889.88 seconds
Started Jan 17 02:32:40 PM PST 24
Finished Jan 17 03:20:52 PM PST 24
Peak memory 202220 kb
Host smart-6fbfdca8-cbcb-4203-81ef-9b9bb5856129
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683673391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
3683673391
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.2552579961
Short name T722
Test name
Test status
Simulation time 7557526939 ps
CPU time 665.75 seconds
Started Jan 17 02:32:57 PM PST 24
Finished Jan 17 02:44:03 PM PST 24
Peak memory 356536 kb
Host smart-c4bc1419-d42a-4a8e-bf78-8b990ae4651d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552579961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.2552579961
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1880073017
Short name T800
Test name
Test status
Simulation time 3138310663 ps
CPU time 138.18 seconds
Started Jan 17 02:32:21 PM PST 24
Finished Jan 17 02:34:40 PM PST 24
Peak memory 341680 kb
Host smart-016d0970-2bc3-45d8-be14-b599bf92c407
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880073017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1880073017
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.876530746
Short name T528
Test name
Test status
Simulation time 3965789192 ps
CPU time 78.54 seconds
Started Jan 17 02:32:48 PM PST 24
Finished Jan 17 02:34:09 PM PST 24
Peak memory 211152 kb
Host smart-0139e9e9-61aa-40d0-b2df-1161bb82a572
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876530746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_mem_partial_access.876530746
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.2259970462
Short name T876
Test name
Test status
Simulation time 2021926825 ps
CPU time 128.58 seconds
Started Jan 17 02:32:16 PM PST 24
Finished Jan 17 02:34:26 PM PST 24
Peak memory 202016 kb
Host smart-ca9e816d-cc86-4843-bd4f-ddeb55807dd7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259970462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.2259970462
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.1727921631
Short name T908
Test name
Test status
Simulation time 31195060763 ps
CPU time 2037.99 seconds
Started Jan 17 02:32:27 PM PST 24
Finished Jan 17 03:06:28 PM PST 24
Peak memory 378064 kb
Host smart-82e43836-2bd0-4ca0-825f-1e015dc69da5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727921631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.1727921631
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.1485917387
Short name T833
Test name
Test status
Simulation time 1470878709 ps
CPU time 28.02 seconds
Started Jan 17 02:33:18 PM PST 24
Finished Jan 17 02:33:48 PM PST 24
Peak memory 202012 kb
Host smart-73c99f04-97ae-4b90-96f3-7e9c16bf67fd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485917387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.1485917387
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4239709931
Short name T344
Test name
Test status
Simulation time 8905550898 ps
CPU time 543.07 seconds
Started Jan 17 02:33:08 PM PST 24
Finished Jan 17 02:42:14 PM PST 24
Peak memory 202172 kb
Host smart-ed43d334-f47d-4cfe-ba12-d9e4400736ec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239709931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.4239709931
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.3073686511
Short name T963
Test name
Test status
Simulation time 369542171 ps
CPU time 6.51 seconds
Started Jan 17 02:32:23 PM PST 24
Finished Jan 17 02:32:31 PM PST 24
Peak memory 202404 kb
Host smart-c3838041-1442-4202-a665-644b6577f781
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073686511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3073686511
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.595484178
Short name T663
Test name
Test status
Simulation time 11907125380 ps
CPU time 582.69 seconds
Started Jan 17 02:32:20 PM PST 24
Finished Jan 17 02:42:04 PM PST 24
Peak memory 374984 kb
Host smart-dc801232-1d21-4657-a702-c9fcc75e355b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595484178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.595484178
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.72501594
Short name T40
Test name
Test status
Simulation time 371408349 ps
CPU time 2.46 seconds
Started Jan 17 02:32:36 PM PST 24
Finished Jan 17 02:32:40 PM PST 24
Peak memory 221056 kb
Host smart-b6ae6661-4101-40ae-9291-bcdba9ae31db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72501594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_sec_cm.72501594
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.1481726814
Short name T294
Test name
Test status
Simulation time 4947107731 ps
CPU time 96.78 seconds
Started Jan 17 02:33:24 PM PST 24
Finished Jan 17 02:35:01 PM PST 24
Peak memory 322836 kb
Host smart-37385f30-fa5e-4a3f-ac85-9a0ac8bd72e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481726814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1481726814
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3157129268
Short name T409
Test name
Test status
Simulation time 1673888793 ps
CPU time 6094.58 seconds
Started Jan 17 02:32:18 PM PST 24
Finished Jan 17 04:13:53 PM PST 24
Peak memory 696120 kb
Host smart-4d8b5e22-8b17-43aa-9953-9c8d2ef16d14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3157129268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3157129268
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1509760139
Short name T667
Test name
Test status
Simulation time 19029673625 ps
CPU time 327.71 seconds
Started Jan 17 02:32:48 PM PST 24
Finished Jan 17 02:38:18 PM PST 24
Peak memory 202192 kb
Host smart-56df0563-ddc0-4d9e-8b54-cc4d714c7fd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509760139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.1509760139
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2395868774
Short name T396
Test name
Test status
Simulation time 1404172788 ps
CPU time 31.49 seconds
Started Jan 17 02:32:14 PM PST 24
Finished Jan 17 02:32:47 PM PST 24
Peak memory 234872 kb
Host smart-d8d93db5-8f75-4c17-997e-172814ccb968
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395868774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.2395868774
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2139634542
Short name T620
Test name
Test status
Simulation time 7601140514 ps
CPU time 1605.94 seconds
Started Jan 17 02:34:44 PM PST 24
Finished Jan 17 03:01:31 PM PST 24
Peak memory 380084 kb
Host smart-d5777561-816e-457a-b80a-df79bc012b75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139634542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2139634542
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.3952957846
Short name T11
Test name
Test status
Simulation time 18031106 ps
CPU time 0.64 seconds
Started Jan 17 02:34:00 PM PST 24
Finished Jan 17 02:34:02 PM PST 24
Peak memory 201852 kb
Host smart-ec30edee-40d9-4b5d-9fef-dcb04a51890a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952957846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.3952957846
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.4261623510
Short name T768
Test name
Test status
Simulation time 76502979570 ps
CPU time 1136.01 seconds
Started Jan 17 02:35:03 PM PST 24
Finished Jan 17 02:54:01 PM PST 24
Peak memory 202160 kb
Host smart-32be38ca-0309-4e5a-a4e7-4158c5eedede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261623510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.4261623510
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.3634531980
Short name T301
Test name
Test status
Simulation time 60834997455 ps
CPU time 1068.21 seconds
Started Jan 17 02:34:30 PM PST 24
Finished Jan 17 02:52:22 PM PST 24
Peak memory 377064 kb
Host smart-207fc8ae-87cf-4419-9bb3-387bc62d1493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634531980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.3634531980
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.3735433778
Short name T919
Test name
Test status
Simulation time 47254544302 ps
CPU time 290.31 seconds
Started Jan 17 02:36:08 PM PST 24
Finished Jan 17 02:40:59 PM PST 24
Peak memory 210416 kb
Host smart-05498253-676a-4ea9-9744-eeedad1da7ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735433778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.3735433778
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3363660139
Short name T844
Test name
Test status
Simulation time 696918266 ps
CPU time 25.32 seconds
Started Jan 17 02:37:39 PM PST 24
Finished Jan 17 02:38:08 PM PST 24
Peak memory 209888 kb
Host smart-62781d20-5457-4364-915e-b4e7d8b81ffc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363660139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3363660139
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4128153389
Short name T550
Test name
Test status
Simulation time 3944820950 ps
CPU time 73.34 seconds
Started Jan 17 02:35:49 PM PST 24
Finished Jan 17 02:37:03 PM PST 24
Peak memory 211108 kb
Host smart-dcf0134c-27d7-4a13-9247-ee267d202600
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128153389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.4128153389
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.4284966623
Short name T785
Test name
Test status
Simulation time 15765427377 ps
CPU time 252.23 seconds
Started Jan 17 02:34:45 PM PST 24
Finished Jan 17 02:38:58 PM PST 24
Peak memory 202572 kb
Host smart-5a79ba4a-eba8-43aa-bd1f-1a25ef5ee9c2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284966623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.4284966623
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.1700958920
Short name T146
Test name
Test status
Simulation time 30052665030 ps
CPU time 824.41 seconds
Started Jan 17 02:37:37 PM PST 24
Finished Jan 17 02:51:27 PM PST 24
Peak memory 376016 kb
Host smart-5f59ffc0-89da-4b25-b46c-9580f02edaa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700958920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.1700958920
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2962748846
Short name T652
Test name
Test status
Simulation time 676362071 ps
CPU time 32.33 seconds
Started Jan 17 02:34:49 PM PST 24
Finished Jan 17 02:35:23 PM PST 24
Peak memory 273444 kb
Host smart-9a6c5c7c-e4a5-4aef-b687-2933a2e97fb0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962748846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2962748846
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1888554378
Short name T469
Test name
Test status
Simulation time 6778972680 ps
CPU time 201.73 seconds
Started Jan 17 02:38:02 PM PST 24
Finished Jan 17 02:41:29 PM PST 24
Peak memory 202000 kb
Host smart-5a768e05-c4e5-439c-9051-f5e250359fa9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888554378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.1888554378
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.2620532358
Short name T669
Test name
Test status
Simulation time 3729382253 ps
CPU time 7.11 seconds
Started Jan 17 02:33:53 PM PST 24
Finished Jan 17 02:34:00 PM PST 24
Peak memory 202512 kb
Host smart-2a65fe69-e79f-46e1-9001-56e00347e594
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620532358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2620532358
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.3341889831
Short name T600
Test name
Test status
Simulation time 14072194126 ps
CPU time 1263.1 seconds
Started Jan 17 02:35:10 PM PST 24
Finished Jan 17 02:56:18 PM PST 24
Peak memory 379004 kb
Host smart-a48ea471-4711-4dc7-a69d-ef751a130fbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341889831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3341889831
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.1797193901
Short name T875
Test name
Test status
Simulation time 985186817 ps
CPU time 32.46 seconds
Started Jan 17 02:35:17 PM PST 24
Finished Jan 17 02:35:50 PM PST 24
Peak memory 268612 kb
Host smart-3ed95880-ce2a-424a-b615-14a19850936e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797193901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1797193901
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.3079018540
Short name T680
Test name
Test status
Simulation time 61956887010 ps
CPU time 6269.64 seconds
Started Jan 17 02:35:49 PM PST 24
Finished Jan 17 04:20:20 PM PST 24
Peak memory 381144 kb
Host smart-611309a7-7346-40e1-bc4b-1f9c753b8f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079018540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.3079018540
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1022164289
Short name T388
Test name
Test status
Simulation time 921181554 ps
CPU time 5659.94 seconds
Started Jan 17 02:33:51 PM PST 24
Finished Jan 17 04:08:12 PM PST 24
Peak memory 619756 kb
Host smart-d10b0d82-307a-4e14-95fb-caabf7269bce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1022164289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1022164289
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3782685531
Short name T262
Test name
Test status
Simulation time 2762238511 ps
CPU time 214.49 seconds
Started Jan 17 02:35:49 PM PST 24
Finished Jan 17 02:39:24 PM PST 24
Peak memory 202176 kb
Host smart-0ebf896c-3569-4df8-96ae-2051144cf730
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782685531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.3782685531
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.502700146
Short name T428
Test name
Test status
Simulation time 786363926 ps
CPU time 87.69 seconds
Started Jan 17 02:37:40 PM PST 24
Finished Jan 17 02:39:10 PM PST 24
Peak memory 344496 kb
Host smart-0cd06b69-29f1-42da-b9c3-d0102f25ab96
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502700146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.502700146
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1582083038
Short name T614
Test name
Test status
Simulation time 26594432278 ps
CPU time 1728.83 seconds
Started Jan 17 02:34:11 PM PST 24
Finished Jan 17 03:03:01 PM PST 24
Peak memory 379140 kb
Host smart-ccd15386-a6d1-4acf-8870-db30d8afbc10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582083038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.1582083038
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.2406235463
Short name T869
Test name
Test status
Simulation time 17527771 ps
CPU time 0.6 seconds
Started Jan 17 02:38:19 PM PST 24
Finished Jan 17 02:38:21 PM PST 24
Peak memory 201244 kb
Host smart-53afacdb-b2f1-4816-aa81-c5a2c61dace7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406235463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.2406235463
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.1291267918
Short name T493
Test name
Test status
Simulation time 45290531656 ps
CPU time 676.84 seconds
Started Jan 17 02:34:30 PM PST 24
Finished Jan 17 02:45:50 PM PST 24
Peak memory 202100 kb
Host smart-bd23e70d-6aae-40db-9fcf-d7319dd1e5e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291267918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.1291267918
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.1126039536
Short name T653
Test name
Test status
Simulation time 32748110753 ps
CPU time 989.44 seconds
Started Jan 17 02:34:14 PM PST 24
Finished Jan 17 02:50:44 PM PST 24
Peak memory 378184 kb
Host smart-2e8b8596-b77c-48f8-9190-126e0cdee7a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126039536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.1126039536
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.48906448
Short name T153
Test name
Test status
Simulation time 3063918009 ps
CPU time 144.74 seconds
Started Jan 17 02:34:06 PM PST 24
Finished Jan 17 02:36:32 PM PST 24
Peak memory 368944 kb
Host smart-18efc03a-17e7-4a21-9773-bcbd4132b598
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48906448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_max_throughput.48906448
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3076626176
Short name T349
Test name
Test status
Simulation time 15826998527 ps
CPU time 76.32 seconds
Started Jan 17 02:34:19 PM PST 24
Finished Jan 17 02:35:36 PM PST 24
Peak memory 211488 kb
Host smart-2c391955-a08d-429f-8402-fb1429289528
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076626176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.3076626176
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.999411212
Short name T423
Test name
Test status
Simulation time 15767231433 ps
CPU time 261.19 seconds
Started Jan 17 02:36:27 PM PST 24
Finished Jan 17 02:40:49 PM PST 24
Peak memory 202256 kb
Host smart-a3783823-fe58-4989-8f18-d83180e85fd8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999411212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.999411212
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.1519579329
Short name T446
Test name
Test status
Simulation time 95523256235 ps
CPU time 1512.01 seconds
Started Jan 17 02:34:10 PM PST 24
Finished Jan 17 02:59:23 PM PST 24
Peak memory 381116 kb
Host smart-bec64c2b-d938-4df6-8f7c-01e29bcf5736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519579329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.1519579329
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.2270933769
Short name T326
Test name
Test status
Simulation time 1914227024 ps
CPU time 17.25 seconds
Started Jan 17 02:37:41 PM PST 24
Finished Jan 17 02:38:00 PM PST 24
Peak memory 219952 kb
Host smart-72fe83b5-1839-48c1-9d47-76fa0a3b649d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270933769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.2270933769
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.984458549
Short name T911
Test name
Test status
Simulation time 51491938646 ps
CPU time 361.16 seconds
Started Jan 17 02:34:07 PM PST 24
Finished Jan 17 02:40:09 PM PST 24
Peak memory 202240 kb
Host smart-37e63cbf-b80d-402f-a0a7-a6e9db16df9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984458549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.984458549
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.3912209495
Short name T405
Test name
Test status
Simulation time 683894734 ps
CPU time 6.2 seconds
Started Jan 17 02:37:41 PM PST 24
Finished Jan 17 02:37:49 PM PST 24
Peak memory 201880 kb
Host smart-d26b20ff-12e1-4204-8de0-5761854a2812
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912209495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3912209495
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.4019553326
Short name T34
Test name
Test status
Simulation time 11468549735 ps
CPU time 176.68 seconds
Started Jan 17 02:34:17 PM PST 24
Finished Jan 17 02:37:14 PM PST 24
Peak memory 370856 kb
Host smart-eac6e55c-1230-4144-a6c3-df514bad0204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019553326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.4019553326
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.235711167
Short name T724
Test name
Test status
Simulation time 2299309606 ps
CPU time 23.35 seconds
Started Jan 17 02:34:40 PM PST 24
Finished Jan 17 02:35:04 PM PST 24
Peak memory 202144 kb
Host smart-51cbd9b9-4b36-45ea-a5dc-cc55c0757978
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235711167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.235711167
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.2401535909
Short name T702
Test name
Test status
Simulation time 38192566040 ps
CPU time 4720.69 seconds
Started Jan 17 02:34:16 PM PST 24
Finished Jan 17 03:52:58 PM PST 24
Peak memory 381168 kb
Host smart-ccff8fcb-c2ea-42f6-8d09-618415958587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401535909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.2401535909
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.421535241
Short name T316
Test name
Test status
Simulation time 7619284562 ps
CPU time 5702.77 seconds
Started Jan 17 02:34:17 PM PST 24
Finished Jan 17 04:09:22 PM PST 24
Peak memory 633248 kb
Host smart-ca98a5cd-b8e9-4407-a170-fe7accbbca64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=421535241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.421535241
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.4212852293
Short name T244
Test name
Test status
Simulation time 72495508720 ps
CPU time 316.39 seconds
Started Jan 17 02:34:09 PM PST 24
Finished Jan 17 02:39:26 PM PST 24
Peak memory 202088 kb
Host smart-5ca10151-37f3-4ffa-bf92-a4184e024d74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212852293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.4212852293
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2893032651
Short name T44
Test name
Test status
Simulation time 4263879200 ps
CPU time 127.84 seconds
Started Jan 17 02:34:29 PM PST 24
Finished Jan 17 02:36:41 PM PST 24
Peak memory 345992 kb
Host smart-923eb6ce-2238-4a56-b8e9-e00863378e15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893032651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2893032651
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.848590728
Short name T805
Test name
Test status
Simulation time 13792006222 ps
CPU time 401.36 seconds
Started Jan 17 02:34:35 PM PST 24
Finished Jan 17 02:41:16 PM PST 24
Peak memory 345176 kb
Host smart-77bcc93c-e1d7-4d31-8314-33e3791b8c12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848590728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_access_during_key_req.848590728
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.2166226070
Short name T638
Test name
Test status
Simulation time 29337611 ps
CPU time 0.65 seconds
Started Jan 17 02:34:35 PM PST 24
Finished Jan 17 02:34:38 PM PST 24
Peak memory 201908 kb
Host smart-2d8f780d-9bf6-4fdd-afff-c6e17e3f1489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166226070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.2166226070
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.2297942794
Short name T2
Test name
Test status
Simulation time 62261455880 ps
CPU time 1057.65 seconds
Started Jan 17 02:34:27 PM PST 24
Finished Jan 17 02:52:06 PM PST 24
Peak memory 202128 kb
Host smart-a7ddaa7b-e652-4291-9dbf-077955d653e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297942794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2297942794
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.3242272574
Short name T709
Test name
Test status
Simulation time 35954310105 ps
CPU time 1226.11 seconds
Started Jan 17 02:34:31 PM PST 24
Finished Jan 17 02:55:00 PM PST 24
Peak memory 377040 kb
Host smart-5877ec7c-ee20-458f-afea-2f636ec4b8eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242272574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.3242272574
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.2124048638
Short name T676
Test name
Test status
Simulation time 1102639648 ps
CPU time 12.81 seconds
Started Jan 17 02:38:20 PM PST 24
Finished Jan 17 02:38:34 PM PST 24
Peak memory 212520 kb
Host smart-f8973444-b6e3-446a-ade7-435ff159b8f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124048638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.2124048638
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.3598853962
Short name T915
Test name
Test status
Simulation time 775800456 ps
CPU time 147.31 seconds
Started Jan 17 02:34:34 PM PST 24
Finished Jan 17 02:37:02 PM PST 24
Peak memory 368840 kb
Host smart-a4ac3b1b-d21b-40b5-a04d-e1e001023c9f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598853962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.3598853962
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1979528784
Short name T560
Test name
Test status
Simulation time 4546073902 ps
CPU time 152.94 seconds
Started Jan 17 02:34:31 PM PST 24
Finished Jan 17 02:37:07 PM PST 24
Peak memory 214500 kb
Host smart-75600f4f-3b3d-4796-bc56-d57ad26e5dab
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979528784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.1979528784
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.3268220946
Short name T829
Test name
Test status
Simulation time 7880290528 ps
CPU time 259.49 seconds
Started Jan 17 02:34:32 PM PST 24
Finished Jan 17 02:38:53 PM PST 24
Peak memory 202444 kb
Host smart-ed3d1ff8-297c-456b-88c4-12eab81f30e9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268220946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.3268220946
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.4074057418
Short name T238
Test name
Test status
Simulation time 11557982812 ps
CPU time 640.8 seconds
Started Jan 17 02:34:24 PM PST 24
Finished Jan 17 02:45:08 PM PST 24
Peak memory 379092 kb
Host smart-bba07baa-2ec1-422c-a52c-a3edcea9025e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074057418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.4074057418
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.300970750
Short name T593
Test name
Test status
Simulation time 2358841547 ps
CPU time 84.14 seconds
Started Jan 17 02:34:27 PM PST 24
Finished Jan 17 02:35:52 PM PST 24
Peak memory 317820 kb
Host smart-b0639ebf-eb7f-4289-b5dd-f9a03b3ca3c3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300970750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.s
ram_ctrl_partial_access.300970750
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1468012256
Short name T590
Test name
Test status
Simulation time 19081033120 ps
CPU time 403.92 seconds
Started Jan 17 02:34:33 PM PST 24
Finished Jan 17 02:41:18 PM PST 24
Peak memory 201988 kb
Host smart-c6dcbd8e-410e-4ad2-80a7-add1d3c6e134
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468012256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.1468012256
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3666306119
Short name T334
Test name
Test status
Simulation time 348616948 ps
CPU time 6.27 seconds
Started Jan 17 02:38:19 PM PST 24
Finished Jan 17 02:38:26 PM PST 24
Peak memory 202176 kb
Host smart-d2e92f59-f9b7-4bfb-a588-4f703bb37ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666306119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3666306119
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.2920665961
Short name T846
Test name
Test status
Simulation time 16682684247 ps
CPU time 952.78 seconds
Started Jan 17 02:34:33 PM PST 24
Finished Jan 17 02:50:27 PM PST 24
Peak memory 378968 kb
Host smart-710b628c-e0dc-47cd-98cc-dbc0c0c9e9ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920665961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2920665961
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3864563781
Short name T959
Test name
Test status
Simulation time 3071047445 ps
CPU time 28.67 seconds
Started Jan 17 02:34:20 PM PST 24
Finished Jan 17 02:34:51 PM PST 24
Peak memory 210420 kb
Host smart-0e92cb81-d4b1-4ef9-91d2-fa9ff36e3a66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864563781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3864563781
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.986941034
Short name T452
Test name
Test status
Simulation time 35337447030 ps
CPU time 2481.23 seconds
Started Jan 17 02:34:38 PM PST 24
Finished Jan 17 03:16:01 PM PST 24
Peak memory 381048 kb
Host smart-ec36fbcd-5885-41d0-962f-be86d530f7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986941034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_stress_all.986941034
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1934555061
Short name T293
Test name
Test status
Simulation time 2165276919 ps
CPU time 3768.45 seconds
Started Jan 17 02:34:37 PM PST 24
Finished Jan 17 03:37:28 PM PST 24
Peak memory 572776 kb
Host smart-0b1ace5b-2203-4e1d-ae4c-274ef2d5cc68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1934555061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1934555061
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.4231839431
Short name T451
Test name
Test status
Simulation time 21537995379 ps
CPU time 399.36 seconds
Started Jan 17 02:34:26 PM PST 24
Finished Jan 17 02:41:07 PM PST 24
Peak memory 202156 kb
Host smart-31cdbcc2-7570-4006-8db2-a87121342e88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231839431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.4231839431
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3108890438
Short name T650
Test name
Test status
Simulation time 3450285060 ps
CPU time 99.14 seconds
Started Jan 17 02:34:34 PM PST 24
Finished Jan 17 02:36:14 PM PST 24
Peak memory 340236 kb
Host smart-9b6c45d2-0e1b-47ca-a921-0d58ad9c6291
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108890438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.3108890438
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.294819108
Short name T250
Test name
Test status
Simulation time 11559873161 ps
CPU time 1178.98 seconds
Started Jan 17 02:34:56 PM PST 24
Finished Jan 17 02:54:37 PM PST 24
Peak memory 379212 kb
Host smart-0267171b-1c38-4e07-aefd-0a4a3a6ebb63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294819108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_access_during_key_req.294819108
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.3814542656
Short name T589
Test name
Test status
Simulation time 42397712 ps
CPU time 0.67 seconds
Started Jan 17 02:35:15 PM PST 24
Finished Jan 17 02:35:16 PM PST 24
Peak memory 201816 kb
Host smart-c4f7fa4b-0123-4f11-b345-14954ad68a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814542656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.3814542656
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.3902922329
Short name T764
Test name
Test status
Simulation time 69021201630 ps
CPU time 2314.89 seconds
Started Jan 17 02:34:40 PM PST 24
Finished Jan 17 03:13:16 PM PST 24
Peak memory 202096 kb
Host smart-e8eace72-1239-45b5-ae70-c1be2fccc0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902922329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.3902922329
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.3993678330
Short name T661
Test name
Test status
Simulation time 56311125098 ps
CPU time 165.25 seconds
Started Jan 17 02:34:55 PM PST 24
Finished Jan 17 02:37:42 PM PST 24
Peak memory 210416 kb
Host smart-3cf94675-3ce5-48de-a462-dd621eb25e77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993678330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.3993678330
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.910010593
Short name T3
Test name
Test status
Simulation time 5036226873 ps
CPU time 120.85 seconds
Started Jan 17 02:34:54 PM PST 24
Finished Jan 17 02:36:57 PM PST 24
Peak memory 346460 kb
Host smart-2bba33dd-e183-4d04-8b92-3a6f01a46df5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910010593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.910010593
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3551085503
Short name T425
Test name
Test status
Simulation time 3113770731 ps
CPU time 131.87 seconds
Started Jan 17 02:34:57 PM PST 24
Finished Jan 17 02:37:15 PM PST 24
Peak memory 211372 kb
Host smart-429f41e0-72a0-4bab-9f14-5bd6d7f1f010
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551085503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.3551085503
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1552057528
Short name T960
Test name
Test status
Simulation time 7239119753 ps
CPU time 143.11 seconds
Started Jan 17 02:34:57 PM PST 24
Finished Jan 17 02:37:25 PM PST 24
Peak memory 202436 kb
Host smart-c69822b4-f88d-4d3c-a93f-19d55f63b4c9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552057528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1552057528
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.3101619310
Short name T649
Test name
Test status
Simulation time 33891849070 ps
CPU time 1330.5 seconds
Started Jan 17 02:34:43 PM PST 24
Finished Jan 17 02:56:54 PM PST 24
Peak memory 379908 kb
Host smart-ffa021f8-ad63-4255-90ea-3b02abb4187b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101619310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.3101619310
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2242867495
Short name T861
Test name
Test status
Simulation time 623342387 ps
CPU time 31.61 seconds
Started Jan 17 02:34:45 PM PST 24
Finished Jan 17 02:35:18 PM PST 24
Peak memory 202088 kb
Host smart-6b39601d-db06-4262-97aa-2359a26b3f57
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242867495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2242867495
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.493025424
Short name T75
Test name
Test status
Simulation time 4397824170 ps
CPU time 295 seconds
Started Jan 17 02:34:54 PM PST 24
Finished Jan 17 02:39:51 PM PST 24
Peak memory 202192 kb
Host smart-7cac6dd6-08b4-499b-b2ba-f4f1b94e5aa7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493025424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.sram_ctrl_partial_access_b2b.493025424
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.3949347965
Short name T420
Test name
Test status
Simulation time 366527106 ps
CPU time 6.49 seconds
Started Jan 17 02:34:53 PM PST 24
Finished Jan 17 02:35:01 PM PST 24
Peak memory 202432 kb
Host smart-715cbe37-a0f9-49c0-b75e-03f9a1069688
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949347965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3949347965
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.4046423030
Short name T33
Test name
Test status
Simulation time 9360012391 ps
CPU time 491.03 seconds
Started Jan 17 02:34:55 PM PST 24
Finished Jan 17 02:43:08 PM PST 24
Peak memory 366804 kb
Host smart-fc8077ce-5a09-4af9-a069-8d2d2491fdab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046423030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.4046423030
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.920743388
Short name T710
Test name
Test status
Simulation time 1550146688 ps
CPU time 7.45 seconds
Started Jan 17 02:37:52 PM PST 24
Finished Jan 17 02:38:01 PM PST 24
Peak memory 199984 kb
Host smart-9afd0773-999b-4e56-b1e4-076a25e6f9e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920743388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.920743388
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.872376788
Short name T358
Test name
Test status
Simulation time 318505322 ps
CPU time 3792.73 seconds
Started Jan 17 02:35:09 PM PST 24
Finished Jan 17 03:38:27 PM PST 24
Peak memory 592228 kb
Host smart-d8379a29-fae5-4958-b64d-3777d42fb2cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=872376788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.872376788
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.511622461
Short name T566
Test name
Test status
Simulation time 11269783394 ps
CPU time 215.86 seconds
Started Jan 17 02:34:49 PM PST 24
Finished Jan 17 02:38:26 PM PST 24
Peak memory 202036 kb
Host smart-c0f64426-a5f3-4adc-a68d-ccfb8cecacc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511622461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_stress_pipeline.511622461
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1135424601
Short name T543
Test name
Test status
Simulation time 2847728372 ps
CPU time 31.2 seconds
Started Jan 17 02:34:52 PM PST 24
Finished Jan 17 02:35:24 PM PST 24
Peak memory 230832 kb
Host smart-681ca292-62f9-4354-9951-434c7d501aa3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135424601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1135424601
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1909556764
Short name T252
Test name
Test status
Simulation time 10277078198 ps
CPU time 1245.55 seconds
Started Jan 17 02:35:25 PM PST 24
Finished Jan 17 02:56:11 PM PST 24
Peak memory 380168 kb
Host smart-712140b5-a36c-4b7d-85cf-8ed4fa22abfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909556764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1909556764
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2262801274
Short name T951
Test name
Test status
Simulation time 11661254 ps
CPU time 0.64 seconds
Started Jan 17 02:35:25 PM PST 24
Finished Jan 17 02:35:27 PM PST 24
Peak memory 201476 kb
Host smart-37a793e1-1bcf-4ef4-bb1e-8a24a82a142b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262801274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2262801274
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.1523121080
Short name T263
Test name
Test status
Simulation time 75991196156 ps
CPU time 1243.87 seconds
Started Jan 17 02:35:08 PM PST 24
Finished Jan 17 02:55:55 PM PST 24
Peak memory 202188 kb
Host smart-225d9cad-9782-49d1-8b48-e7128680b040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523121080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.1523121080
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.3580602470
Short name T840
Test name
Test status
Simulation time 34013686088 ps
CPU time 90.42 seconds
Started Jan 17 02:35:18 PM PST 24
Finished Jan 17 02:36:49 PM PST 24
Peak memory 202144 kb
Host smart-b3582d83-c616-4dc3-93cd-95f7d32b7362
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580602470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.3580602470
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2457436206
Short name T646
Test name
Test status
Simulation time 1339346924 ps
CPU time 27.95 seconds
Started Jan 17 02:35:14 PM PST 24
Finished Jan 17 02:35:44 PM PST 24
Peak memory 210348 kb
Host smart-07fe60a2-06c9-44c8-a475-ed0fc7e15fc3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457436206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.2457436206
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.183243114
Short name T329
Test name
Test status
Simulation time 8627926072 ps
CPU time 140.17 seconds
Started Jan 17 02:35:26 PM PST 24
Finished Jan 17 02:37:47 PM PST 24
Peak memory 211112 kb
Host smart-0d587753-6f4b-46c7-b52a-0e07ebf5db66
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183243114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_mem_partial_access.183243114
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.3819004438
Short name T559
Test name
Test status
Simulation time 21743597866 ps
CPU time 308.94 seconds
Started Jan 17 02:35:27 PM PST 24
Finished Jan 17 02:40:38 PM PST 24
Peak memory 202176 kb
Host smart-1d4a2a11-ada8-43fc-aebe-7d08c2f6856b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819004438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.3819004438
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.890065761
Short name T859
Test name
Test status
Simulation time 20829501213 ps
CPU time 784.11 seconds
Started Jan 17 02:35:09 PM PST 24
Finished Jan 17 02:48:19 PM PST 24
Peak memory 375916 kb
Host smart-8bd34d9f-baea-481d-ba0a-f9d773329585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890065761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multip
le_keys.890065761
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.916942123
Short name T449
Test name
Test status
Simulation time 7140399635 ps
CPU time 34.03 seconds
Started Jan 17 02:35:16 PM PST 24
Finished Jan 17 02:35:51 PM PST 24
Peak memory 202076 kb
Host smart-015dc699-eaa3-44fc-837a-750fefa5fc0f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916942123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_partial_access.916942123
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1788917225
Short name T749
Test name
Test status
Simulation time 13954422843 ps
CPU time 347.53 seconds
Started Jan 17 02:35:17 PM PST 24
Finished Jan 17 02:41:06 PM PST 24
Peak memory 202092 kb
Host smart-2aa269a6-4263-4968-bc98-35bbeac50143
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788917225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.1788917225
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.2127171806
Short name T306
Test name
Test status
Simulation time 349940931 ps
CPU time 5.89 seconds
Started Jan 17 02:35:31 PM PST 24
Finished Jan 17 02:35:39 PM PST 24
Peak memory 202476 kb
Host smart-22faed02-4bac-4497-ac47-7164beb7cd4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127171806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2127171806
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.2396801672
Short name T143
Test name
Test status
Simulation time 12626377254 ps
CPU time 775.41 seconds
Started Jan 17 02:35:23 PM PST 24
Finished Jan 17 02:48:19 PM PST 24
Peak memory 349440 kb
Host smart-4f8da398-2813-4476-b7ee-f8fc228b49c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396801672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2396801672
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.3353382159
Short name T753
Test name
Test status
Simulation time 1606132990 ps
CPU time 63.06 seconds
Started Jan 17 02:35:10 PM PST 24
Finished Jan 17 02:36:18 PM PST 24
Peak memory 316580 kb
Host smart-e1f614d3-8d49-44fd-8255-6561af4778c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353382159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3353382159
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.899942976
Short name T668
Test name
Test status
Simulation time 9093869289 ps
CPU time 4089 seconds
Started Jan 17 02:35:27 PM PST 24
Finished Jan 17 03:43:37 PM PST 24
Peak memory 666680 kb
Host smart-8a4870fc-e0a6-4daf-b8d2-c84d09d620ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=899942976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.899942976
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3825223793
Short name T499
Test name
Test status
Simulation time 17774296579 ps
CPU time 355.11 seconds
Started Jan 17 02:35:09 PM PST 24
Finished Jan 17 02:41:09 PM PST 24
Peak memory 202076 kb
Host smart-5ce8d7ba-fd3c-40ee-9610-14bfe7fdcac2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825223793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.3825223793
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3657927509
Short name T860
Test name
Test status
Simulation time 2799321487 ps
CPU time 39.91 seconds
Started Jan 17 02:35:24 PM PST 24
Finished Jan 17 02:36:05 PM PST 24
Peak memory 251288 kb
Host smart-cd29931e-e806-4471-ab46-015c036d897e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657927509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3657927509
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2389620127
Short name T766
Test name
Test status
Simulation time 7915419898 ps
CPU time 1226.48 seconds
Started Jan 17 02:35:47 PM PST 24
Finished Jan 17 02:56:14 PM PST 24
Peak memory 378072 kb
Host smart-db2da504-c3f1-485f-bfc5-27652084e93f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389620127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.2389620127
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.1492616638
Short name T787
Test name
Test status
Simulation time 37962376 ps
CPU time 0.68 seconds
Started Jan 17 02:37:36 PM PST 24
Finished Jan 17 02:37:43 PM PST 24
Peak memory 200500 kb
Host smart-03811982-7db8-454a-91ec-5d678a24f590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492616638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.1492616638
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.3414048438
Short name T937
Test name
Test status
Simulation time 45097017085 ps
CPU time 749.94 seconds
Started Jan 17 02:35:33 PM PST 24
Finished Jan 17 02:48:04 PM PST 24
Peak memory 202148 kb
Host smart-83d8de90-e3e9-46a7-ab44-bcf5a462e8d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414048438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.3414048438
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.3316494723
Short name T9
Test name
Test status
Simulation time 13088237646 ps
CPU time 67.16 seconds
Started Jan 17 02:35:45 PM PST 24
Finished Jan 17 02:36:53 PM PST 24
Peak memory 202208 kb
Host smart-99951bf4-a06b-4258-b41d-d5fa79a3de6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316494723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.3316494723
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.1574149160
Short name T345
Test name
Test status
Simulation time 2761489450 ps
CPU time 31.94 seconds
Started Jan 17 02:35:47 PM PST 24
Finished Jan 17 02:36:19 PM PST 24
Peak memory 234876 kb
Host smart-d84fb8a5-aa28-4535-acd9-50683c0c1bf5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574149160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.1574149160
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.169726717
Short name T671
Test name
Test status
Simulation time 25382633548 ps
CPU time 151.59 seconds
Started Jan 17 02:35:52 PM PST 24
Finished Jan 17 02:38:24 PM PST 24
Peak memory 214588 kb
Host smart-8e7da105-1253-4da7-a741-ad75f8d3ffa5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169726717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_mem_partial_access.169726717
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.1315169283
Short name T538
Test name
Test status
Simulation time 15761026723 ps
CPU time 256.75 seconds
Started Jan 17 02:35:51 PM PST 24
Finished Jan 17 02:40:08 PM PST 24
Peak memory 202212 kb
Host smart-4539ec4a-ac1d-4393-af8c-ce3b459014a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315169283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.1315169283
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3019169565
Short name T938
Test name
Test status
Simulation time 50895016400 ps
CPU time 964.22 seconds
Started Jan 17 02:35:33 PM PST 24
Finished Jan 17 02:51:39 PM PST 24
Peak memory 379168 kb
Host smart-04892455-981e-40b0-b4b6-5696d36e067c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019169565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3019169565
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.3539533000
Short name T782
Test name
Test status
Simulation time 630057558 ps
CPU time 31.13 seconds
Started Jan 17 02:35:40 PM PST 24
Finished Jan 17 02:36:15 PM PST 24
Peak memory 202020 kb
Host smart-fe972ca1-53a6-4afd-ae72-5b055ead3b2b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539533000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.3539533000
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1093341049
Short name T940
Test name
Test status
Simulation time 33203414487 ps
CPU time 396.77 seconds
Started Jan 17 02:35:36 PM PST 24
Finished Jan 17 02:42:20 PM PST 24
Peak memory 202068 kb
Host smart-f8d32aac-a9a4-4e19-9c92-aacbb18171fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093341049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.1093341049
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.297238018
Short name T319
Test name
Test status
Simulation time 539749967 ps
CPU time 6.81 seconds
Started Jan 17 02:35:50 PM PST 24
Finished Jan 17 02:35:58 PM PST 24
Peak memory 202420 kb
Host smart-71f52eab-73e8-4cf0-95fc-57dea520abdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297238018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.297238018
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.1698082904
Short name T681
Test name
Test status
Simulation time 8233854844 ps
CPU time 522.64 seconds
Started Jan 17 02:38:01 PM PST 24
Finished Jan 17 02:46:47 PM PST 24
Peak memory 329804 kb
Host smart-c9fef9f4-69d3-4feb-b88f-36d047aa0170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698082904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1698082904
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.4079308190
Short name T14
Test name
Test status
Simulation time 18881836665 ps
CPU time 98.11 seconds
Started Jan 17 02:35:29 PM PST 24
Finished Jan 17 02:37:11 PM PST 24
Peak memory 327908 kb
Host smart-dcfd26fe-9950-4766-a17b-ea6c6bac77a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079308190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.4079308190
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.933687579
Short name T815
Test name
Test status
Simulation time 241124405800 ps
CPU time 4135.29 seconds
Started Jan 17 02:38:02 PM PST 24
Finished Jan 17 03:47:00 PM PST 24
Peak memory 376892 kb
Host smart-447143c2-aa4d-45e0-ab36-3a3e513a76bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933687579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_stress_all.933687579
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1514007803
Short name T292
Test name
Test status
Simulation time 1247911298 ps
CPU time 3040.49 seconds
Started Jan 17 02:38:02 PM PST 24
Finished Jan 17 03:28:46 PM PST 24
Peak memory 606944 kb
Host smart-9eee57ae-269d-4e49-8729-9dd5d1eb07e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1514007803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1514007803
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.631914239
Short name T643
Test name
Test status
Simulation time 21929238268 ps
CPU time 432.7 seconds
Started Jan 17 02:35:37 PM PST 24
Finished Jan 17 02:42:56 PM PST 24
Peak memory 202244 kb
Host smart-e23b167f-f234-46b0-b2c2-b195d5e6b137
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631914239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.631914239
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.429245374
Short name T445
Test name
Test status
Simulation time 3085297722 ps
CPU time 138.91 seconds
Started Jan 17 02:35:43 PM PST 24
Finished Jan 17 02:38:03 PM PST 24
Peak memory 351484 kb
Host smart-a4be40d8-c8e5-45ab-85af-106a88cf97ad
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429245374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.429245374
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.908440978
Short name T473
Test name
Test status
Simulation time 24134608706 ps
CPU time 598.32 seconds
Started Jan 17 02:36:25 PM PST 24
Finished Jan 17 02:46:25 PM PST 24
Peak memory 353560 kb
Host smart-b179b8c9-5dec-4e84-a3d0-c8368ee46b84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908440978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_access_during_key_req.908440978
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.1751733653
Short name T466
Test name
Test status
Simulation time 14631178 ps
CPU time 0.64 seconds
Started Jan 17 02:36:29 PM PST 24
Finished Jan 17 02:36:31 PM PST 24
Peak memory 201448 kb
Host smart-f2abb0ec-0b1e-436d-8df7-8bd64762d902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751733653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.1751733653
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.3724478593
Short name T261
Test name
Test status
Simulation time 219576048604 ps
CPU time 2135.7 seconds
Started Jan 17 02:36:03 PM PST 24
Finished Jan 17 03:11:39 PM PST 24
Peak memory 202156 kb
Host smart-5fe5007c-ea55-4968-8368-798d55d13ab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724478593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.3724478593
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.3164697826
Short name T851
Test name
Test status
Simulation time 5288178332 ps
CPU time 457.42 seconds
Started Jan 17 02:36:27 PM PST 24
Finished Jan 17 02:44:05 PM PST 24
Peak memory 377000 kb
Host smart-9fa8954f-efdb-4891-a48e-12d66dc864d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164697826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.3164697826
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.4139751050
Short name T459
Test name
Test status
Simulation time 2813123579 ps
CPU time 49.19 seconds
Started Jan 17 02:36:14 PM PST 24
Finished Jan 17 02:37:06 PM PST 24
Peak memory 267616 kb
Host smart-dd3297e6-9fe6-433f-8aa2-c79a8130bff6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139751050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.4139751050
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.2294234435
Short name T351
Test name
Test status
Simulation time 4029187572 ps
CPU time 131.62 seconds
Started Jan 17 02:36:26 PM PST 24
Finished Jan 17 02:38:38 PM PST 24
Peak memory 202072 kb
Host smart-8e534494-f0d6-4e93-ab92-189f6c571c62
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294234435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.2294234435
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.3900961867
Short name T797
Test name
Test status
Simulation time 9065996501 ps
CPU time 596.17 seconds
Started Jan 17 02:36:03 PM PST 24
Finished Jan 17 02:46:00 PM PST 24
Peak memory 336204 kb
Host smart-c5aa17ab-b7f9-4df0-b87b-bbdcc59a7461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900961867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.3900961867
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.434178811
Short name T429
Test name
Test status
Simulation time 1509417773 ps
CPU time 48.48 seconds
Started Jan 17 02:37:41 PM PST 24
Finished Jan 17 02:38:32 PM PST 24
Peak memory 280480 kb
Host smart-55cbc10c-8389-4f31-83de-81343ea51730
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434178811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.434178811
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1467460002
Short name T330
Test name
Test status
Simulation time 7100738053 ps
CPU time 296.59 seconds
Started Jan 17 02:36:12 PM PST 24
Finished Jan 17 02:41:10 PM PST 24
Peak memory 202384 kb
Host smart-83f48b96-53ee-45ab-9acc-62d9b3610249
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467460002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.1467460002
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.190178381
Short name T874
Test name
Test status
Simulation time 1350383951 ps
CPU time 6.63 seconds
Started Jan 17 02:37:39 PM PST 24
Finished Jan 17 02:37:49 PM PST 24
Peak memory 201856 kb
Host smart-8c227374-091d-42f8-8f4f-bb83a7dcba27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190178381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.190178381
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.1492368170
Short name T331
Test name
Test status
Simulation time 3218654091 ps
CPU time 1061.64 seconds
Started Jan 17 02:36:24 PM PST 24
Finished Jan 17 02:54:07 PM PST 24
Peak memory 371992 kb
Host smart-b1f7e5fc-4f32-4246-b0ee-7b88f26e079e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492368170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1492368170
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.2699306828
Short name T266
Test name
Test status
Simulation time 3112106256 ps
CPU time 21.62 seconds
Started Jan 17 02:36:07 PM PST 24
Finished Jan 17 02:36:30 PM PST 24
Peak memory 202160 kb
Host smart-7b6c945f-07b9-4c48-a7ba-bb71606613a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699306828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2699306828
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.3880051884
Short name T353
Test name
Test status
Simulation time 589504425484 ps
CPU time 3436.04 seconds
Started Jan 17 02:36:32 PM PST 24
Finished Jan 17 03:33:54 PM PST 24
Peak memory 380068 kb
Host smart-4be082d7-c84d-4264-b88c-7be321756920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880051884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.3880051884
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2414221595
Short name T456
Test name
Test status
Simulation time 1462147842 ps
CPU time 4822.05 seconds
Started Jan 17 02:36:32 PM PST 24
Finished Jan 17 03:56:59 PM PST 24
Peak memory 693160 kb
Host smart-313b394e-eb1b-456c-85c3-64b679b62cb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2414221595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2414221595
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1777075111
Short name T910
Test name
Test status
Simulation time 11420838081 ps
CPU time 242.31 seconds
Started Jan 17 02:36:05 PM PST 24
Finished Jan 17 02:40:08 PM PST 24
Peak memory 202164 kb
Host smart-7479cc77-187f-4b6f-8be1-a8b0f052cfe5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777075111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.1777075111
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.992017312
Short name T380
Test name
Test status
Simulation time 1507899862 ps
CPU time 50.49 seconds
Started Jan 17 02:37:39 PM PST 24
Finished Jan 17 02:38:33 PM PST 24
Peak memory 302924 kb
Host smart-f7bfda6d-effa-40ff-af1a-55dd534c9e99
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992017312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.992017312
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.2446147133
Short name T740
Test name
Test status
Simulation time 31942944 ps
CPU time 0.67 seconds
Started Jan 17 02:37:05 PM PST 24
Finished Jan 17 02:37:08 PM PST 24
Peak memory 201880 kb
Host smart-5e1218bd-4ca1-440e-961f-7ac080fd7027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446147133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.2446147133
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.1364690027
Short name T781
Test name
Test status
Simulation time 31806456594 ps
CPU time 2224.68 seconds
Started Jan 17 02:36:30 PM PST 24
Finished Jan 17 03:13:36 PM PST 24
Peak memory 202264 kb
Host smart-0d7deb65-c852-49b6-acce-73b3dbb3e912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364690027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1364690027
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.1900620247
Short name T696
Test name
Test status
Simulation time 14098932625 ps
CPU time 113.78 seconds
Started Jan 17 02:36:45 PM PST 24
Finished Jan 17 02:38:40 PM PST 24
Peak memory 210384 kb
Host smart-034c813f-fc25-41d2-b02e-f10ddcbb011d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900620247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.1900620247
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.2299414246
Short name T605
Test name
Test status
Simulation time 3172122540 ps
CPU time 28.52 seconds
Started Jan 17 02:36:38 PM PST 24
Finished Jan 17 02:37:10 PM PST 24
Peak memory 210388 kb
Host smart-7df6a73c-f367-430f-9d9c-611c4f250aca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299414246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.2299414246
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1883624196
Short name T22
Test name
Test status
Simulation time 2303374326 ps
CPU time 143.39 seconds
Started Jan 17 02:36:52 PM PST 24
Finished Jan 17 02:39:16 PM PST 24
Peak memory 213844 kb
Host smart-139a6da6-e0d5-409a-8750-72413c853340
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883624196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.1883624196
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2117755118
Short name T633
Test name
Test status
Simulation time 15763198807 ps
CPU time 249.49 seconds
Started Jan 17 02:36:49 PM PST 24
Finished Jan 17 02:40:59 PM PST 24
Peak memory 202296 kb
Host smart-e98402d8-1aa2-4a91-9330-600a0d9da826
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117755118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2117755118
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.591509887
Short name T438
Test name
Test status
Simulation time 24076902328 ps
CPU time 373.92 seconds
Started Jan 17 02:36:31 PM PST 24
Finished Jan 17 02:42:48 PM PST 24
Peak memory 380180 kb
Host smart-f97fbf85-8ecd-45e9-ab86-e721aba9f114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591509887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip
le_keys.591509887
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.699714439
Short name T750
Test name
Test status
Simulation time 375253861 ps
CPU time 14.57 seconds
Started Jan 17 02:36:36 PM PST 24
Finished Jan 17 02:36:56 PM PST 24
Peak memory 202072 kb
Host smart-7440f3b9-1551-48cd-9aa1-0d109892318c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699714439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.s
ram_ctrl_partial_access.699714439
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.874440216
Short name T338
Test name
Test status
Simulation time 152852464990 ps
CPU time 682.28 seconds
Started Jan 17 02:36:36 PM PST 24
Finished Jan 17 02:48:04 PM PST 24
Peak memory 202172 kb
Host smart-7679e5f4-dd48-411c-a8a2-7e5cb6ab807e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874440216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.sram_ctrl_partial_access_b2b.874440216
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.4018941476
Short name T965
Test name
Test status
Simulation time 357147643 ps
CPU time 13.86 seconds
Started Jan 17 02:36:48 PM PST 24
Finished Jan 17 02:37:03 PM PST 24
Peak memory 202436 kb
Host smart-29dd5802-7f79-4b02-9cb4-4685d27518ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018941476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.4018941476
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.2925830915
Short name T461
Test name
Test status
Simulation time 44545234413 ps
CPU time 1698.55 seconds
Started Jan 17 02:36:44 PM PST 24
Finished Jan 17 03:05:03 PM PST 24
Peak memory 377104 kb
Host smart-c6b252b0-5d0f-4fe9-9ab9-4c0f85ec2f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925830915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2925830915
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.4209940025
Short name T930
Test name
Test status
Simulation time 1230863976 ps
CPU time 118.12 seconds
Started Jan 17 02:36:29 PM PST 24
Finished Jan 17 02:38:28 PM PST 24
Peak memory 338088 kb
Host smart-aa8c62f8-df69-470e-a86a-51632b0447fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209940025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4209940025
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.485889370
Short name T942
Test name
Test status
Simulation time 73066814856 ps
CPU time 5143.78 seconds
Started Jan 17 02:36:57 PM PST 24
Finished Jan 17 04:02:44 PM PST 24
Peak memory 380132 kb
Host smart-f85e133b-d41a-4f1d-bbcf-da493f865a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485889370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_stress_all.485889370
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.165142238
Short name T558
Test name
Test status
Simulation time 8671347139 ps
CPU time 1386.51 seconds
Started Jan 17 02:36:54 PM PST 24
Finished Jan 17 03:00:01 PM PST 24
Peak memory 420256 kb
Host smart-b8b62c4b-1ae1-48c9-9ffa-72578738860f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=165142238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.165142238
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1113341018
Short name T247
Test name
Test status
Simulation time 2963724188 ps
CPU time 247.78 seconds
Started Jan 17 02:36:38 PM PST 24
Finished Jan 17 02:40:49 PM PST 24
Peak memory 202100 kb
Host smart-2741523d-0092-4e22-a448-42bfd3990867
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113341018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.1113341018
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1163233932
Short name T443
Test name
Test status
Simulation time 3259885501 ps
CPU time 166.46 seconds
Started Jan 17 02:36:36 PM PST 24
Finished Jan 17 02:39:28 PM PST 24
Peak memory 366896 kb
Host smart-0bfb33da-c9fe-4fee-9ee3-5ccb3ec81ab1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163233932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1163233932
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2884858887
Short name T581
Test name
Test status
Simulation time 34718555779 ps
CPU time 1605.19 seconds
Started Jan 17 02:37:16 PM PST 24
Finished Jan 17 03:04:02 PM PST 24
Peak memory 378556 kb
Host smart-bfb6f440-1944-44ff-bd72-f4dd4a36f0ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884858887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.2884858887
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.465195281
Short name T917
Test name
Test status
Simulation time 42507726 ps
CPU time 0.65 seconds
Started Jan 17 02:37:18 PM PST 24
Finished Jan 17 02:37:19 PM PST 24
Peak memory 201456 kb
Host smart-c9143353-f5f2-412d-b5a2-dbb6bc9f250b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465195281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.465195281
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.2543622360
Short name T761
Test name
Test status
Simulation time 115441570112 ps
CPU time 1266.08 seconds
Started Jan 17 02:37:00 PM PST 24
Finished Jan 17 02:58:12 PM PST 24
Peak memory 202148 kb
Host smart-1a6f57d1-b682-4504-913f-45c095937988
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543622360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.2543622360
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.356975981
Short name T505
Test name
Test status
Simulation time 102532770222 ps
CPU time 1597 seconds
Started Jan 17 02:37:16 PM PST 24
Finished Jan 17 03:03:54 PM PST 24
Peak memory 376012 kb
Host smart-eca72b07-2b4d-4b85-a2d4-22bbc82161bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356975981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executabl
e.356975981
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.1160079174
Short name T442
Test name
Test status
Simulation time 13540303700 ps
CPU time 152.67 seconds
Started Jan 17 02:37:06 PM PST 24
Finished Jan 17 02:39:40 PM PST 24
Peak memory 213724 kb
Host smart-375941ca-2e77-4a9f-9e42-40098ad52087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160079174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.1160079174
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.1879160256
Short name T401
Test name
Test status
Simulation time 807669735 ps
CPU time 138.16 seconds
Started Jan 17 02:37:06 PM PST 24
Finished Jan 17 02:39:26 PM PST 24
Peak memory 354600 kb
Host smart-003fed79-7237-4b64-b0c6-024113c6bf78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879160256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.1879160256
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.4216632882
Short name T372
Test name
Test status
Simulation time 5148586621 ps
CPU time 160.25 seconds
Started Jan 17 02:37:13 PM PST 24
Finished Jan 17 02:39:54 PM PST 24
Peak memory 213356 kb
Host smart-c70b2a0e-121f-4afc-bffc-7865e4658697
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216632882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.4216632882
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.1653860071
Short name T891
Test name
Test status
Simulation time 3943653895 ps
CPU time 255.81 seconds
Started Jan 17 02:37:13 PM PST 24
Finished Jan 17 02:41:30 PM PST 24
Peak memory 202132 kb
Host smart-bc55421a-26f6-478c-8395-39914a2eb2a4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653860071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.1653860071
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.130322684
Short name T765
Test name
Test status
Simulation time 35100210374 ps
CPU time 756 seconds
Started Jan 17 02:37:02 PM PST 24
Finished Jan 17 02:49:44 PM PST 24
Peak memory 365716 kb
Host smart-1f4c7322-491e-41e2-b28f-9bde04f71e11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130322684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.130322684
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.1096154237
Short name T864
Test name
Test status
Simulation time 2111903699 ps
CPU time 169.96 seconds
Started Jan 17 02:37:10 PM PST 24
Finished Jan 17 02:40:01 PM PST 24
Peak memory 369840 kb
Host smart-b48472f4-20f5-41aa-bd9f-f80eca337f9d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096154237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.1096154237
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3405367593
Short name T339
Test name
Test status
Simulation time 64239976550 ps
CPU time 399.48 seconds
Started Jan 17 02:37:10 PM PST 24
Finished Jan 17 02:43:50 PM PST 24
Peak memory 202140 kb
Host smart-fa3e4629-a063-4c7e-bafc-649468782cf0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405367593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.3405367593
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.3444719197
Short name T913
Test name
Test status
Simulation time 1361833839 ps
CPU time 13.19 seconds
Started Jan 17 02:37:16 PM PST 24
Finished Jan 17 02:37:30 PM PST 24
Peak memory 201956 kb
Host smart-673e8120-e1a3-475f-b8af-68362507d966
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444719197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3444719197
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.1381323270
Short name T645
Test name
Test status
Simulation time 78385835620 ps
CPU time 2233.85 seconds
Started Jan 17 02:37:15 PM PST 24
Finished Jan 17 03:14:30 PM PST 24
Peak memory 381008 kb
Host smart-3abe5b70-a5e8-4fdb-991d-957b564d724a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381323270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1381323270
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.948675326
Short name T436
Test name
Test status
Simulation time 3058291958 ps
CPU time 154.64 seconds
Started Jan 17 02:37:02 PM PST 24
Finished Jan 17 02:39:42 PM PST 24
Peak memory 354464 kb
Host smart-5cb0e280-b603-44d4-a705-2084bcfd1c47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948675326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.948675326
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.2391755019
Short name T752
Test name
Test status
Simulation time 198878756694 ps
CPU time 5854.84 seconds
Started Jan 17 02:37:19 PM PST 24
Finished Jan 17 04:14:55 PM PST 24
Peak memory 381080 kb
Host smart-eac30578-fb41-4eae-8a97-54e70826d377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391755019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.2391755019
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.167610304
Short name T865
Test name
Test status
Simulation time 861462746 ps
CPU time 5795.21 seconds
Started Jan 17 02:37:14 PM PST 24
Finished Jan 17 04:13:51 PM PST 24
Peak memory 451784 kb
Host smart-a1aa89b0-6303-4fed-a94a-62df542b405a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=167610304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.167610304
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1717886336
Short name T276
Test name
Test status
Simulation time 14961362590 ps
CPU time 294.29 seconds
Started Jan 17 02:37:06 PM PST 24
Finished Jan 17 02:42:02 PM PST 24
Peak memory 202084 kb
Host smart-6c68884e-52b2-4200-a2f2-2886c3f18ab7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717886336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.1717886336
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1962292912
Short name T562
Test name
Test status
Simulation time 719830753 ps
CPU time 30.47 seconds
Started Jan 17 02:37:07 PM PST 24
Finished Jan 17 02:37:39 PM PST 24
Peak memory 234604 kb
Host smart-963fbfb4-92c8-491b-9a5c-298fd59d0af1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962292912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1962292912
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3107154016
Short name T529
Test name
Test status
Simulation time 12445903133 ps
CPU time 364.06 seconds
Started Jan 17 02:37:40 PM PST 24
Finished Jan 17 02:43:47 PM PST 24
Peak memory 371920 kb
Host smart-11c6c620-9af9-415f-b657-e79e43058202
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107154016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3107154016
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.3749487622
Short name T926
Test name
Test status
Simulation time 23530513 ps
CPU time 0.65 seconds
Started Jan 17 02:37:56 PM PST 24
Finished Jan 17 02:37:57 PM PST 24
Peak memory 201880 kb
Host smart-d972a7a6-96bb-432a-8199-0f2e0bad10ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749487622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.3749487622
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.612295495
Short name T683
Test name
Test status
Simulation time 503398866527 ps
CPU time 1381.98 seconds
Started Jan 17 02:37:25 PM PST 24
Finished Jan 17 03:00:29 PM PST 24
Peak memory 202100 kb
Host smart-a71ba9ce-0e83-4316-82e1-0c3646c11c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612295495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.
612295495
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.2411650879
Short name T462
Test name
Test status
Simulation time 115232301387 ps
CPU time 616.5 seconds
Started Jan 17 02:37:40 PM PST 24
Finished Jan 17 02:47:59 PM PST 24
Peak memory 375984 kb
Host smart-78327b24-1ff1-4a7e-bd17-6609780f1a86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411650879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.2411650879
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.3840335112
Short name T325
Test name
Test status
Simulation time 6083878663 ps
CPU time 77.02 seconds
Started Jan 17 02:37:37 PM PST 24
Finished Jan 17 02:38:59 PM PST 24
Peak memory 202184 kb
Host smart-c2dd42c8-89f7-436b-93f6-3f30a98cfccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840335112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.3840335112
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.2640527918
Short name T841
Test name
Test status
Simulation time 804118880 ps
CPU time 189.89 seconds
Started Jan 17 02:37:32 PM PST 24
Finished Jan 17 02:40:51 PM PST 24
Peak memory 372904 kb
Host smart-1dd57887-7d78-4fa8-b717-5c2cd54ebbc9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640527918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.2640527918
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1252605703
Short name T304
Test name
Test status
Simulation time 4515581645 ps
CPU time 157.22 seconds
Started Jan 17 02:37:54 PM PST 24
Finished Jan 17 02:40:32 PM PST 24
Peak memory 214676 kb
Host smart-38f5ea55-cbc4-46cc-9419-ed489832248e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252605703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.1252605703
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2179469562
Short name T333
Test name
Test status
Simulation time 6364747991 ps
CPU time 135.3 seconds
Started Jan 17 02:37:54 PM PST 24
Finished Jan 17 02:40:10 PM PST 24
Peak memory 202292 kb
Host smart-19cce749-e103-48e3-9c77-8a96a2c26116
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179469562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2179469562
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.3418526725
Short name T546
Test name
Test status
Simulation time 72521220065 ps
CPU time 1194.56 seconds
Started Jan 17 02:37:24 PM PST 24
Finished Jan 17 02:57:20 PM PST 24
Peak memory 370300 kb
Host smart-b583c9ba-1798-4965-b5c5-1a3dccd60423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418526725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.3418526725
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.526981897
Short name T729
Test name
Test status
Simulation time 28299789966 ps
CPU time 33.82 seconds
Started Jan 17 02:37:34 PM PST 24
Finished Jan 17 02:38:15 PM PST 24
Peak memory 202092 kb
Host smart-9af3f5b6-a9ea-4a84-967b-653c652e2b69
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526981897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_partial_access.526981897
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.230376629
Short name T795
Test name
Test status
Simulation time 8538250812 ps
CPU time 292.38 seconds
Started Jan 17 02:37:37 PM PST 24
Finished Jan 17 02:42:35 PM PST 24
Peak memory 202108 kb
Host smart-6e0fcd3e-1c84-4860-9fd5-ada2db59f4a7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230376629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.sram_ctrl_partial_access_b2b.230376629
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.2624547727
Short name T491
Test name
Test status
Simulation time 346008325 ps
CPU time 6.11 seconds
Started Jan 17 02:37:54 PM PST 24
Finished Jan 17 02:38:01 PM PST 24
Peak memory 202392 kb
Host smart-bc43d981-5732-47a3-806a-953c080191ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624547727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2624547727
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.1146224679
Short name T539
Test name
Test status
Simulation time 108487851305 ps
CPU time 1436.81 seconds
Started Jan 17 02:37:40 PM PST 24
Finished Jan 17 03:01:40 PM PST 24
Peak memory 379024 kb
Host smart-d7cfec25-c720-4884-b52c-e84a2cb09bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146224679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1146224679
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.3583552677
Short name T484
Test name
Test status
Simulation time 2588972312 ps
CPU time 31.83 seconds
Started Jan 17 02:37:17 PM PST 24
Finished Jan 17 02:37:49 PM PST 24
Peak memory 202092 kb
Host smart-3db9a0d2-d845-447e-a830-1eacf37a15b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583552677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3583552677
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.1715161124
Short name T437
Test name
Test status
Simulation time 590233094117 ps
CPU time 5220.34 seconds
Started Jan 17 02:37:54 PM PST 24
Finished Jan 17 04:04:56 PM PST 24
Peak memory 381164 kb
Host smart-554f19a4-55ff-44d8-8d43-e41aef6f1cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715161124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.1715161124
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4252938750
Short name T379
Test name
Test status
Simulation time 913992412 ps
CPU time 4745.21 seconds
Started Jan 17 02:37:53 PM PST 24
Finished Jan 17 03:57:00 PM PST 24
Peak memory 485564 kb
Host smart-a17254ec-444e-465a-8b91-79d7ce3cc9de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4252938750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.4252938750
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2510003959
Short name T457
Test name
Test status
Simulation time 6284874953 ps
CPU time 502.29 seconds
Started Jan 17 02:37:31 PM PST 24
Finished Jan 17 02:46:03 PM PST 24
Peak memory 202164 kb
Host smart-3a7b9ddf-4992-4d4f-b4f9-8a6b0192a848
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510003959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.2510003959
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2685887408
Short name T892
Test name
Test status
Simulation time 2847863318 ps
CPU time 44.87 seconds
Started Jan 17 02:37:34 PM PST 24
Finished Jan 17 02:38:26 PM PST 24
Peak memory 267624 kb
Host smart-1458c5f9-5d18-4114-ba5e-6a8699127690
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685887408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.2685887408
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1990768176
Short name T976
Test name
Test status
Simulation time 29558366919 ps
CPU time 1064.02 seconds
Started Jan 17 02:32:26 PM PST 24
Finished Jan 17 02:50:12 PM PST 24
Peak memory 379172 kb
Host smart-9f35c853-c38b-479d-b5c5-b16c4ecc1e8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990768176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.1990768176
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.1944924574
Short name T410
Test name
Test status
Simulation time 15512649 ps
CPU time 0.63 seconds
Started Jan 17 02:38:18 PM PST 24
Finished Jan 17 02:38:20 PM PST 24
Peak memory 201660 kb
Host smart-2c8f1c76-4336-41d8-8a21-a7082a9326fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944924574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.1944924574
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.3967015754
Short name T776
Test name
Test status
Simulation time 105790287727 ps
CPU time 583.68 seconds
Started Jan 17 02:32:26 PM PST 24
Finished Jan 17 02:42:11 PM PST 24
Peak memory 202172 kb
Host smart-b241c5cd-49bc-45cb-897b-2c81c180c3fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967015754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
3967015754
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.4156793014
Short name T677
Test name
Test status
Simulation time 4021060946 ps
CPU time 88.9 seconds
Started Jan 17 02:32:41 PM PST 24
Finished Jan 17 02:34:11 PM PST 24
Peak memory 210404 kb
Host smart-b53bf17b-8ff5-4a92-8e61-f78f35c15576
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156793014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.4156793014
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.2780350644
Short name T967
Test name
Test status
Simulation time 757964156 ps
CPU time 70.91 seconds
Started Jan 17 02:32:53 PM PST 24
Finished Jan 17 02:34:04 PM PST 24
Peak memory 302236 kb
Host smart-399fd3d8-d679-4f27-afcb-98246303200e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780350644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.2780350644
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1839651300
Short name T664
Test name
Test status
Simulation time 32552789062 ps
CPU time 169.21 seconds
Started Jan 17 02:33:37 PM PST 24
Finished Jan 17 02:36:29 PM PST 24
Peak memory 210960 kb
Host smart-ecd4b902-8318-4a4b-93aa-28c44ab83fb3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839651300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.1839651300
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.2895124838
Short name T296
Test name
Test status
Simulation time 7040494397 ps
CPU time 257.42 seconds
Started Jan 17 02:33:28 PM PST 24
Finished Jan 17 02:37:46 PM PST 24
Peak memory 202356 kb
Host smart-459fdaee-e28f-491d-bb9f-806ab50ad642
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895124838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.2895124838
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.3592089409
Short name T479
Test name
Test status
Simulation time 14939797288 ps
CPU time 514.9 seconds
Started Jan 17 02:32:56 PM PST 24
Finished Jan 17 02:41:32 PM PST 24
Peak memory 345356 kb
Host smart-ea69bf34-7c50-4558-8cf5-183bfc4fce89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592089409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.3592089409
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.454036751
Short name T342
Test name
Test status
Simulation time 773851983 ps
CPU time 7.75 seconds
Started Jan 17 02:32:34 PM PST 24
Finished Jan 17 02:32:45 PM PST 24
Peak memory 202084 kb
Host smart-87a4090e-3e95-4011-af06-ec5f50c2a482
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454036751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sr
am_ctrl_partial_access.454036751
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1594175619
Short name T980
Test name
Test status
Simulation time 52055165295 ps
CPU time 527.04 seconds
Started Jan 17 02:32:32 PM PST 24
Finished Jan 17 02:41:25 PM PST 24
Peak memory 202108 kb
Host smart-74af57fa-a597-4ca9-826c-6f0d55fda4ec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594175619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.1594175619
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.3684084581
Short name T684
Test name
Test status
Simulation time 42259742137 ps
CPU time 1179.96 seconds
Started Jan 17 02:33:01 PM PST 24
Finished Jan 17 02:52:42 PM PST 24
Peak memory 379568 kb
Host smart-2aa4eae6-13fe-49ca-9e0f-df992367d263
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684084581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3684084581
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.1776507663
Short name T32
Test name
Test status
Simulation time 213227474 ps
CPU time 1.91 seconds
Started Jan 17 02:33:08 PM PST 24
Finished Jan 17 02:33:12 PM PST 24
Peak memory 221012 kb
Host smart-0a07a5bb-74b6-498a-b9f6-408a0908ad10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776507663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.1776507663
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.3992813481
Short name T155
Test name
Test status
Simulation time 10392956466 ps
CPU time 28.59 seconds
Started Jan 17 02:32:55 PM PST 24
Finished Jan 17 02:33:25 PM PST 24
Peak memory 202144 kb
Host smart-f3dbf442-543b-43c1-a60c-835f42a0e42e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992813481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3992813481
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.3545930090
Short name T384
Test name
Test status
Simulation time 137298353260 ps
CPU time 4205.47 seconds
Started Jan 17 02:32:29 PM PST 24
Finished Jan 17 03:42:41 PM PST 24
Peak memory 377224 kb
Host smart-7b67adfa-864b-4e13-b634-cb7775949d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545930090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.3545930090
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1289357118
Short name T639
Test name
Test status
Simulation time 908098922 ps
CPU time 1608.61 seconds
Started Jan 17 02:34:31 PM PST 24
Finished Jan 17 03:01:22 PM PST 24
Peak memory 551772 kb
Host smart-e4ccdd3b-1cbc-4787-bcaa-4ccf0ec79edb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1289357118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1289357118
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2714532439
Short name T758
Test name
Test status
Simulation time 6160473658 ps
CPU time 459.46 seconds
Started Jan 17 02:33:30 PM PST 24
Finished Jan 17 02:41:10 PM PST 24
Peak memory 202176 kb
Host smart-285dc25a-b1a7-448d-a3f6-ceca2339375d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714532439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.2714532439
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3093257043
Short name T535
Test name
Test status
Simulation time 681883017 ps
CPU time 27.24 seconds
Started Jan 17 02:32:26 PM PST 24
Finished Jan 17 02:32:55 PM PST 24
Peak memory 215820 kb
Host smart-5f24099a-ff18-4213-affc-dc657b5fd0fa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093257043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3093257043
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1062100387
Short name T929
Test name
Test status
Simulation time 35366512864 ps
CPU time 1013.19 seconds
Started Jan 17 02:38:04 PM PST 24
Finished Jan 17 02:55:02 PM PST 24
Peak memory 379692 kb
Host smart-03cf0796-59fc-4120-9bad-65be27b7ed68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062100387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.1062100387
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.94141890
Short name T704
Test name
Test status
Simulation time 16613291 ps
CPU time 0.68 seconds
Started Jan 17 02:38:16 PM PST 24
Finished Jan 17 02:38:18 PM PST 24
Peak memory 201892 kb
Host smart-b0ddc962-3cb7-4b45-a7b9-c74b73c283c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94141890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_alert_test.94141890
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.1575186572
Short name T847
Test name
Test status
Simulation time 346660260161 ps
CPU time 811.94 seconds
Started Jan 17 02:37:54 PM PST 24
Finished Jan 17 02:51:26 PM PST 24
Peak memory 202228 kb
Host smart-961e9a7e-afaf-4546-82e5-aee33c1160ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575186572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.1575186572
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.3060131987
Short name T648
Test name
Test status
Simulation time 48700246421 ps
CPU time 1664.88 seconds
Started Jan 17 02:38:04 PM PST 24
Finished Jan 17 03:05:54 PM PST 24
Peak memory 378056 kb
Host smart-f55bbc83-469f-4448-a81c-c168ada03b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060131987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.3060131987
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.2175350073
Short name T127
Test name
Test status
Simulation time 8587071725 ps
CPU time 91.71 seconds
Started Jan 17 02:37:59 PM PST 24
Finished Jan 17 02:39:32 PM PST 24
Peak memory 202148 kb
Host smart-bf7812ed-d7e2-4d5e-af2a-bda2ac6025bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175350073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.2175350073
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.936061050
Short name T435
Test name
Test status
Simulation time 3788659509 ps
CPU time 33.75 seconds
Started Jan 17 02:37:59 PM PST 24
Finished Jan 17 02:38:34 PM PST 24
Peak memory 235072 kb
Host smart-97ca844c-0f71-47e5-8ed9-54dd6d3e9bbd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936061050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.sram_ctrl_max_throughput.936061050
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2054131497
Short name T922
Test name
Test status
Simulation time 1971489106 ps
CPU time 76.24 seconds
Started Jan 17 02:38:13 PM PST 24
Finished Jan 17 02:39:34 PM PST 24
Peak memory 218108 kb
Host smart-0edf51a9-595c-4137-b5b3-dd7c1f502711
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054131497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2054131497
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.3018369346
Short name T545
Test name
Test status
Simulation time 4113771366 ps
CPU time 261.34 seconds
Started Jan 17 02:38:12 PM PST 24
Finished Jan 17 02:42:39 PM PST 24
Peak memory 201772 kb
Host smart-79388fb6-dfb8-4757-987e-17b3587d1d1f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018369346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.3018369346
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.3669221341
Short name T889
Test name
Test status
Simulation time 40238539070 ps
CPU time 898.55 seconds
Started Jan 17 02:37:52 PM PST 24
Finished Jan 17 02:52:52 PM PST 24
Peak memory 380112 kb
Host smart-9999efcc-41e3-45a1-a5bd-f3bf0059bd10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669221341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.3669221341
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.2951499357
Short name T403
Test name
Test status
Simulation time 3262811660 ps
CPU time 17.38 seconds
Started Jan 17 02:37:57 PM PST 24
Finished Jan 17 02:38:15 PM PST 24
Peak memory 202136 kb
Host smart-6a7fabec-d9a8-4528-82f8-2eaff2090a38
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951499357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.2951499357
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.4102757080
Short name T412
Test name
Test status
Simulation time 15764437164 ps
CPU time 373.92 seconds
Started Jan 17 02:37:58 PM PST 24
Finished Jan 17 02:44:13 PM PST 24
Peak memory 202148 kb
Host smart-4199b76b-da93-4fc0-a49b-072c49123835
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102757080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.4102757080
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.3257148468
Short name T422
Test name
Test status
Simulation time 345873241 ps
CPU time 6.7 seconds
Started Jan 17 02:38:04 PM PST 24
Finished Jan 17 02:38:15 PM PST 24
Peak memory 202284 kb
Host smart-a3a3cfae-aaa9-4c86-9ad5-004e5ea40175
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257148468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3257148468
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.662009915
Short name T138
Test name
Test status
Simulation time 7614863835 ps
CPU time 847.8 seconds
Started Jan 17 02:38:07 PM PST 24
Finished Jan 17 02:52:18 PM PST 24
Peak memory 372928 kb
Host smart-2b920f4a-7ed3-41e6-bad1-e9a54da3ab33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662009915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.662009915
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.4163582898
Short name T522
Test name
Test status
Simulation time 4180200564 ps
CPU time 61.44 seconds
Started Jan 17 02:37:52 PM PST 24
Finished Jan 17 02:38:55 PM PST 24
Peak memory 303524 kb
Host smart-be3c1df0-5db5-45ff-b6bc-9c4fe3cdd1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163582898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4163582898
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1392596850
Short name T501
Test name
Test status
Simulation time 615755588 ps
CPU time 3015.42 seconds
Started Jan 17 02:38:18 PM PST 24
Finished Jan 17 03:28:35 PM PST 24
Peak memory 586308 kb
Host smart-efcfe408-fa49-4bcc-a9ce-91b1dfa51097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1392596850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1392596850
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.566977888
Short name T619
Test name
Test status
Simulation time 29031043649 ps
CPU time 259.01 seconds
Started Jan 17 02:37:54 PM PST 24
Finished Jan 17 02:42:14 PM PST 24
Peak memory 202284 kb
Host smart-a91a6a03-bc6b-4bcb-9718-5ed120329c65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566977888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_stress_pipeline.566977888
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1203126612
Short name T812
Test name
Test status
Simulation time 685489444 ps
CPU time 27.71 seconds
Started Jan 17 02:37:59 PM PST 24
Finished Jan 17 02:38:28 PM PST 24
Peak memory 211328 kb
Host smart-c4f1a3ee-3950-4036-860f-ec8c17d5dfde
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203126612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1203126612
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2040365772
Short name T741
Test name
Test status
Simulation time 4289378665 ps
CPU time 1072.14 seconds
Started Jan 17 02:38:37 PM PST 24
Finished Jan 17 02:56:34 PM PST 24
Peak memory 380064 kb
Host smart-d71333fa-ad80-4cb7-a9a4-8d433bf82e1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040365772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.2040365772
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.3111875583
Short name T597
Test name
Test status
Simulation time 40967394 ps
CPU time 0.64 seconds
Started Jan 17 02:38:48 PM PST 24
Finished Jan 17 02:38:53 PM PST 24
Peak memory 201900 kb
Host smart-000e8e4a-1638-4530-95a6-f86e8733e28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111875583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.3111875583
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1774060880
Short name T406
Test name
Test status
Simulation time 121999900081 ps
CPU time 2245.72 seconds
Started Jan 17 02:38:32 PM PST 24
Finished Jan 17 03:15:58 PM PST 24
Peak memory 202364 kb
Host smart-f53e06c5-dda5-4565-8e76-e42c011264c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774060880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1774060880
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.398582701
Short name T806
Test name
Test status
Simulation time 8072864683 ps
CPU time 394.17 seconds
Started Jan 17 02:38:38 PM PST 24
Finished Jan 17 02:45:17 PM PST 24
Peak memory 376012 kb
Host smart-a640d659-cbf6-4081-a43b-295c193560c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398582701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl
e.398582701
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.958135496
Short name T877
Test name
Test status
Simulation time 3753591306 ps
CPU time 27.94 seconds
Started Jan 17 02:38:38 PM PST 24
Finished Jan 17 02:39:11 PM PST 24
Peak memory 218468 kb
Host smart-e7a8765c-76e3-4001-9350-82c64bdeee19
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958135496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.958135496
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.278824008
Short name T886
Test name
Test status
Simulation time 9035278481 ps
CPU time 86.53 seconds
Started Jan 17 02:38:43 PM PST 24
Finished Jan 17 02:40:19 PM PST 24
Peak memory 211116 kb
Host smart-67fb4674-11b0-4489-9be8-1a849d478ac0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278824008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.sram_ctrl_mem_partial_access.278824008
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.3419028392
Short name T644
Test name
Test status
Simulation time 14358745724 ps
CPU time 282.36 seconds
Started Jan 17 02:38:42 PM PST 24
Finished Jan 17 02:43:34 PM PST 24
Peak memory 202144 kb
Host smart-d01bfd01-ea91-4f2d-9ea5-adee9a508924
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419028392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.3419028392
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.3125432455
Short name T147
Test name
Test status
Simulation time 106557474934 ps
CPU time 1486.31 seconds
Started Jan 17 02:38:35 PM PST 24
Finished Jan 17 03:03:24 PM PST 24
Peak memory 378024 kb
Host smart-fdfe0d45-8613-4570-9421-64333428c6f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125432455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.3125432455
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.1606557667
Short name T777
Test name
Test status
Simulation time 398407511 ps
CPU time 22.45 seconds
Started Jan 17 02:38:33 PM PST 24
Finished Jan 17 02:38:56 PM PST 24
Peak memory 238240 kb
Host smart-7f5f60a9-2e4f-4d10-aaf3-9f8de3905c84
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606557667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.1606557667
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.212154385
Short name T582
Test name
Test status
Simulation time 1208962689 ps
CPU time 13.6 seconds
Started Jan 17 02:38:42 PM PST 24
Finished Jan 17 02:39:06 PM PST 24
Peak memory 202392 kb
Host smart-afb0d496-9d5c-4995-8d40-03a2f3d53204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212154385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.212154385
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.1213962861
Short name T492
Test name
Test status
Simulation time 4530538270 ps
CPU time 233.58 seconds
Started Jan 17 02:38:43 PM PST 24
Finished Jan 17 02:42:46 PM PST 24
Peak memory 331952 kb
Host smart-ff41cec2-e2ee-4d7b-acf4-d09969e73599
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213962861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1213962861
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3633537002
Short name T497
Test name
Test status
Simulation time 812751502 ps
CPU time 14.37 seconds
Started Jan 17 02:38:25 PM PST 24
Finished Jan 17 02:38:40 PM PST 24
Peak memory 202012 kb
Host smart-717d79b2-7533-4d62-8ce9-3fef0bc33966
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633537002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3633537002
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.1153786797
Short name T792
Test name
Test status
Simulation time 444271764614 ps
CPU time 4786.21 seconds
Started Jan 17 02:38:46 PM PST 24
Finished Jan 17 03:58:39 PM PST 24
Peak memory 386260 kb
Host smart-bfe08b86-9234-4dae-a2d2-8d053ce7c7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153786797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.1153786797
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.886443544
Short name T791
Test name
Test status
Simulation time 1098886155 ps
CPU time 1853.58 seconds
Started Jan 17 02:38:44 PM PST 24
Finished Jan 17 03:09:46 PM PST 24
Peak memory 422480 kb
Host smart-c2261c6c-b788-466e-97c4-896ff4c54db8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=886443544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.886443544
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1899019102
Short name T237
Test name
Test status
Simulation time 12943711503 ps
CPU time 257.59 seconds
Started Jan 17 02:38:33 PM PST 24
Finished Jan 17 02:42:51 PM PST 24
Peak memory 202148 kb
Host smart-b2b3d353-a0f5-4e76-ae1b-7ef94ca137fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899019102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.1899019102
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2979836339
Short name T834
Test name
Test status
Simulation time 742057898 ps
CPU time 70.26 seconds
Started Jan 17 02:38:37 PM PST 24
Finished Jan 17 02:39:52 PM PST 24
Peak memory 307436 kb
Host smart-7d1c3aaa-e8d3-4bec-bfae-053d56ffedf0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979836339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2979836339
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3355483628
Short name T626
Test name
Test status
Simulation time 12504731178 ps
CPU time 702.1 seconds
Started Jan 17 02:39:02 PM PST 24
Finished Jan 17 02:50:45 PM PST 24
Peak memory 361460 kb
Host smart-de70fc6f-c58b-4cf3-9703-3acd7c23f373
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355483628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.3355483628
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.1729049564
Short name T944
Test name
Test status
Simulation time 48957969 ps
CPU time 0.69 seconds
Started Jan 17 02:39:08 PM PST 24
Finished Jan 17 02:39:10 PM PST 24
Peak memory 201700 kb
Host smart-d224c300-684b-40e3-9dad-a20f84db7d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729049564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.1729049564
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.630905950
Short name T718
Test name
Test status
Simulation time 4694882029 ps
CPU time 206.9 seconds
Started Jan 17 02:39:01 PM PST 24
Finished Jan 17 02:42:28 PM PST 24
Peak memory 339004 kb
Host smart-eef4416a-c595-452c-9ae5-7b02875e6c25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630905950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl
e.630905950
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.2122877391
Short name T126
Test name
Test status
Simulation time 5548472993 ps
CPU time 17.84 seconds
Started Jan 17 02:39:02 PM PST 24
Finished Jan 17 02:39:21 PM PST 24
Peak memory 213612 kb
Host smart-92ec067f-1d29-467e-842e-fa5b35f3f99a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122877391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.2122877391
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.1358828382
Short name T246
Test name
Test status
Simulation time 2950739583 ps
CPU time 49.78 seconds
Started Jan 17 02:38:54 PM PST 24
Finished Jan 17 02:39:49 PM PST 24
Peak memory 269668 kb
Host smart-7a1f6f36-9b4e-4c38-b3d7-ae17eade4263
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358828382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.1358828382
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2478881325
Short name T486
Test name
Test status
Simulation time 5181543357 ps
CPU time 150.82 seconds
Started Jan 17 02:39:06 PM PST 24
Finished Jan 17 02:41:38 PM PST 24
Peak memory 214360 kb
Host smart-786cdff6-4ef8-4b30-bc90-96b2d8bfaa16
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478881325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.2478881325
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.1371288749
Short name T563
Test name
Test status
Simulation time 63861695765 ps
CPU time 180.35 seconds
Started Jan 17 02:39:07 PM PST 24
Finished Jan 17 02:42:08 PM PST 24
Peak memory 202528 kb
Host smart-60dfaa5e-b118-4e47-8b45-fdc126a5d8ae
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371288749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.1371288749
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.304098845
Short name T373
Test name
Test status
Simulation time 24226181292 ps
CPU time 2047.97 seconds
Started Jan 17 02:38:46 PM PST 24
Finished Jan 17 03:13:01 PM PST 24
Peak memory 380156 kb
Host smart-d4eecff1-30da-45b2-b200-b868caa5dae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304098845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip
le_keys.304098845
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.3739811110
Short name T549
Test name
Test status
Simulation time 865242226 ps
CPU time 16.51 seconds
Started Jan 17 02:38:53 PM PST 24
Finished Jan 17 02:39:16 PM PST 24
Peak memory 202096 kb
Host smart-4ed8a041-77a4-4971-9b90-0c32c92eda67
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739811110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.3739811110
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.976769744
Short name T863
Test name
Test status
Simulation time 4248558128 ps
CPU time 265.85 seconds
Started Jan 17 02:38:53 PM PST 24
Finished Jan 17 02:43:25 PM PST 24
Peak memory 201996 kb
Host smart-40f14a77-9415-4fb8-81d4-42f43abb0290
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976769744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.sram_ctrl_partial_access_b2b.976769744
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.3764235008
Short name T941
Test name
Test status
Simulation time 349381141 ps
CPU time 14.47 seconds
Started Jan 17 02:39:01 PM PST 24
Finished Jan 17 02:39:16 PM PST 24
Peak memory 202404 kb
Host smart-cc578939-3cbf-407d-9072-28722684f964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764235008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3764235008
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.944720333
Short name T983
Test name
Test status
Simulation time 64478459859 ps
CPU time 1580.39 seconds
Started Jan 17 02:39:03 PM PST 24
Finished Jan 17 03:05:25 PM PST 24
Peak memory 378288 kb
Host smart-41dfa90e-2313-4fac-9a3d-6ec9f7118540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944720333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.944720333
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.939430403
Short name T811
Test name
Test status
Simulation time 1723862165 ps
CPU time 70.76 seconds
Started Jan 17 02:38:48 PM PST 24
Finished Jan 17 02:40:03 PM PST 24
Peak memory 316604 kb
Host smart-9c55d08e-2d73-4e61-991e-5d5ab554e769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939430403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.939430403
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3615513161
Short name T918
Test name
Test status
Simulation time 3021318204 ps
CPU time 1111.63 seconds
Started Jan 17 02:39:05 PM PST 24
Finished Jan 17 02:57:38 PM PST 24
Peak memory 412948 kb
Host smart-5ede0c9b-8e30-4a5c-9540-88846a7b48d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3615513161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3615513161
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.666332736
Short name T315
Test name
Test status
Simulation time 3457289167 ps
CPU time 290.54 seconds
Started Jan 17 02:38:52 PM PST 24
Finished Jan 17 02:43:49 PM PST 24
Peak memory 202212 kb
Host smart-ee4c35f6-12a2-48ed-906e-c9866ab7ce2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666332736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.666332736
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2307724812
Short name T280
Test name
Test status
Simulation time 780127887 ps
CPU time 144.43 seconds
Started Jan 17 02:38:53 PM PST 24
Finished Jan 17 02:41:23 PM PST 24
Peak memory 353396 kb
Host smart-8dcbf308-4ea7-4c5f-a50b-62b5599c8a0c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307724812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2307724812
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2589258889
Short name T536
Test name
Test status
Simulation time 9956124171 ps
CPU time 745.38 seconds
Started Jan 17 02:39:14 PM PST 24
Finished Jan 17 02:51:40 PM PST 24
Peak memory 376904 kb
Host smart-04399cdc-24ff-4804-aaf6-1dcc3a21156b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589258889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.2589258889
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1586755792
Short name T596
Test name
Test status
Simulation time 103424769 ps
CPU time 0.65 seconds
Started Jan 17 02:39:29 PM PST 24
Finished Jan 17 02:39:32 PM PST 24
Peak memory 201668 kb
Host smart-4b17038a-4698-41f6-9254-0db323fc6ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586755792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1586755792
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.484118539
Short name T18
Test name
Test status
Simulation time 253516250612 ps
CPU time 2104.95 seconds
Started Jan 17 02:39:14 PM PST 24
Finished Jan 17 03:14:20 PM PST 24
Peak memory 202100 kb
Host smart-5d521a06-5d6c-4561-8851-374cccd29bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484118539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.
484118539
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.4172536138
Short name T359
Test name
Test status
Simulation time 16819531517 ps
CPU time 538.78 seconds
Started Jan 17 02:39:15 PM PST 24
Finished Jan 17 02:48:14 PM PST 24
Peak memory 375984 kb
Host smart-42d50469-7d6a-4da4-a0ba-4d855d1c5453
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172536138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.4172536138
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.258189974
Short name T730
Test name
Test status
Simulation time 5645273652 ps
CPU time 77.59 seconds
Started Jan 17 02:39:14 PM PST 24
Finished Jan 17 02:40:32 PM PST 24
Peak memory 202000 kb
Host smart-67708975-6849-4434-aa3e-c620cf1af7c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258189974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esc
alation.258189974
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.2677733500
Short name T419
Test name
Test status
Simulation time 715423024 ps
CPU time 28.21 seconds
Started Jan 17 02:39:13 PM PST 24
Finished Jan 17 02:39:43 PM PST 24
Peak memory 211368 kb
Host smart-57cf1eaf-0265-4a1d-b09c-c70b96c24988
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677733500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.2677733500
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1815234288
Short name T790
Test name
Test status
Simulation time 17387362793 ps
CPU time 83.5 seconds
Started Jan 17 02:39:21 PM PST 24
Finished Jan 17 02:40:47 PM PST 24
Peak memory 211052 kb
Host smart-fd44c257-69ba-4cb1-af15-fe519e7e30bc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815234288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.1815234288
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.474795668
Short name T760
Test name
Test status
Simulation time 13917450231 ps
CPU time 288.23 seconds
Started Jan 17 02:39:18 PM PST 24
Finished Jan 17 02:44:09 PM PST 24
Peak memory 202540 kb
Host smart-b85f77bd-e6ae-477f-8b6d-acbb6f93846f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474795668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl
_mem_walk.474795668
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.2240535166
Short name T235
Test name
Test status
Simulation time 20132921040 ps
CPU time 1186.98 seconds
Started Jan 17 02:39:07 PM PST 24
Finished Jan 17 02:58:55 PM PST 24
Peak memory 379152 kb
Host smart-ff146697-7a86-4925-a8c9-f133977a1078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240535166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.2240535166
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.1182336295
Short name T64
Test name
Test status
Simulation time 1936836704 ps
CPU time 44.29 seconds
Started Jan 17 02:39:12 PM PST 24
Finished Jan 17 02:39:58 PM PST 24
Peak memory 202040 kb
Host smart-6aaae4fa-cdf1-430e-b870-a2ffca205e05
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182336295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.1182336295
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.458887086
Short name T415
Test name
Test status
Simulation time 21293413412 ps
CPU time 365.64 seconds
Started Jan 17 02:39:15 PM PST 24
Finished Jan 17 02:45:21 PM PST 24
Peak memory 202140 kb
Host smart-a21b8703-06b0-43be-890d-0b53ca0d26cd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458887086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.sram_ctrl_partial_access_b2b.458887086
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2984539552
Short name T958
Test name
Test status
Simulation time 1459594495 ps
CPU time 6.51 seconds
Started Jan 17 02:39:20 PM PST 24
Finished Jan 17 02:39:30 PM PST 24
Peak memory 202420 kb
Host smart-fb32a7e6-47b3-47ac-967c-3323f0421c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984539552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2984539552
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.783710967
Short name T337
Test name
Test status
Simulation time 27958978229 ps
CPU time 779.27 seconds
Started Jan 17 02:39:13 PM PST 24
Finished Jan 17 02:52:14 PM PST 24
Peak memory 375044 kb
Host smart-0c0163be-9730-4a91-9b78-1eefc0ad9728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783710967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.783710967
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.2847179620
Short name T255
Test name
Test status
Simulation time 716225781 ps
CPU time 12.74 seconds
Started Jan 17 02:39:06 PM PST 24
Finished Jan 17 02:39:19 PM PST 24
Peak memory 202116 kb
Host smart-a55b5241-3aeb-4529-bee5-6468cd52f04c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847179620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2847179620
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.1876263640
Short name T973
Test name
Test status
Simulation time 87755773241 ps
CPU time 4858.06 seconds
Started Jan 17 02:39:21 PM PST 24
Finished Jan 17 04:00:22 PM PST 24
Peak memory 379032 kb
Host smart-ccf1c652-1e45-4af6-bdbd-77ced702b093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876263640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.1876263640
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3730480839
Short name T574
Test name
Test status
Simulation time 1725084585 ps
CPU time 3434.81 seconds
Started Jan 17 02:39:18 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 432196 kb
Host smart-4ddc4f20-9a52-4f69-8614-13a362825bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3730480839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3730480839
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1945641906
Short name T775
Test name
Test status
Simulation time 18582977986 ps
CPU time 357.3 seconds
Started Jan 17 02:39:13 PM PST 24
Finished Jan 17 02:45:12 PM PST 24
Peak memory 202180 kb
Host smart-1b205af4-4245-477f-906d-05ad010c9169
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945641906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.1945641906
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.727008470
Short name T954
Test name
Test status
Simulation time 3033634608 ps
CPU time 123.84 seconds
Started Jan 17 02:39:14 PM PST 24
Finished Jan 17 02:41:18 PM PST 24
Peak memory 336168 kb
Host smart-4269b864-e648-4ee0-b72d-f093304db59b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727008470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.727008470
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1941209632
Short name T571
Test name
Test status
Simulation time 109757877846 ps
CPU time 1665.29 seconds
Started Jan 17 02:39:38 PM PST 24
Finished Jan 17 03:07:25 PM PST 24
Peak memory 373976 kb
Host smart-b974fa20-ae59-4614-830c-13b7959db50f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941209632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.1941209632
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.278167313
Short name T513
Test name
Test status
Simulation time 11575427 ps
CPU time 0.65 seconds
Started Jan 17 02:39:44 PM PST 24
Finished Jan 17 02:39:51 PM PST 24
Peak memory 201856 kb
Host smart-5fbd9058-ce95-47ea-8409-8257bd53a013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278167313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.278167313
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.4016923495
Short name T946
Test name
Test status
Simulation time 56011913833 ps
CPU time 971.83 seconds
Started Jan 17 02:39:25 PM PST 24
Finished Jan 17 02:55:43 PM PST 24
Peak memory 202164 kb
Host smart-6bedcc2f-20f7-4b3e-94d7-171a0a22b449
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016923495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.4016923495
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.3457163793
Short name T430
Test name
Test status
Simulation time 18319355825 ps
CPU time 1189.59 seconds
Started Jan 17 02:39:37 PM PST 24
Finished Jan 17 02:59:27 PM PST 24
Peak memory 372888 kb
Host smart-b1bce083-c7dd-4b0b-94d1-8092a0fd1926
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457163793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.3457163793
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.3790539211
Short name T343
Test name
Test status
Simulation time 8080725384 ps
CPU time 15.22 seconds
Started Jan 17 02:39:37 PM PST 24
Finished Jan 17 02:39:53 PM PST 24
Peak memory 202112 kb
Host smart-516d2641-4118-417f-a46a-40deb6722c00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790539211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.3790539211
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2006119294
Short name T921
Test name
Test status
Simulation time 821669709 ps
CPU time 50.23 seconds
Started Jan 17 02:39:33 PM PST 24
Finished Jan 17 02:40:24 PM PST 24
Peak memory 272748 kb
Host smart-f056b4a0-4ec7-4fa8-8aca-d15e9e7ce42a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006119294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2006119294
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.84143035
Short name T519
Test name
Test status
Simulation time 8733263400 ps
CPU time 147.27 seconds
Started Jan 17 02:39:45 PM PST 24
Finished Jan 17 02:42:18 PM PST 24
Peak memory 210792 kb
Host smart-a5bb4680-e329-4802-b54f-94638da3e054
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84143035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_mem_partial_access.84143035
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.23948104
Short name T431
Test name
Test status
Simulation time 28728412990 ps
CPU time 150.75 seconds
Started Jan 17 02:39:43 PM PST 24
Finished Jan 17 02:42:20 PM PST 24
Peak memory 202172 kb
Host smart-8f3a1f28-93dd-4c5b-8dc6-14bb53c2a767
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23948104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_
mem_walk.23948104
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.2652490918
Short name T305
Test name
Test status
Simulation time 12594556890 ps
CPU time 526.32 seconds
Started Jan 17 02:39:26 PM PST 24
Finished Jan 17 02:48:18 PM PST 24
Peak memory 379116 kb
Host smart-9e07ed6f-c7b2-4151-98cf-ff08697cec26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652490918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.2652490918
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3060912349
Short name T362
Test name
Test status
Simulation time 795352963 ps
CPU time 57.46 seconds
Started Jan 17 02:39:32 PM PST 24
Finished Jan 17 02:40:30 PM PST 24
Peak memory 302448 kb
Host smart-ed0df84e-5569-460f-9585-eb679f91e44f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060912349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3060912349
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4018342429
Short name T949
Test name
Test status
Simulation time 4490070418 ps
CPU time 284.09 seconds
Started Jan 17 02:39:31 PM PST 24
Finished Jan 17 02:44:17 PM PST 24
Peak memory 202180 kb
Host smart-4d8c0c76-c2b9-4700-b542-16937eb24219
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018342429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.4018342429
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.3763703331
Short name T500
Test name
Test status
Simulation time 1538560039 ps
CPU time 6.67 seconds
Started Jan 17 02:39:45 PM PST 24
Finished Jan 17 02:39:57 PM PST 24
Peak memory 202460 kb
Host smart-57357d34-f800-43ab-92c6-2f53410af8dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763703331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3763703331
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.3271942896
Short name T386
Test name
Test status
Simulation time 15283672750 ps
CPU time 1728.58 seconds
Started Jan 17 02:39:43 PM PST 24
Finished Jan 17 03:08:38 PM PST 24
Peak memory 373904 kb
Host smart-cb5106b7-129f-4787-9843-2877915eace0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271942896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3271942896
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.1469617298
Short name T733
Test name
Test status
Simulation time 6805201412 ps
CPU time 115.38 seconds
Started Jan 17 02:39:27 PM PST 24
Finished Jan 17 02:41:27 PM PST 24
Peak memory 329936 kb
Host smart-d9524ced-d412-4e1a-a07d-9ae4728db813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469617298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1469617298
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3622092389
Short name T483
Test name
Test status
Simulation time 955169284 ps
CPU time 2634.49 seconds
Started Jan 17 02:39:45 PM PST 24
Finished Jan 17 03:23:46 PM PST 24
Peak memory 641652 kb
Host smart-a8e4db9e-a59e-43ce-91bd-a3f7d6e1bf7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3622092389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3622092389
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3345096990
Short name T945
Test name
Test status
Simulation time 2969089725 ps
CPU time 195.13 seconds
Started Jan 17 02:39:29 PM PST 24
Finished Jan 17 02:42:47 PM PST 24
Peak memory 201976 kb
Host smart-8c3867ac-ff2f-497c-a50e-f0021af86583
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345096990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.3345096990
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.4253608783
Short name T737
Test name
Test status
Simulation time 1175037931 ps
CPU time 46.49 seconds
Started Jan 17 02:39:33 PM PST 24
Finished Jan 17 02:40:21 PM PST 24
Peak memory 267512 kb
Host smart-b10e0b0b-47a7-4677-9c0c-148537580542
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253608783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.4253608783
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1005657171
Short name T780
Test name
Test status
Simulation time 18622260717 ps
CPU time 554.71 seconds
Started Jan 17 02:39:54 PM PST 24
Finished Jan 17 02:49:10 PM PST 24
Peak memory 358584 kb
Host smart-644e71e4-64cd-47ba-bec8-f43133126f47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005657171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.1005657171
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.1850504079
Short name T936
Test name
Test status
Simulation time 23691349 ps
CPU time 0.7 seconds
Started Jan 17 02:40:00 PM PST 24
Finished Jan 17 02:40:14 PM PST 24
Peak memory 201816 kb
Host smart-802fec62-9307-4a84-91b0-780be7a57885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850504079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.1850504079
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.633819828
Short name T878
Test name
Test status
Simulation time 260902386715 ps
CPU time 1200.05 seconds
Started Jan 17 02:39:49 PM PST 24
Finished Jan 17 02:59:52 PM PST 24
Peak memory 202160 kb
Host smart-3866160c-b841-4133-b6b1-9e89bc7361b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633819828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.
633819828
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.387598764
Short name T629
Test name
Test status
Simulation time 10934109097 ps
CPU time 721.91 seconds
Started Jan 17 02:39:55 PM PST 24
Finished Jan 17 02:51:59 PM PST 24
Peak memory 374920 kb
Host smart-ff14e8b5-c232-49e6-a250-cb12b5654afc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387598764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executabl
e.387598764
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3881839147
Short name T297
Test name
Test status
Simulation time 33318649402 ps
CPU time 88.46 seconds
Started Jan 17 02:39:54 PM PST 24
Finished Jan 17 02:41:24 PM PST 24
Peak memory 202216 kb
Host smart-2d9cfa75-1c94-443a-9ef3-ef3df62e7b1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881839147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3881839147
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.3834923363
Short name T274
Test name
Test status
Simulation time 783102505 ps
CPU time 110.1 seconds
Started Jan 17 02:39:54 PM PST 24
Finished Jan 17 02:41:45 PM PST 24
Peak memory 331952 kb
Host smart-ead7abd7-290e-41e9-bcca-ddea84e04060
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834923363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.3834923363
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2659041989
Short name T259
Test name
Test status
Simulation time 1582345931 ps
CPU time 128.61 seconds
Started Jan 17 02:40:01 PM PST 24
Finished Jan 17 02:42:24 PM PST 24
Peak memory 211436 kb
Host smart-53301692-3c50-4445-89cc-af3ad77d7497
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659041989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2659041989
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3329786563
Short name T157
Test name
Test status
Simulation time 7261593626 ps
CPU time 140.75 seconds
Started Jan 17 02:39:56 PM PST 24
Finished Jan 17 02:42:20 PM PST 24
Peak memory 202268 kb
Host smart-38760845-b574-44c0-8be5-2abe57b1ea99
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329786563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.3329786563
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.2084684534
Short name T978
Test name
Test status
Simulation time 19351379441 ps
CPU time 1193.52 seconds
Started Jan 17 02:39:50 PM PST 24
Finished Jan 17 02:59:46 PM PST 24
Peak memory 377972 kb
Host smart-e0480e2d-2595-49b3-ba0b-73590e0f9e10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084684534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.2084684534
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.652905368
Short name T506
Test name
Test status
Simulation time 4013594751 ps
CPU time 26.18 seconds
Started Jan 17 02:39:50 PM PST 24
Finished Jan 17 02:40:18 PM PST 24
Peak memory 246032 kb
Host smart-479e0d73-8b32-471b-b7f8-92085a7bdb6a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652905368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s
ram_ctrl_partial_access.652905368
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3260329289
Short name T827
Test name
Test status
Simulation time 12442577927 ps
CPU time 317.44 seconds
Started Jan 17 02:39:55 PM PST 24
Finished Jan 17 02:45:14 PM PST 24
Peak memory 202076 kb
Host smart-3d995649-a444-43cf-af46-f578c2cf1b45
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260329289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3260329289
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.595206659
Short name T10
Test name
Test status
Simulation time 1465163005 ps
CPU time 6.54 seconds
Started Jan 17 02:39:55 PM PST 24
Finished Jan 17 02:40:02 PM PST 24
Peak memory 202436 kb
Host smart-f245e530-8345-459c-9600-df9f4145ea49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595206659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.595206659
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.24971818
Short name T123
Test name
Test status
Simulation time 3287774663 ps
CPU time 2134.33 seconds
Started Jan 17 02:39:56 PM PST 24
Finished Jan 17 03:15:31 PM PST 24
Peak memory 381012 kb
Host smart-c709e0e2-96ae-4186-bc1b-1354fe737aae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24971818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.24971818
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1759887816
Short name T524
Test name
Test status
Simulation time 1412356953 ps
CPU time 72.25 seconds
Started Jan 17 02:39:44 PM PST 24
Finished Jan 17 02:41:02 PM PST 24
Peak memory 305388 kb
Host smart-cbdc9989-9f22-455a-950e-9b5ecbb98d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759887816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1759887816
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.298489516
Short name T616
Test name
Test status
Simulation time 1076970772768 ps
CPU time 2788.86 seconds
Started Jan 17 02:40:01 PM PST 24
Finished Jan 17 03:26:44 PM PST 24
Peak memory 383136 kb
Host smart-d0009018-ba01-426c-b577-fd281e1e4af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298489516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_stress_all.298489516
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.167318831
Short name T720
Test name
Test status
Simulation time 103535707 ps
CPU time 1838.63 seconds
Started Jan 17 02:40:00 PM PST 24
Finished Jan 17 03:10:54 PM PST 24
Peak memory 528720 kb
Host smart-3cc3cf67-a104-406d-b062-1e3fc0400e80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=167318831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.167318831
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1314854919
Short name T554
Test name
Test status
Simulation time 4668674864 ps
CPU time 347.68 seconds
Started Jan 17 02:39:50 PM PST 24
Finished Jan 17 02:45:40 PM PST 24
Peak memory 202092 kb
Host smart-bfe36fd1-4db0-4930-814d-6b8dda9ecd03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314854919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.1314854919
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.106410115
Short name T346
Test name
Test status
Simulation time 1340543500 ps
CPU time 26.49 seconds
Started Jan 17 02:39:56 PM PST 24
Finished Jan 17 02:40:25 PM PST 24
Peak memory 210352 kb
Host smart-ee1afa27-233f-4b96-a15c-2304623fa589
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106410115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.106410115
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3439344765
Short name T799
Test name
Test status
Simulation time 13649099709 ps
CPU time 1385.6 seconds
Started Jan 17 02:40:13 PM PST 24
Finished Jan 17 03:03:22 PM PST 24
Peak memory 379096 kb
Host smart-d7bc6dd2-6aeb-4ee2-a78f-36a9f96aaae6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439344765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.3439344765
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.2321311723
Short name T476
Test name
Test status
Simulation time 324590500112 ps
CPU time 2820.12 seconds
Started Jan 17 02:40:06 PM PST 24
Finished Jan 17 03:27:16 PM PST 24
Peak memory 201972 kb
Host smart-37e2963b-dea7-439b-bdb3-b0c580c7d2cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321311723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.2321311723
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3031317198
Short name T317
Test name
Test status
Simulation time 107853680854 ps
CPU time 132.46 seconds
Started Jan 17 02:40:13 PM PST 24
Finished Jan 17 02:42:29 PM PST 24
Peak memory 202204 kb
Host smart-faed8dfa-12c8-4e28-a0ce-4de3c02e5863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031317198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3031317198
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.251237369
Short name T630
Test name
Test status
Simulation time 2780432923 ps
CPU time 28.36 seconds
Started Jan 17 02:40:04 PM PST 24
Finished Jan 17 02:40:44 PM PST 24
Peak memory 210368 kb
Host smart-ed74380d-cf5c-406e-a332-2bee2917d382
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251237369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.sram_ctrl_max_throughput.251237369
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.813069323
Short name T880
Test name
Test status
Simulation time 5049271088 ps
CPU time 149.38 seconds
Started Jan 17 02:40:20 PM PST 24
Finished Jan 17 02:42:52 PM PST 24
Peak memory 211132 kb
Host smart-344c7146-e1b7-48df-94b6-349571237a43
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813069323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_mem_partial_access.813069323
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2153738923
Short name T674
Test name
Test status
Simulation time 99514033925 ps
CPU time 322.43 seconds
Started Jan 17 02:40:20 PM PST 24
Finished Jan 17 02:45:44 PM PST 24
Peak memory 202256 kb
Host smart-181c1d4d-2a23-4b64-ac7c-5773a7d5444e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153738923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2153738923
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.2461198938
Short name T920
Test name
Test status
Simulation time 9445524770 ps
CPU time 1290.83 seconds
Started Jan 17 02:40:08 PM PST 24
Finished Jan 17 03:01:46 PM PST 24
Peak memory 377096 kb
Host smart-58032dca-e897-432c-a50f-0d85db2c1a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461198938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.2461198938
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.2440427712
Short name T928
Test name
Test status
Simulation time 479842514 ps
CPU time 79.27 seconds
Started Jan 17 02:40:05 PM PST 24
Finished Jan 17 02:41:35 PM PST 24
Peak memory 315512 kb
Host smart-1962d68c-9e34-4204-a21d-f311691c01fe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440427712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.2440427712
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3980950910
Short name T955
Test name
Test status
Simulation time 4146866920 ps
CPU time 258.38 seconds
Started Jan 17 02:40:05 PM PST 24
Finished Jan 17 02:44:34 PM PST 24
Peak memory 202176 kb
Host smart-75d19772-bffa-4ca1-968c-d2a895cfc245
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980950910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.3980950910
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2052685590
Short name T972
Test name
Test status
Simulation time 363052508 ps
CPU time 6.71 seconds
Started Jan 17 02:40:20 PM PST 24
Finished Jan 17 02:40:28 PM PST 24
Peak memory 202420 kb
Host smart-8586e1ae-c7e9-46e7-8ecf-d7da29befda3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052685590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2052685590
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.501990632
Short name T141
Test name
Test status
Simulation time 1969830683 ps
CPU time 485.34 seconds
Started Jan 17 02:40:14 PM PST 24
Finished Jan 17 02:48:22 PM PST 24
Peak memory 375884 kb
Host smart-47221350-ebac-4a33-a5f5-6a892b6b3c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501990632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.501990632
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3472582107
Short name T810
Test name
Test status
Simulation time 4078151096 ps
CPU time 19.25 seconds
Started Jan 17 02:40:00 PM PST 24
Finished Jan 17 02:40:34 PM PST 24
Peak memory 202096 kb
Host smart-eb3d866b-49ec-47c4-9f54-d868d8ae5a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472582107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3472582107
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.591876536
Short name T788
Test name
Test status
Simulation time 19465020752 ps
CPU time 5263.58 seconds
Started Jan 17 02:40:20 PM PST 24
Finished Jan 17 04:08:05 PM PST 24
Peak memory 652876 kb
Host smart-883445c6-82e3-4761-9e12-89a70a4f0180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=591876536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.591876536
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.4207688246
Short name T119
Test name
Test status
Simulation time 6017595931 ps
CPU time 340.11 seconds
Started Jan 17 02:40:08 PM PST 24
Finished Jan 17 02:45:56 PM PST 24
Peak memory 202176 kb
Host smart-ba0e5e4c-afcf-45e9-a2a7-22163f5bae3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207688246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.4207688246
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2066474105
Short name T607
Test name
Test status
Simulation time 1537765831 ps
CPU time 102.97 seconds
Started Jan 17 02:40:04 PM PST 24
Finished Jan 17 02:41:58 PM PST 24
Peak memory 344508 kb
Host smart-4a79e7be-d38a-4065-89d9-0b92bfd0e60e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066474105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2066474105
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.48429264
Short name T599
Test name
Test status
Simulation time 13312841837 ps
CPU time 553.23 seconds
Started Jan 17 02:40:29 PM PST 24
Finished Jan 17 02:49:44 PM PST 24
Peak memory 379912 kb
Host smart-03ed1bde-884f-4e7f-bfaf-f1f519be1724
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48429264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.sram_ctrl_access_during_key_req.48429264
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.3385468921
Short name T866
Test name
Test status
Simulation time 23969967 ps
CPU time 0.63 seconds
Started Jan 17 02:40:37 PM PST 24
Finished Jan 17 02:40:46 PM PST 24
Peak memory 201356 kb
Host smart-faddade7-75a7-46a0-baf0-76eb3cf3cc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385468921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.3385468921
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.106604547
Short name T551
Test name
Test status
Simulation time 411602390671 ps
CPU time 968.37 seconds
Started Jan 17 02:40:20 PM PST 24
Finished Jan 17 02:56:31 PM PST 24
Peak memory 210332 kb
Host smart-3ce20961-6d89-4378-bacb-8ee25019d771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106604547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.
106604547
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.3043236668
Short name T823
Test name
Test status
Simulation time 43104437608 ps
CPU time 2093.91 seconds
Started Jan 17 02:41:19 PM PST 24
Finished Jan 17 03:16:17 PM PST 24
Peak memory 379092 kb
Host smart-a3fb624f-7655-4567-a207-4df1cf4c50bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043236668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.3043236668
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.2596769042
Short name T981
Test name
Test status
Simulation time 10755211300 ps
CPU time 134.49 seconds
Started Jan 17 02:40:30 PM PST 24
Finished Jan 17 02:42:45 PM PST 24
Peak memory 355544 kb
Host smart-e5c3900c-74aa-4c70-8c98-268aba40d076
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596769042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.2596769042
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.483084988
Short name T145
Test name
Test status
Simulation time 4978085682 ps
CPU time 148.25 seconds
Started Jan 17 02:40:38 PM PST 24
Finished Jan 17 02:43:14 PM PST 24
Peak memory 214512 kb
Host smart-bee6a2fc-ff4d-4106-9a41-6e779613de93
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483084988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.sram_ctrl_mem_partial_access.483084988
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.2730720606
Short name T773
Test name
Test status
Simulation time 23187253153 ps
CPU time 251.05 seconds
Started Jan 17 02:40:38 PM PST 24
Finished Jan 17 02:44:57 PM PST 24
Peak memory 202292 kb
Host smart-f9a1fcec-1d53-4204-8865-700a4a428ab5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730720606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.2730720606
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.2886921973
Short name T914
Test name
Test status
Simulation time 74974796671 ps
CPU time 886.94 seconds
Started Jan 17 02:40:19 PM PST 24
Finished Jan 17 02:55:07 PM PST 24
Peak memory 377076 kb
Host smart-354d5c5b-64e7-4799-a728-1c78c6f084c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886921973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.2886921973
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.2683581596
Short name T845
Test name
Test status
Simulation time 3217916878 ps
CPU time 24.71 seconds
Started Jan 17 02:40:22 PM PST 24
Finished Jan 17 02:40:48 PM PST 24
Peak memory 201964 kb
Host smart-cf94e52f-afbf-45ef-8865-14c2d33fbaa6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683581596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.2683581596
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1787570575
Short name T323
Test name
Test status
Simulation time 31572333676 ps
CPU time 221.16 seconds
Started Jan 17 02:40:30 PM PST 24
Finished Jan 17 02:44:12 PM PST 24
Peak memory 202096 kb
Host smart-b0e4beba-ef5f-4557-8cfc-b4706892c1cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787570575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.1787570575
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.3540158323
Short name T46
Test name
Test status
Simulation time 350944116 ps
CPU time 6.03 seconds
Started Jan 17 02:40:39 PM PST 24
Finished Jan 17 02:40:52 PM PST 24
Peak memory 202364 kb
Host smart-e243216a-dd53-4e21-854f-a9a17aab8134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540158323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3540158323
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.3732522756
Short name T413
Test name
Test status
Simulation time 30855555783 ps
CPU time 1148.45 seconds
Started Jan 17 02:40:28 PM PST 24
Finished Jan 17 02:59:37 PM PST 24
Peak memory 379124 kb
Host smart-6bdca3a5-5c89-4099-bd8f-3e6ecce115ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732522756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3732522756
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1369411567
Short name T659
Test name
Test status
Simulation time 2603115036 ps
CPU time 22.32 seconds
Started Jan 17 02:40:20 PM PST 24
Finished Jan 17 02:40:44 PM PST 24
Peak memory 240344 kb
Host smart-e9108dd9-4769-44bd-b476-fdfc9b080d82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369411567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1369411567
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.3614445196
Short name T906
Test name
Test status
Simulation time 369638129097 ps
CPU time 4948.8 seconds
Started Jan 17 02:40:38 PM PST 24
Finished Jan 17 04:03:15 PM PST 24
Peak memory 385440 kb
Host smart-826ea35a-9cf6-4cf7-8b37-7997953de432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614445196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.3614445196
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2504828028
Short name T692
Test name
Test status
Simulation time 2011875191 ps
CPU time 2748.66 seconds
Started Jan 17 02:40:36 PM PST 24
Finished Jan 17 03:26:35 PM PST 24
Peak memory 603428 kb
Host smart-7e513f46-b3ab-4379-a2ca-d0785225cbd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2504828028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2504828028
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1955765303
Short name T557
Test name
Test status
Simulation time 8722234368 ps
CPU time 182.02 seconds
Started Jan 17 02:40:23 PM PST 24
Finished Jan 17 02:43:26 PM PST 24
Peak memory 202092 kb
Host smart-8f254d41-db90-4645-aae6-00c29b4f72d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955765303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.1955765303
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3824840943
Short name T568
Test name
Test status
Simulation time 697262873 ps
CPU time 33.67 seconds
Started Jan 17 02:40:28 PM PST 24
Finished Jan 17 02:41:03 PM PST 24
Peak memory 234836 kb
Host smart-c891395c-8c5b-436f-82af-7cca9c0ae99e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824840943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3824840943
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.786770278
Short name T947
Test name
Test status
Simulation time 9298607842 ps
CPU time 1036.48 seconds
Started Jan 17 02:40:55 PM PST 24
Finished Jan 17 02:58:14 PM PST 24
Peak memory 380120 kb
Host smart-97096bce-bf79-4c44-88d0-869c388a8e7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786770278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.sram_ctrl_access_during_key_req.786770278
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.1164734470
Short name T28
Test name
Test status
Simulation time 20074763 ps
CPU time 0.66 seconds
Started Jan 17 02:40:53 PM PST 24
Finished Jan 17 02:40:57 PM PST 24
Peak memory 201888 kb
Host smart-b87f4a2f-e24a-43fe-b9a0-4c6243ee97af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164734470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.1164734470
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.2086670703
Short name T754
Test name
Test status
Simulation time 83339617029 ps
CPU time 1410.76 seconds
Started Jan 17 02:40:38 PM PST 24
Finished Jan 17 03:04:17 PM PST 24
Peak memory 202028 kb
Host smart-5d1a962e-5965-4681-a279-81fd8cb5bed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086670703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.2086670703
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.2668464107
Short name T289
Test name
Test status
Simulation time 746449583 ps
CPU time 61.47 seconds
Started Jan 17 02:40:48 PM PST 24
Finished Jan 17 02:41:57 PM PST 24
Peak memory 293272 kb
Host smart-9e018261-5850-4457-ba59-f0d635101d3a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668464107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.2668464107
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.524439996
Short name T73
Test name
Test status
Simulation time 5054864130 ps
CPU time 148.87 seconds
Started Jan 17 02:40:53 PM PST 24
Finished Jan 17 02:43:26 PM PST 24
Peak memory 211636 kb
Host smart-3fe7b180-cdc9-40f6-9923-8b60162eb3fe
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524439996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.524439996
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.347338544
Short name T298
Test name
Test status
Simulation time 187863297326 ps
CPU time 323.56 seconds
Started Jan 17 02:40:53 PM PST 24
Finished Jan 17 02:46:20 PM PST 24
Peak memory 202164 kb
Host smart-a2a61249-c534-43ea-8b42-342eedf45ebf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347338544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_mem_walk.347338544
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.1391154750
Short name T278
Test name
Test status
Simulation time 40165065422 ps
CPU time 368.84 seconds
Started Jan 17 02:40:39 PM PST 24
Finished Jan 17 02:46:55 PM PST 24
Peak memory 379036 kb
Host smart-05e29c47-72bb-40be-9ecc-9a950929cea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391154750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.1391154750
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.429168525
Short name T816
Test name
Test status
Simulation time 5634167627 ps
CPU time 21.88 seconds
Started Jan 17 02:40:50 PM PST 24
Finished Jan 17 02:41:18 PM PST 24
Peak memory 201984 kb
Host smart-beb6a337-ecd6-4190-ac62-72f4997be6f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429168525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s
ram_ctrl_partial_access.429168525
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2660488783
Short name T975
Test name
Test status
Simulation time 44894737180 ps
CPU time 365.71 seconds
Started Jan 17 02:40:50 PM PST 24
Finished Jan 17 02:47:02 PM PST 24
Peak memory 202168 kb
Host smart-8df68a7d-69ca-4ae2-a7e3-b19d7204d0de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660488783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.2660488783
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.3018953408
Short name T690
Test name
Test status
Simulation time 1347090216 ps
CPU time 14.09 seconds
Started Jan 17 02:40:55 PM PST 24
Finished Jan 17 02:41:11 PM PST 24
Peak memory 202392 kb
Host smart-0dce9c66-68e4-46ff-8b1d-7972b01b51ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018953408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3018953408
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.1546811334
Short name T399
Test name
Test status
Simulation time 9341328415 ps
CPU time 783.64 seconds
Started Jan 17 02:40:54 PM PST 24
Finished Jan 17 02:54:01 PM PST 24
Peak memory 373900 kb
Host smart-f6ffaad2-965e-45cd-9018-889b9e229de6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546811334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1546811334
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.1405107629
Short name T369
Test name
Test status
Simulation time 683209022 ps
CPU time 41.49 seconds
Started Jan 17 02:40:37 PM PST 24
Finished Jan 17 02:41:27 PM PST 24
Peak memory 280816 kb
Host smart-501dca97-dc63-47ad-8e65-7fac8601b664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405107629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1405107629
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2368809299
Short name T314
Test name
Test status
Simulation time 6092931120 ps
CPU time 5255.75 seconds
Started Jan 17 02:40:54 PM PST 24
Finished Jan 17 04:08:33 PM PST 24
Peak memory 809488 kb
Host smart-ec929c04-f939-4682-9bd3-de61d5e9f9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2368809299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2368809299
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.703323756
Short name T324
Test name
Test status
Simulation time 22299522290 ps
CPU time 470.23 seconds
Started Jan 17 02:40:37 PM PST 24
Finished Jan 17 02:48:36 PM PST 24
Peak memory 202164 kb
Host smart-2c99b543-7b14-4937-bb71-1aef26a9178b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703323756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.703323756
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.586925407
Short name T856
Test name
Test status
Simulation time 998761129 ps
CPU time 25.77 seconds
Started Jan 17 02:40:49 PM PST 24
Finished Jan 17 02:41:22 PM PST 24
Peak memory 210352 kb
Host smart-cc63d1cc-7f6d-41a3-8db4-5e585fde743c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586925407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.586925407
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.415911865
Short name T517
Test name
Test status
Simulation time 16744101306 ps
CPU time 469.25 seconds
Started Jan 17 02:41:01 PM PST 24
Finished Jan 17 02:49:06 PM PST 24
Peak memory 362604 kb
Host smart-432d6c39-0b83-4bd5-a200-37d79507be0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415911865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.sram_ctrl_access_during_key_req.415911865
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.4175836123
Short name T567
Test name
Test status
Simulation time 23375253 ps
CPU time 0.69 seconds
Started Jan 17 02:41:19 PM PST 24
Finished Jan 17 02:41:24 PM PST 24
Peak memory 201788 kb
Host smart-6092a7f4-2eac-4cf1-8f22-8c877d161525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175836123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.4175836123
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.3354943718
Short name T411
Test name
Test status
Simulation time 27447870074 ps
CPU time 976.89 seconds
Started Jan 17 02:41:01 PM PST 24
Finished Jan 17 02:57:34 PM PST 24
Peak memory 202160 kb
Host smart-552b574c-2c94-4543-a829-cdfc35024997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354943718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.3354943718
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1878745261
Short name T757
Test name
Test status
Simulation time 40209668652 ps
CPU time 488.42 seconds
Started Jan 17 02:41:10 PM PST 24
Finished Jan 17 02:49:25 PM PST 24
Peak memory 372788 kb
Host smart-69363098-1b20-4247-9cbc-b7b192c94b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878745261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1878745261
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.156832464
Short name T925
Test name
Test status
Simulation time 38546360521 ps
CPU time 120.27 seconds
Started Jan 17 02:41:02 PM PST 24
Finished Jan 17 02:43:17 PM PST 24
Peak memory 213724 kb
Host smart-5ee59dc6-c631-42a0-9f48-cd8709e0c764
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156832464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc
alation.156832464
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1262955537
Short name T961
Test name
Test status
Simulation time 762872185 ps
CPU time 73.87 seconds
Started Jan 17 02:41:02 PM PST 24
Finished Jan 17 02:42:31 PM PST 24
Peak memory 314512 kb
Host smart-19a6dab3-a89c-4622-8476-457268a02451
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262955537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1262955537
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.4290660095
Short name T285
Test name
Test status
Simulation time 1552138817 ps
CPU time 129.2 seconds
Started Jan 17 02:41:12 PM PST 24
Finished Jan 17 02:43:26 PM PST 24
Peak memory 213740 kb
Host smart-c7a01e57-3069-4d6b-a5a1-5cb9334a9fda
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290660095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.4290660095
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.2251433399
Short name T17
Test name
Test status
Simulation time 3873755401 ps
CPU time 122.87 seconds
Started Jan 17 02:41:09 PM PST 24
Finished Jan 17 02:43:20 PM PST 24
Peak memory 202136 kb
Host smart-0e8e054f-17b8-485a-aa70-27be3d73e327
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251433399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.2251433399
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.2927350998
Short name T441
Test name
Test status
Simulation time 5883664413 ps
CPU time 673.11 seconds
Started Jan 17 02:40:54 PM PST 24
Finished Jan 17 02:52:10 PM PST 24
Peak memory 354660 kb
Host smart-c630dda4-f883-4eb2-9b33-8f3db3601d13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927350998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.2927350998
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.1757029195
Short name T881
Test name
Test status
Simulation time 720734400 ps
CPU time 14.01 seconds
Started Jan 17 02:41:03 PM PST 24
Finished Jan 17 02:41:31 PM PST 24
Peak memory 202084 kb
Host smart-ed923415-22bb-41ad-9846-57074fa5a536
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757029195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.1757029195
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.569454194
Short name T448
Test name
Test status
Simulation time 846862916 ps
CPU time 14.18 seconds
Started Jan 17 02:41:11 PM PST 24
Finished Jan 17 02:41:31 PM PST 24
Peak memory 202404 kb
Host smart-f0e18b9f-39c6-4d62-8af9-ccedd3dd72eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569454194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.569454194
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.2132820266
Short name T367
Test name
Test status
Simulation time 36168442512 ps
CPU time 1397.93 seconds
Started Jan 17 02:41:11 PM PST 24
Finished Jan 17 03:04:35 PM PST 24
Peak memory 371932 kb
Host smart-176dfc6d-6dad-4c7d-8771-d5bfd0c7b935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132820266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2132820266
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.1315342530
Short name T707
Test name
Test status
Simulation time 7449119214 ps
CPU time 7.79 seconds
Started Jan 17 02:40:53 PM PST 24
Finished Jan 17 02:41:04 PM PST 24
Peak memory 202080 kb
Host smart-53b8cf83-02c7-4ccf-bd05-bd9ed4353403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315342530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1315342530
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.4052991478
Short name T269
Test name
Test status
Simulation time 4384630040 ps
CPU time 305.65 seconds
Started Jan 17 02:41:00 PM PST 24
Finished Jan 17 02:46:23 PM PST 24
Peak memory 202152 kb
Host smart-9bf731bc-801b-467c-a36e-d0b52f662d36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052991478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.4052991478
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1094081920
Short name T675
Test name
Test status
Simulation time 2883001118 ps
CPU time 89.56 seconds
Started Jan 17 02:41:01 PM PST 24
Finished Jan 17 02:42:46 PM PST 24
Peak memory 320852 kb
Host smart-6c8c9370-f0c7-4c2a-bd21-aa6aee658386
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094081920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1094081920
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3957776847
Short name T83
Test name
Test status
Simulation time 36012497550 ps
CPU time 871.14 seconds
Started Jan 17 02:32:59 PM PST 24
Finished Jan 17 02:47:33 PM PST 24
Peak memory 368868 kb
Host smart-acb7f1aa-0df6-400b-bea8-8981d81128c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957776847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.3957776847
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.2166954920
Short name T622
Test name
Test status
Simulation time 24604387 ps
CPU time 0.67 seconds
Started Jan 17 02:38:02 PM PST 24
Finished Jan 17 02:38:06 PM PST 24
Peak memory 201712 kb
Host smart-03cbee48-1059-49f1-abcd-e6c43cbc327f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166954920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.2166954920
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.2152576117
Short name T830
Test name
Test status
Simulation time 25351542869 ps
CPU time 1766.76 seconds
Started Jan 17 02:34:10 PM PST 24
Finished Jan 17 03:03:38 PM PST 24
Peak memory 202148 kb
Host smart-77763d23-bf8f-4a47-bde4-7315cff1a023
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152576117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2152576117
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.2041723851
Short name T673
Test name
Test status
Simulation time 28808267040 ps
CPU time 988.5 seconds
Started Jan 17 02:32:34 PM PST 24
Finished Jan 17 02:49:06 PM PST 24
Peak memory 377984 kb
Host smart-d8899e04-fe49-45e0-aedd-ed79bbd474e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041723851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.2041723851
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.658380781
Short name T313
Test name
Test status
Simulation time 755325676 ps
CPU time 110.21 seconds
Started Jan 17 02:32:33 PM PST 24
Finished Jan 17 02:34:28 PM PST 24
Peak memory 333008 kb
Host smart-28579a5f-acd5-43ec-b132-096061287563
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658380781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.sram_ctrl_max_throughput.658380781
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.235468218
Short name T427
Test name
Test status
Simulation time 2487278924 ps
CPU time 87.53 seconds
Started Jan 17 02:32:34 PM PST 24
Finished Jan 17 02:34:05 PM PST 24
Peak memory 211244 kb
Host smart-49942d43-271b-48dc-a028-9bdca8c8bf67
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235468218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
sram_ctrl_mem_partial_access.235468218
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.842795187
Short name T882
Test name
Test status
Simulation time 6959257734 ps
CPU time 142.43 seconds
Started Jan 17 02:33:11 PM PST 24
Finished Jan 17 02:35:40 PM PST 24
Peak memory 202348 kb
Host smart-58ced532-359e-4ea5-b0ed-4080a7299c37
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842795187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
mem_walk.842795187
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.3816087927
Short name T842
Test name
Test status
Simulation time 21215268820 ps
CPU time 1507.47 seconds
Started Jan 17 02:32:25 PM PST 24
Finished Jan 17 02:57:35 PM PST 24
Peak memory 380132 kb
Host smart-8006e2cc-dbe8-4bbf-891e-37d272e4657c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816087927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.3816087927
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.2590895415
Short name T897
Test name
Test status
Simulation time 5476082577 ps
CPU time 38.67 seconds
Started Jan 17 02:34:18 PM PST 24
Finished Jan 17 02:34:58 PM PST 24
Peak memory 202144 kb
Host smart-bd23ad59-a132-40ba-b549-a0c9812aa901
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590895415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.2590895415
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1190114786
Short name T256
Test name
Test status
Simulation time 6198425568 ps
CPU time 382.69 seconds
Started Jan 17 02:32:31 PM PST 24
Finished Jan 17 02:39:00 PM PST 24
Peak memory 202204 kb
Host smart-caffb230-54a4-47ca-99e0-f19454a4c99a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190114786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.1190114786
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3287854896
Short name T295
Test name
Test status
Simulation time 2238894268 ps
CPU time 14.81 seconds
Started Jan 17 02:33:40 PM PST 24
Finished Jan 17 02:33:55 PM PST 24
Peak memory 202484 kb
Host smart-02790aa4-24c9-4b14-9cad-8c707a15235d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287854896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3287854896
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1411389218
Short name T51
Test name
Test status
Simulation time 12690539663 ps
CPU time 1076.56 seconds
Started Jan 17 02:32:51 PM PST 24
Finished Jan 17 02:50:49 PM PST 24
Peak memory 367852 kb
Host smart-5277315e-bce2-4a52-bca1-d9c2af854471
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411389218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1411389218
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.2328294021
Short name T30
Test name
Test status
Simulation time 144297796 ps
CPU time 1.97 seconds
Started Jan 17 02:34:04 PM PST 24
Finished Jan 17 02:34:09 PM PST 24
Peak memory 221080 kb
Host smart-e225891c-1c82-4485-b5cd-def4a636ae2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328294021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.2328294021
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2910906014
Short name T578
Test name
Test status
Simulation time 1397565611 ps
CPU time 15.59 seconds
Started Jan 17 02:32:47 PM PST 24
Finished Jan 17 02:33:06 PM PST 24
Peak memory 202088 kb
Host smart-d2a21675-2db9-4edc-93d1-1a292b0dd51f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910906014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2910906014
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.3519265984
Short name T25
Test name
Test status
Simulation time 57093119360 ps
CPU time 3600.57 seconds
Started Jan 17 02:37:37 PM PST 24
Finished Jan 17 03:37:43 PM PST 24
Peak memory 378024 kb
Host smart-3831737e-e836-4316-83d0-6d50b3c8132a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519265984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.3519265984
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1754531085
Short name T36
Test name
Test status
Simulation time 7144165778 ps
CPU time 3389.88 seconds
Started Jan 17 02:33:30 PM PST 24
Finished Jan 17 03:30:00 PM PST 24
Peak memory 514180 kb
Host smart-7e06e1b9-ca79-4c4f-a71c-fbdba14fa97a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1754531085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1754531085
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2434647539
Short name T485
Test name
Test status
Simulation time 4479737723 ps
CPU time 329.65 seconds
Started Jan 17 02:32:27 PM PST 24
Finished Jan 17 02:37:59 PM PST 24
Peak memory 202152 kb
Host smart-1e7ab98d-2a72-4a9f-a10b-818a0bdff01a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434647539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.2434647539
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.709712565
Short name T651
Test name
Test status
Simulation time 5445578827 ps
CPU time 44.77 seconds
Started Jan 17 02:35:37 PM PST 24
Finished Jan 17 02:36:28 PM PST 24
Peak memory 267672 kb
Host smart-787ebe61-869b-42fa-8705-c4bdaccb0add
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709712565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.709712565
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2332825405
Short name T857
Test name
Test status
Simulation time 31900573144 ps
CPU time 1302.93 seconds
Started Jan 17 02:41:24 PM PST 24
Finished Jan 17 03:03:08 PM PST 24
Peak memory 377088 kb
Host smart-afb0c4ff-e4a0-4abc-9aa6-37ecd24a7801
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332825405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.2332825405
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.2474951804
Short name T783
Test name
Test status
Simulation time 19794994 ps
CPU time 0.7 seconds
Started Jan 17 02:41:41 PM PST 24
Finished Jan 17 02:41:43 PM PST 24
Peak memory 201840 kb
Host smart-c958368b-ab3a-42e6-9a21-3d5240e61cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474951804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.2474951804
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.3537284763
Short name T281
Test name
Test status
Simulation time 19286094871 ps
CPU time 1321.55 seconds
Started Jan 17 02:41:21 PM PST 24
Finished Jan 17 03:03:26 PM PST 24
Peak memory 202160 kb
Host smart-d0aae295-4d43-4e2d-bc06-640207d72720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537284763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.3537284763
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.3663128900
Short name T736
Test name
Test status
Simulation time 1990788308 ps
CPU time 238.19 seconds
Started Jan 17 02:41:31 PM PST 24
Finished Jan 17 02:45:30 PM PST 24
Peak memory 371764 kb
Host smart-d38f487e-aa3d-485f-affd-e721e85aa5f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663128900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.3663128900
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.4008574309
Short name T902
Test name
Test status
Simulation time 15840007936 ps
CPU time 153.15 seconds
Started Jan 17 02:41:24 PM PST 24
Finished Jan 17 02:43:59 PM PST 24
Peak memory 210428 kb
Host smart-82469bd9-0d00-49ea-9f0f-c6cb0714d616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008574309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.4008574309
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.1302415387
Short name T901
Test name
Test status
Simulation time 1435741884 ps
CPU time 40.82 seconds
Started Jan 17 02:41:19 PM PST 24
Finished Jan 17 02:42:04 PM PST 24
Peak memory 257416 kb
Host smart-e46084fb-e9b5-40f1-817d-e6dc797aad91
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302415387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.1302415387
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.145620826
Short name T82
Test name
Test status
Simulation time 6196804011 ps
CPU time 138.14 seconds
Started Jan 17 02:41:33 PM PST 24
Finished Jan 17 02:43:52 PM PST 24
Peak memory 214428 kb
Host smart-ba0e35d0-db2b-41ed-b8b9-5ac3312d75ff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145620826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.sram_ctrl_mem_partial_access.145620826
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.3686548857
Short name T460
Test name
Test status
Simulation time 15766799851 ps
CPU time 251 seconds
Started Jan 17 02:41:33 PM PST 24
Finished Jan 17 02:45:45 PM PST 24
Peak memory 202240 kb
Host smart-d3f1296f-a383-4a22-a109-5bdd5bfae7da
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686548857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.3686548857
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.1102337447
Short name T666
Test name
Test status
Simulation time 10407049436 ps
CPU time 63.96 seconds
Started Jan 17 02:41:22 PM PST 24
Finished Jan 17 02:42:29 PM PST 24
Peak memory 252532 kb
Host smart-2c5af804-12f4-4d87-b62c-99ff60ca7412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102337447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.1102337447
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.601019795
Short name T267
Test name
Test status
Simulation time 1085503517 ps
CPU time 122.96 seconds
Started Jan 17 02:41:20 PM PST 24
Finished Jan 17 02:43:26 PM PST 24
Peak memory 350344 kb
Host smart-21695c5b-dc91-475e-92ab-cb161767ae0f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601019795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.s
ram_ctrl_partial_access.601019795
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3384437081
Short name T672
Test name
Test status
Simulation time 41948176404 ps
CPU time 344.03 seconds
Started Jan 17 02:41:14 PM PST 24
Finished Jan 17 02:47:03 PM PST 24
Peak memory 202164 kb
Host smart-2a4eb2db-6c0e-4e3e-897b-6583c3b8ca68
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384437081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.3384437081
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.2205300156
Short name T618
Test name
Test status
Simulation time 1530268569 ps
CPU time 14.67 seconds
Started Jan 17 02:41:34 PM PST 24
Finished Jan 17 02:41:50 PM PST 24
Peak memory 202288 kb
Host smart-09d08de4-7760-4d5a-8409-cd4a7561591e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205300156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2205300156
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.4082768013
Short name T124
Test name
Test status
Simulation time 4681159991 ps
CPU time 944.44 seconds
Started Jan 17 02:41:34 PM PST 24
Finished Jan 17 02:57:19 PM PST 24
Peak memory 373716 kb
Host smart-9436175b-c54f-48ce-a5d5-001c2fbd4581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082768013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4082768013
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.3460523527
Short name T654
Test name
Test status
Simulation time 1868379340 ps
CPU time 26.26 seconds
Started Jan 17 02:41:20 PM PST 24
Finished Jan 17 02:41:50 PM PST 24
Peak memory 266480 kb
Host smart-5b18ff38-4a06-4238-bc8f-4297bcfdf49e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460523527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3460523527
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.726685533
Short name T56
Test name
Test status
Simulation time 459524785 ps
CPU time 2533.19 seconds
Started Jan 17 02:41:41 PM PST 24
Finished Jan 17 03:23:55 PM PST 24
Peak memory 772760 kb
Host smart-e9ff1599-e002-4d21-99fc-4618bf3bf619
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=726685533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.726685533
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3694142456
Short name T434
Test name
Test status
Simulation time 20142948292 ps
CPU time 351.58 seconds
Started Jan 17 02:41:20 PM PST 24
Finished Jan 17 02:47:15 PM PST 24
Peak memory 202144 kb
Host smart-7f2536b3-caec-4339-b0c6-342f7ae87c0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694142456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.3694142456
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2902573157
Short name T332
Test name
Test status
Simulation time 720430700 ps
CPU time 47.5 seconds
Started Jan 17 02:41:25 PM PST 24
Finished Jan 17 02:42:13 PM PST 24
Peak memory 271820 kb
Host smart-2b7472ec-2470-4c1f-9e9c-5e046436d500
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902573157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2902573157
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2334161912
Short name T625
Test name
Test status
Simulation time 9602840248 ps
CPU time 837.59 seconds
Started Jan 17 02:41:57 PM PST 24
Finished Jan 17 02:55:55 PM PST 24
Peak memory 378840 kb
Host smart-9fe7620b-084d-4252-a5ae-dca9e43ca587
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334161912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.2334161912
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.1008571920
Short name T555
Test name
Test status
Simulation time 14907386 ps
CPU time 0.65 seconds
Started Jan 17 02:41:56 PM PST 24
Finished Jan 17 02:41:58 PM PST 24
Peak memory 201872 kb
Host smart-43dc4ff4-3aba-48c7-8b8d-492626b061a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008571920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.1008571920
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.1759453397
Short name T375
Test name
Test status
Simulation time 173466436198 ps
CPU time 952.66 seconds
Started Jan 17 02:41:42 PM PST 24
Finished Jan 17 02:57:35 PM PST 24
Peak memory 202204 kb
Host smart-405c73a8-3157-4751-a728-816ea34d5898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759453397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.1759453397
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.294456790
Short name T694
Test name
Test status
Simulation time 1454646747 ps
CPU time 27.43 seconds
Started Jan 17 02:41:56 PM PST 24
Finished Jan 17 02:42:25 PM PST 24
Peak memory 211320 kb
Host smart-02bfe80d-5cec-4d47-803b-35d03ce10ec1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294456790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.sram_ctrl_max_throughput.294456790
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2944185531
Short name T943
Test name
Test status
Simulation time 4334481288 ps
CPU time 75.84 seconds
Started Jan 17 02:41:56 PM PST 24
Finished Jan 17 02:43:13 PM PST 24
Peak memory 218536 kb
Host smart-c44131e9-35e5-4a80-aff0-2d66e256e4b0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944185531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2944185531
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.1342159208
Short name T818
Test name
Test status
Simulation time 41251930432 ps
CPU time 161.57 seconds
Started Jan 17 02:41:58 PM PST 24
Finished Jan 17 02:44:40 PM PST 24
Peak memory 202440 kb
Host smart-edb62136-3254-4ad0-b1d5-3cebca9a9d9c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342159208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.1342159208
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.3167247031
Short name T508
Test name
Test status
Simulation time 65213762123 ps
CPU time 1163.26 seconds
Started Jan 17 02:41:41 PM PST 24
Finished Jan 17 03:01:05 PM PST 24
Peak memory 366452 kb
Host smart-b7a90189-893b-49a4-b51e-a94418dbf72a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167247031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.3167247031
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.1733565007
Short name T679
Test name
Test status
Simulation time 864235533 ps
CPU time 19.19 seconds
Started Jan 17 02:41:42 PM PST 24
Finished Jan 17 02:42:02 PM PST 24
Peak memory 228276 kb
Host smart-a4b87866-9313-4912-aa89-fbfee802258e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733565007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.1733565007
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1325105903
Short name T148
Test name
Test status
Simulation time 17841839864 ps
CPU time 388.08 seconds
Started Jan 17 02:41:48 PM PST 24
Finished Jan 17 02:48:17 PM PST 24
Peak memory 202108 kb
Host smart-0f643b2d-30f4-422d-8482-da2709e68954
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325105903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.1325105903
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.259660668
Short name T808
Test name
Test status
Simulation time 345560856 ps
CPU time 13.93 seconds
Started Jan 17 02:41:59 PM PST 24
Finished Jan 17 02:42:13 PM PST 24
Peak memory 202336 kb
Host smart-95af82ec-a0a4-4c94-b880-dfef88fafce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259660668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.259660668
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2663606176
Short name T311
Test name
Test status
Simulation time 18623526842 ps
CPU time 1263.61 seconds
Started Jan 17 02:41:58 PM PST 24
Finished Jan 17 03:03:02 PM PST 24
Peak memory 372800 kb
Host smart-64d35a60-d70b-4e2d-a2af-18b336b5adfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663606176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2663606176
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.2999438002
Short name T735
Test name
Test status
Simulation time 2267529168 ps
CPU time 29.93 seconds
Started Jan 17 02:41:41 PM PST 24
Finished Jan 17 02:42:11 PM PST 24
Peak memory 202104 kb
Host smart-af0efc19-6c23-4235-bfe1-656b2f593285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999438002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2999438002
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.803643354
Short name T779
Test name
Test status
Simulation time 56972452090 ps
CPU time 4284.68 seconds
Started Jan 17 02:41:57 PM PST 24
Finished Jan 17 03:53:23 PM PST 24
Peak memory 381192 kb
Host smart-0150db34-e868-4b8f-bf65-dcb92539e9f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803643354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_stress_all.803643354
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2336857302
Short name T347
Test name
Test status
Simulation time 4110297551 ps
CPU time 5283.72 seconds
Started Jan 17 02:41:56 PM PST 24
Finished Jan 17 04:10:02 PM PST 24
Peak memory 729092 kb
Host smart-4ec91c81-b650-4ccf-9ab7-9baf0e86b07f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2336857302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2336857302
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1150167952
Short name T19
Test name
Test status
Simulation time 6001471737 ps
CPU time 201.44 seconds
Started Jan 17 02:41:41 PM PST 24
Finished Jan 17 02:45:04 PM PST 24
Peak memory 201976 kb
Host smart-f782d4ae-736d-4bb1-8ac3-c54aa002a156
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150167952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.1150167952
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1024737005
Short name T647
Test name
Test status
Simulation time 2144083087 ps
CPU time 93.44 seconds
Started Jan 17 02:41:58 PM PST 24
Finished Jan 17 02:43:32 PM PST 24
Peak memory 321708 kb
Host smart-03f66b13-620a-4c7f-a0f2-ad0cf9832a91
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024737005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1024737005
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3038507224
Short name T21
Test name
Test status
Simulation time 6036719534 ps
CPU time 871.62 seconds
Started Jan 17 02:42:08 PM PST 24
Finished Jan 17 02:56:43 PM PST 24
Peak memory 371932 kb
Host smart-ba1c1466-c7a5-46c6-8fb1-dc85697582f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038507224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.3038507224
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.559172919
Short name T813
Test name
Test status
Simulation time 14304844 ps
CPU time 0.71 seconds
Started Jan 17 02:42:25 PM PST 24
Finished Jan 17 02:42:27 PM PST 24
Peak memory 201804 kb
Host smart-55d75518-b198-4f44-92f0-093d8e8a871f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559172919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.559172919
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.1160514137
Short name T655
Test name
Test status
Simulation time 23944744600 ps
CPU time 1730.52 seconds
Started Jan 17 02:42:01 PM PST 24
Finished Jan 17 03:10:53 PM PST 24
Peak memory 202180 kb
Host smart-cd9d4639-c42f-4a99-9a93-4fa0ae0b4324
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160514137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.1160514137
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1160042183
Short name T739
Test name
Test status
Simulation time 709517272 ps
CPU time 36.84 seconds
Started Jan 17 02:42:08 PM PST 24
Finished Jan 17 02:42:47 PM PST 24
Peak memory 252272 kb
Host smart-69592520-00b1-427f-b79b-defdc1c93350
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160042183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1160042183
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3067446075
Short name T144
Test name
Test status
Simulation time 2461296717 ps
CPU time 85.94 seconds
Started Jan 17 02:42:09 PM PST 24
Finished Jan 17 02:43:37 PM PST 24
Peak memory 211460 kb
Host smart-7fe3803f-d3f1-474a-963c-8719ec5bf16a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067446075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3067446075
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.3017946602
Short name T48
Test name
Test status
Simulation time 9999936472 ps
CPU time 145.43 seconds
Started Jan 17 02:42:09 PM PST 24
Finished Jan 17 02:44:37 PM PST 24
Peak memory 202260 kb
Host smart-15f90160-c474-4993-acd5-d2a8d6455c6f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017946602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.3017946602
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.95724961
Short name T895
Test name
Test status
Simulation time 96967828152 ps
CPU time 1354.13 seconds
Started Jan 17 02:41:59 PM PST 24
Finished Jan 17 03:04:34 PM PST 24
Peak memory 379936 kb
Host smart-c32fae3c-6f5b-492a-9950-977de517990a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95724961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multipl
e_keys.95724961
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.2685782540
Short name T302
Test name
Test status
Simulation time 1450013150 ps
CPU time 11.61 seconds
Started Jan 17 02:42:02 PM PST 24
Finished Jan 17 02:42:15 PM PST 24
Peak memory 202004 kb
Host smart-2778fa55-bc6e-46d5-bb4d-0cb7051207fe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685782540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.2685782540
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.785869347
Short name T641
Test name
Test status
Simulation time 44455313822 ps
CPU time 288.47 seconds
Started Jan 17 02:42:01 PM PST 24
Finished Jan 17 02:46:51 PM PST 24
Peak memory 202156 kb
Host smart-7dade341-d154-401e-8087-f325efd92d37
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785869347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.sram_ctrl_partial_access_b2b.785869347
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.3223891261
Short name T159
Test name
Test status
Simulation time 3731012034 ps
CPU time 5.84 seconds
Started Jan 17 02:42:08 PM PST 24
Finished Jan 17 02:42:16 PM PST 24
Peak memory 202472 kb
Host smart-dafd4589-9514-4654-a968-864749f911e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223891261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3223891261
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.384022845
Short name T893
Test name
Test status
Simulation time 4801343105 ps
CPU time 11.78 seconds
Started Jan 17 02:41:57 PM PST 24
Finished Jan 17 02:42:10 PM PST 24
Peak memory 202184 kb
Host smart-ba037a79-3276-4643-9745-162fa808b0e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384022845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.384022845
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.1328918495
Short name T887
Test name
Test status
Simulation time 164915056761 ps
CPU time 4063.69 seconds
Started Jan 17 02:42:08 PM PST 24
Finished Jan 17 03:49:54 PM PST 24
Peak memory 378840 kb
Host smart-f6e8243a-339e-4bc1-a52f-bd9fe2f5fe53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328918495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.1328918495
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1649691631
Short name T732
Test name
Test status
Simulation time 3233660614 ps
CPU time 2294.98 seconds
Started Jan 17 02:42:09 PM PST 24
Finished Jan 17 03:20:26 PM PST 24
Peak memory 675908 kb
Host smart-4f74db8e-cddf-4c9e-b00b-9937ee27d628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1649691631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1649691631
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.433758178
Short name T417
Test name
Test status
Simulation time 3266647009 ps
CPU time 250.54 seconds
Started Jan 17 02:42:01 PM PST 24
Finished Jan 17 02:46:13 PM PST 24
Peak memory 210356 kb
Host smart-d3319b3a-cd7a-4fde-90bd-bcbb043a10de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433758178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_stress_pipeline.433758178
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3148637783
Short name T817
Test name
Test status
Simulation time 3461613245 ps
CPU time 60.59 seconds
Started Jan 17 02:42:08 PM PST 24
Finished Jan 17 02:43:11 PM PST 24
Peak memory 285004 kb
Host smart-f066303f-8cb6-45d9-85c3-e1e7eef38532
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148637783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3148637783
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3262309898
Short name T366
Test name
Test status
Simulation time 18946307195 ps
CPU time 593.89 seconds
Started Jan 17 02:42:20 PM PST 24
Finished Jan 17 02:52:17 PM PST 24
Peak memory 379672 kb
Host smart-2a57f9b7-dc4b-4f85-9962-073e9ff533f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262309898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.3262309898
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.1299466387
Short name T268
Test name
Test status
Simulation time 43790984 ps
CPU time 0.68 seconds
Started Jan 17 02:42:29 PM PST 24
Finished Jan 17 02:42:31 PM PST 24
Peak memory 201436 kb
Host smart-0455ddef-b7ca-4028-8650-6e49a7eabfb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299466387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.1299466387
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.3464058943
Short name T240
Test name
Test status
Simulation time 313567541932 ps
CPU time 1770.45 seconds
Started Jan 17 02:42:20 PM PST 24
Finished Jan 17 03:11:54 PM PST 24
Peak memory 202160 kb
Host smart-caf6c712-bde4-4311-9e66-6e46ae82620e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464058943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.3464058943
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.3489846263
Short name T534
Test name
Test status
Simulation time 7405892582 ps
CPU time 32.92 seconds
Started Jan 17 02:42:22 PM PST 24
Finished Jan 17 02:42:58 PM PST 24
Peak memory 232888 kb
Host smart-d2184b99-f0fc-41de-8c9c-439b7ca5aa35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489846263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.3489846263
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.2653150876
Short name T723
Test name
Test status
Simulation time 10363199721 ps
CPU time 23.94 seconds
Started Jan 17 02:42:17 PM PST 24
Finished Jan 17 02:42:42 PM PST 24
Peak memory 210504 kb
Host smart-9133a9fe-de35-43f7-badc-27cafedb0cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653150876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.2653150876
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.224365006
Short name T254
Test name
Test status
Simulation time 1576965741 ps
CPU time 147.8 seconds
Started Jan 17 02:42:25 PM PST 24
Finished Jan 17 02:44:54 PM PST 24
Peak memory 370984 kb
Host smart-ea084008-f683-4481-91f1-fb4cd5330e67
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224365006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.sram_ctrl_max_throughput.224365006
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1659357446
Short name T748
Test name
Test status
Simulation time 20698568706 ps
CPU time 157.65 seconds
Started Jan 17 02:42:28 PM PST 24
Finished Jan 17 02:45:06 PM PST 24
Peak memory 214500 kb
Host smart-ea797573-c910-470d-b743-2b82d6e52e91
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659357446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1659357446
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.211799299
Short name T63
Test name
Test status
Simulation time 7023023314 ps
CPU time 149.82 seconds
Started Jan 17 02:42:28 PM PST 24
Finished Jan 17 02:44:58 PM PST 24
Peak memory 202152 kb
Host smart-67eeb5ca-7aba-4789-82bd-59bc83d05b90
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211799299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl
_mem_walk.211799299
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1040275879
Short name T496
Test name
Test status
Simulation time 113856370654 ps
CPU time 1193.53 seconds
Started Jan 17 02:42:17 PM PST 24
Finished Jan 17 03:02:12 PM PST 24
Peak memory 378052 kb
Host smart-4ffdb6ff-259a-4059-b5e8-d436badebf79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040275879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1040275879
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.4202241908
Short name T734
Test name
Test status
Simulation time 816168047 ps
CPU time 29.59 seconds
Started Jan 17 02:42:17 PM PST 24
Finished Jan 17 02:42:48 PM PST 24
Peak memory 202032 kb
Host smart-85baf62d-8809-46c1-ba34-9fa4d53c574a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202241908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.4202241908
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.755676759
Short name T966
Test name
Test status
Simulation time 80458088454 ps
CPU time 242.24 seconds
Started Jan 17 02:42:16 PM PST 24
Finished Jan 17 02:46:21 PM PST 24
Peak memory 202136 kb
Host smart-6e5b0fc6-af10-4ee5-b1dd-932c6e927103
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755676759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_partial_access_b2b.755676759
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.1533104222
Short name T474
Test name
Test status
Simulation time 436585000 ps
CPU time 5.9 seconds
Started Jan 17 02:42:23 PM PST 24
Finished Jan 17 02:42:31 PM PST 24
Peak memory 202332 kb
Host smart-e9076033-51ee-4016-8fb5-3ca919cf5728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533104222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1533104222
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.3162855610
Short name T708
Test name
Test status
Simulation time 8380995420 ps
CPU time 1450.33 seconds
Started Jan 17 02:42:23 PM PST 24
Finished Jan 17 03:06:36 PM PST 24
Peak memory 381080 kb
Host smart-0ea8fdb2-39cb-42e0-b496-957a4f8be45f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162855610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3162855610
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.103048675
Short name T65
Test name
Test status
Simulation time 1001742299 ps
CPU time 20.79 seconds
Started Jan 17 02:42:17 PM PST 24
Finished Jan 17 02:42:39 PM PST 24
Peak memory 202032 kb
Host smart-0b868735-390d-4322-940a-71b42e84e16d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103048675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.103048675
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.1943276327
Short name T140
Test name
Test status
Simulation time 905611996395 ps
CPU time 2472.86 seconds
Started Jan 17 02:42:28 PM PST 24
Finished Jan 17 03:23:43 PM PST 24
Peak memory 375956 kb
Host smart-79d6e5ab-c407-4b06-a3b9-a1ae74c5c614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943276327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.1943276327
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.807633434
Short name T565
Test name
Test status
Simulation time 3947133590 ps
CPU time 4072.93 seconds
Started Jan 17 02:42:23 PM PST 24
Finished Jan 17 03:50:18 PM PST 24
Peak memory 414308 kb
Host smart-016223b1-86ba-4a0b-94fb-14d7b96fa667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=807633434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.807633434
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4049887194
Short name T935
Test name
Test status
Simulation time 8460517061 ps
CPU time 258.64 seconds
Started Jan 17 02:42:16 PM PST 24
Finished Jan 17 02:46:37 PM PST 24
Peak memory 202148 kb
Host smart-b2742cfa-3436-49a0-830c-566591593f20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049887194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.4049887194
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3133620855
Short name T394
Test name
Test status
Simulation time 731039755 ps
CPU time 62.21 seconds
Started Jan 17 02:42:19 PM PST 24
Finished Jan 17 02:43:24 PM PST 24
Peak memory 290708 kb
Host smart-ea7f713f-a96d-4e0e-a46e-9fc14927804a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133620855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3133620855
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2263675217
Short name T454
Test name
Test status
Simulation time 21998072436 ps
CPU time 1722.05 seconds
Started Jan 17 02:42:36 PM PST 24
Finished Jan 17 03:11:19 PM PST 24
Peak memory 380112 kb
Host smart-13cd9698-cf17-4b51-9003-d2f6c1d53dbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263675217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2263675217
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.4199380437
Short name T389
Test name
Test status
Simulation time 17347866 ps
CPU time 0.65 seconds
Started Jan 17 02:42:52 PM PST 24
Finished Jan 17 02:42:53 PM PST 24
Peak memory 201392 kb
Host smart-ef57d21e-4a78-4aa2-9d6f-af05d736fb21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199380437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.4199380437
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1907126103
Short name T580
Test name
Test status
Simulation time 625213033718 ps
CPU time 2621.08 seconds
Started Jan 17 02:42:30 PM PST 24
Finished Jan 17 03:26:15 PM PST 24
Peak memory 202108 kb
Host smart-d2f4cc32-a60d-4fda-970b-02776de19db8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907126103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1907126103
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.4188652687
Short name T595
Test name
Test status
Simulation time 44473159955 ps
CPU time 1011.21 seconds
Started Jan 17 02:42:36 PM PST 24
Finished Jan 17 02:59:28 PM PST 24
Peak memory 374960 kb
Host smart-23a0eb8a-92a4-4630-b717-5e490ca35943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188652687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.4188652687
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.1949342135
Short name T8
Test name
Test status
Simulation time 35300834710 ps
CPU time 121.51 seconds
Started Jan 17 02:42:36 PM PST 24
Finished Jan 17 02:44:39 PM PST 24
Peak memory 213752 kb
Host smart-ad338c6d-7c90-4e4b-a4db-e5fa620dfc13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949342135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.1949342135
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.3550861062
Short name T561
Test name
Test status
Simulation time 2214724726 ps
CPU time 78.78 seconds
Started Jan 17 02:42:37 PM PST 24
Finished Jan 17 02:43:56 PM PST 24
Peak memory 308504 kb
Host smart-8e2d339e-533a-473b-aaa7-ff8e173a82af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550861062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.3550861062
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3845798936
Short name T531
Test name
Test status
Simulation time 2384516927 ps
CPU time 77.04 seconds
Started Jan 17 02:42:43 PM PST 24
Finished Jan 17 02:44:01 PM PST 24
Peak memory 211408 kb
Host smart-fdf2a93d-d3ee-4136-978e-e897fd83fbad
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845798936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.3845798936
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2457326012
Short name T341
Test name
Test status
Simulation time 2038180725 ps
CPU time 121.65 seconds
Started Jan 17 02:42:49 PM PST 24
Finished Jan 17 02:44:51 PM PST 24
Peak memory 202072 kb
Host smart-ac43462d-bfbe-472c-99b6-78c31ed69acc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457326012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2457326012
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.1690046473
Short name T552
Test name
Test status
Simulation time 26383023000 ps
CPU time 828.09 seconds
Started Jan 17 02:42:32 PM PST 24
Finished Jan 17 02:56:22 PM PST 24
Peak memory 378056 kb
Host smart-ad60033b-d8c4-4f9a-81bb-482a4a58e421
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690046473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.1690046473
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.678251348
Short name T488
Test name
Test status
Simulation time 4357422759 ps
CPU time 18.2 seconds
Started Jan 17 02:42:36 PM PST 24
Finished Jan 17 02:42:54 PM PST 24
Peak memory 202060 kb
Host smart-6ebda9e9-5d40-464e-be32-256ec589b799
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678251348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.s
ram_ctrl_partial_access.678251348
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.280825945
Short name T414
Test name
Test status
Simulation time 6180602248 ps
CPU time 359.52 seconds
Started Jan 17 02:42:37 PM PST 24
Finished Jan 17 02:48:37 PM PST 24
Peak memory 202312 kb
Host smart-d8dca362-865a-4711-94ef-fade49eab296
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280825945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.sram_ctrl_partial_access_b2b.280825945
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.1579038170
Short name T234
Test name
Test status
Simulation time 1410563356 ps
CPU time 5.53 seconds
Started Jan 17 02:42:42 PM PST 24
Finished Jan 17 02:42:48 PM PST 24
Peak memory 202412 kb
Host smart-9c2f7c0c-a647-4475-a521-9bf8bbf20481
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579038170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1579038170
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.555651694
Short name T52
Test name
Test status
Simulation time 45461683086 ps
CPU time 1077.11 seconds
Started Jan 17 02:42:45 PM PST 24
Finished Jan 17 03:00:43 PM PST 24
Peak memory 381144 kb
Host smart-46f3f8bd-8950-4fd2-b575-c771d96de27d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555651694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.555651694
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.3418001120
Short name T382
Test name
Test status
Simulation time 717344344 ps
CPU time 28.11 seconds
Started Jan 17 02:42:28 PM PST 24
Finished Jan 17 02:42:58 PM PST 24
Peak memory 202128 kb
Host smart-38ffbd17-5dac-4e62-9b6c-95da59f5bc52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418001120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3418001120
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.2205411210
Short name T564
Test name
Test status
Simulation time 85094115799 ps
CPU time 4448.62 seconds
Started Jan 17 02:42:51 PM PST 24
Finished Jan 17 03:57:01 PM PST 24
Peak memory 382176 kb
Host smart-46a6ea39-4c9c-47e9-8d98-1b3b9e0b1393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205411210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.2205411210
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2123810562
Short name T824
Test name
Test status
Simulation time 4111056930 ps
CPU time 1935.44 seconds
Started Jan 17 02:42:52 PM PST 24
Finished Jan 17 03:15:08 PM PST 24
Peak memory 558440 kb
Host smart-67c96e0e-143f-4d87-9ffd-b7a0f46f2df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2123810562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2123810562
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4081930226
Short name T637
Test name
Test status
Simulation time 17226562717 ps
CPU time 209.68 seconds
Started Jan 17 02:42:30 PM PST 24
Finished Jan 17 02:46:03 PM PST 24
Peak memory 202100 kb
Host smart-86d3694b-e5bf-4efb-9ada-d503e2c4f479
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081930226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.4081930226
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2262668118
Short name T587
Test name
Test status
Simulation time 787638569 ps
CPU time 160.35 seconds
Started Jan 17 02:42:38 PM PST 24
Finished Jan 17 02:45:19 PM PST 24
Peak memory 365780 kb
Host smart-72960db4-2983-4d80-8c8a-9d2ce5385080
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262668118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2262668118
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1990817016
Short name T601
Test name
Test status
Simulation time 14324680630 ps
CPU time 1152.62 seconds
Started Jan 17 02:43:04 PM PST 24
Finished Jan 17 03:02:18 PM PST 24
Peak memory 371912 kb
Host smart-d3a09e34-8002-49ee-8d59-ff48a1e11956
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990817016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.1990817016
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2661975303
Short name T521
Test name
Test status
Simulation time 15342824 ps
CPU time 0.66 seconds
Started Jan 17 02:43:05 PM PST 24
Finished Jan 17 02:43:09 PM PST 24
Peak memory 201892 kb
Host smart-85dde521-78a6-486d-90dd-287ac46063b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661975303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2661975303
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.77432878
Short name T288
Test name
Test status
Simulation time 103612868348 ps
CPU time 1763.13 seconds
Started Jan 17 02:42:53 PM PST 24
Finished Jan 17 03:12:17 PM PST 24
Peak memory 202140 kb
Host smart-370c44fd-b95d-4a13-970b-e698790a58b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77432878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.77432878
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.3712383114
Short name T682
Test name
Test status
Simulation time 5168531676 ps
CPU time 122.3 seconds
Started Jan 17 02:43:05 PM PST 24
Finished Jan 17 02:45:09 PM PST 24
Peak memory 320452 kb
Host smart-2b503ee1-1773-418b-ac2a-381c4a5d867e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712383114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.3712383114
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3936300779
Short name T904
Test name
Test status
Simulation time 27832171879 ps
CPU time 106.58 seconds
Started Jan 17 02:43:05 PM PST 24
Finished Jan 17 02:44:54 PM PST 24
Peak memory 211560 kb
Host smart-fb223f89-8fab-481e-add8-e73ae5c90713
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936300779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3936300779
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.365110245
Short name T162
Test name
Test status
Simulation time 1140879214 ps
CPU time 62.21 seconds
Started Jan 17 02:42:57 PM PST 24
Finished Jan 17 02:44:00 PM PST 24
Peak memory 288156 kb
Host smart-e7d60862-b551-497b-9175-3dce4cee5948
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365110245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.sram_ctrl_max_throughput.365110245
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.578144719
Short name T634
Test name
Test status
Simulation time 20366661607 ps
CPU time 151.65 seconds
Started Jan 17 02:43:05 PM PST 24
Finished Jan 17 02:45:40 PM PST 24
Peak memory 211076 kb
Host smart-3479678f-a80b-4e87-86b5-b91f265e525e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578144719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.578144719
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.157920312
Short name T903
Test name
Test status
Simulation time 21512041927 ps
CPU time 313.82 seconds
Started Jan 17 02:43:07 PM PST 24
Finished Jan 17 02:48:23 PM PST 24
Peak memory 202152 kb
Host smart-7c382eb1-7666-43ec-b28c-0b4561716de6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157920312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_mem_walk.157920312
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.605002308
Short name T361
Test name
Test status
Simulation time 46056258961 ps
CPU time 1834.51 seconds
Started Jan 17 02:42:49 PM PST 24
Finished Jan 17 03:13:25 PM PST 24
Peak memory 379096 kb
Host smart-ca34ed8a-ad7f-48fa-ac6b-3be2af68e41c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605002308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip
le_keys.605002308
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.3404895212
Short name T686
Test name
Test status
Simulation time 1992160586 ps
CPU time 15.38 seconds
Started Jan 17 02:42:58 PM PST 24
Finished Jan 17 02:43:14 PM PST 24
Peak memory 202116 kb
Host smart-c1e9703a-2e39-4f44-8679-2ce432fae212
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404895212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.3404895212
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4131127700
Short name T463
Test name
Test status
Simulation time 30249198969 ps
CPU time 296.55 seconds
Started Jan 17 02:42:57 PM PST 24
Finished Jan 17 02:47:54 PM PST 24
Peak memory 202124 kb
Host smart-08450e9b-0a87-40a4-aa82-59c32450f329
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131127700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.4131127700
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.3573091754
Short name T525
Test name
Test status
Simulation time 1403233660 ps
CPU time 6.12 seconds
Started Jan 17 02:43:05 PM PST 24
Finished Jan 17 02:43:13 PM PST 24
Peak memory 202424 kb
Host smart-85cb7862-c091-453e-88bc-7683479775a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573091754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3573091754
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.64855845
Short name T142
Test name
Test status
Simulation time 1844002572 ps
CPU time 135.27 seconds
Started Jan 17 02:43:06 PM PST 24
Finished Jan 17 02:45:24 PM PST 24
Peak memory 348288 kb
Host smart-2a54bb42-70ca-4414-83d3-da56964ec7ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64855845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.64855845
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.1696756692
Short name T1
Test name
Test status
Simulation time 784620916 ps
CPU time 197.52 seconds
Started Jan 17 02:42:51 PM PST 24
Finished Jan 17 02:46:09 PM PST 24
Peak memory 373888 kb
Host smart-e5cab8ba-23d5-45a7-9972-f1a0596e28ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696756692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1696756692
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.3890410298
Short name T526
Test name
Test status
Simulation time 94729319413 ps
CPU time 6217.75 seconds
Started Jan 17 02:43:06 PM PST 24
Finished Jan 17 04:26:47 PM PST 24
Peak memory 381140 kb
Host smart-a0aafcfb-6638-400d-8713-11f0a1f409c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890410298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.3890410298
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2816600787
Short name T421
Test name
Test status
Simulation time 1234462462 ps
CPU time 4585.39 seconds
Started Jan 17 02:43:05 PM PST 24
Finished Jan 17 03:59:34 PM PST 24
Peak memory 436108 kb
Host smart-a5bbb374-85cb-4e7c-837a-2567b05aa176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2816600787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2816600787
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2288447924
Short name T495
Test name
Test status
Simulation time 5736925835 ps
CPU time 250.77 seconds
Started Jan 17 02:43:00 PM PST 24
Finished Jan 17 02:47:11 PM PST 24
Peak memory 202124 kb
Host smart-11597a44-0225-483a-b811-0fa4400dc85d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288447924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.2288447924
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3218367551
Short name T964
Test name
Test status
Simulation time 2054656390 ps
CPU time 220.54 seconds
Started Jan 17 02:43:05 PM PST 24
Finished Jan 17 02:46:47 PM PST 24
Peak memory 365728 kb
Host smart-0d616570-16eb-4bcb-b34a-10be928dc19e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218367551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3218367551
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3468598106
Short name T714
Test name
Test status
Simulation time 5295232961 ps
CPU time 1294.53 seconds
Started Jan 17 02:43:17 PM PST 24
Finished Jan 17 03:04:52 PM PST 24
Peak memory 377936 kb
Host smart-ed994174-2e6b-4e58-bbf3-aedc23da6c07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468598106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.3468598106
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.930703018
Short name T747
Test name
Test status
Simulation time 12489256 ps
CPU time 0.63 seconds
Started Jan 17 02:43:18 PM PST 24
Finished Jan 17 02:43:20 PM PST 24
Peak memory 201852 kb
Host smart-e4260f7b-43e0-4467-b600-ce9225ced398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930703018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.930703018
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.2579419583
Short name T698
Test name
Test status
Simulation time 113515029458 ps
CPU time 1092.98 seconds
Started Jan 17 02:43:06 PM PST 24
Finished Jan 17 03:01:22 PM PST 24
Peak memory 202216 kb
Host smart-f1a06920-26f1-4a82-bbcc-a70dfa622f42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579419583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.2579419583
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.1728165921
Short name T364
Test name
Test status
Simulation time 11264430253 ps
CPU time 97.07 seconds
Started Jan 17 02:43:10 PM PST 24
Finished Jan 17 02:44:54 PM PST 24
Peak memory 210200 kb
Host smart-7b9b4e28-be20-4761-b4c0-74d4990a026d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728165921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.1728165921
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.1478009348
Short name T986
Test name
Test status
Simulation time 2419860137 ps
CPU time 44.14 seconds
Started Jan 17 02:43:14 PM PST 24
Finished Jan 17 02:44:02 PM PST 24
Peak memory 261352 kb
Host smart-295053e0-dc0e-4683-af99-dfd6be5bfdd3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478009348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.1478009348
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1668687298
Short name T76
Test name
Test status
Simulation time 3663138039 ps
CPU time 76.19 seconds
Started Jan 17 02:43:20 PM PST 24
Finished Jan 17 02:44:37 PM PST 24
Peak memory 211016 kb
Host smart-f766ad09-e597-42a9-951f-910d019d557a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668687298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.1668687298
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1553993958
Short name T370
Test name
Test status
Simulation time 5800181376 ps
CPU time 248.11 seconds
Started Jan 17 02:43:20 PM PST 24
Finished Jan 17 02:47:28 PM PST 24
Peak memory 202180 kb
Host smart-3188fd13-8ee5-4824-92ec-1928d7bf6ac6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553993958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1553993958
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.2308819429
Short name T793
Test name
Test status
Simulation time 35236307023 ps
CPU time 3001.35 seconds
Started Jan 17 02:43:07 PM PST 24
Finished Jan 17 03:33:11 PM PST 24
Peak memory 381100 kb
Host smart-292c6dbb-f9ad-435f-966d-527d1d42c47e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308819429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.2308819429
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.1264580674
Short name T717
Test name
Test status
Simulation time 1039016059 ps
CPU time 16.99 seconds
Started Jan 17 02:43:14 PM PST 24
Finished Jan 17 02:43:34 PM PST 24
Peak memory 202128 kb
Host smart-f6dde790-b69c-4d03-ad3d-6f25039cf684
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264580674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.1264580674
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1607522947
Short name T149
Test name
Test status
Simulation time 55909506092 ps
CPU time 315.7 seconds
Started Jan 17 02:43:09 PM PST 24
Finished Jan 17 02:48:33 PM PST 24
Peak memory 202092 kb
Host smart-9b6afa31-6deb-4d2f-8b3f-cb8436790d5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607522947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.1607522947
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.823463428
Short name T762
Test name
Test status
Simulation time 1459154409 ps
CPU time 14.49 seconds
Started Jan 17 02:43:21 PM PST 24
Finished Jan 17 02:43:36 PM PST 24
Peak memory 202420 kb
Host smart-04bf3b7d-0219-40e0-b123-988383675642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823463428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.823463428
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.58051316
Short name T467
Test name
Test status
Simulation time 44649291141 ps
CPU time 1100.87 seconds
Started Jan 17 02:43:20 PM PST 24
Finished Jan 17 03:01:42 PM PST 24
Peak memory 378000 kb
Host smart-1a90dd28-51b1-48af-92aa-cb507ec6fd88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58051316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.58051316
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.2094777131
Short name T604
Test name
Test status
Simulation time 728630582 ps
CPU time 58.81 seconds
Started Jan 17 02:43:06 PM PST 24
Finished Jan 17 02:44:08 PM PST 24
Peak memory 289804 kb
Host smart-2ae8b647-1b88-48e9-8c3f-dcd003aa1651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094777131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2094777131
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2598297930
Short name T24
Test name
Test status
Simulation time 3626564820 ps
CPU time 3952.22 seconds
Started Jan 17 02:43:20 PM PST 24
Finished Jan 17 03:49:13 PM PST 24
Peak memory 528820 kb
Host smart-45d8e4de-4f45-40c9-817a-f3fedb7fc275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2598297930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2598297930
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3510366815
Short name T688
Test name
Test status
Simulation time 19149018619 ps
CPU time 339.32 seconds
Started Jan 17 02:43:03 PM PST 24
Finished Jan 17 02:48:44 PM PST 24
Peak memory 202172 kb
Host smart-0c5cc5a8-8ad4-4bb5-93a0-a38aa7d8fb09
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510366815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.3510366815
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.723423876
Short name T838
Test name
Test status
Simulation time 2766722486 ps
CPU time 31.92 seconds
Started Jan 17 02:43:09 PM PST 24
Finished Jan 17 02:43:49 PM PST 24
Peak memory 234952 kb
Host smart-36aedcf7-7f15-4687-b9cc-0977226dfb83
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723423876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.723423876
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.627621128
Short name T45
Test name
Test status
Simulation time 3216884507 ps
CPU time 405.13 seconds
Started Jan 17 02:43:31 PM PST 24
Finished Jan 17 02:50:16 PM PST 24
Peak memory 363452 kb
Host smart-3868a90c-b4aa-4936-8451-34eb53d9e42b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627621128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.627621128
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.1217877334
Short name T627
Test name
Test status
Simulation time 22828319 ps
CPU time 0.63 seconds
Started Jan 17 02:43:38 PM PST 24
Finished Jan 17 02:43:40 PM PST 24
Peak memory 201900 kb
Host smart-ad5c655e-a1d3-462d-8738-923ff9fdc2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217877334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.1217877334
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.1060615966
Short name T658
Test name
Test status
Simulation time 198228600951 ps
CPU time 707.78 seconds
Started Jan 17 02:43:29 PM PST 24
Finished Jan 17 02:55:18 PM PST 24
Peak memory 202176 kb
Host smart-ed2c2d07-26ba-4b76-97a6-06174bd7f4b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060615966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.1060615966
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.879633452
Short name T769
Test name
Test status
Simulation time 20356683638 ps
CPU time 93.35 seconds
Started Jan 17 02:43:30 PM PST 24
Finished Jan 17 02:45:04 PM PST 24
Peak memory 202192 kb
Host smart-493b86d6-7951-47c9-8ce5-2294083f4680
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879633452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc
alation.879633452
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.2872507796
Short name T611
Test name
Test status
Simulation time 690607558 ps
CPU time 30.11 seconds
Started Jan 17 02:43:32 PM PST 24
Finished Jan 17 02:44:02 PM PST 24
Peak memory 222996 kb
Host smart-553c0c36-c0cc-4cd1-b6ca-7b4fc4b536d5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872507796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.2872507796
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2519912135
Short name T282
Test name
Test status
Simulation time 9785899676 ps
CPU time 76.29 seconds
Started Jan 17 02:43:39 PM PST 24
Finished Jan 17 02:44:56 PM PST 24
Peak memory 211076 kb
Host smart-f2c37045-1d80-400b-8726-018577384ca8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519912135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.2519912135
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2132900567
Short name T478
Test name
Test status
Simulation time 2021865270 ps
CPU time 127.46 seconds
Started Jan 17 02:43:40 PM PST 24
Finished Jan 17 02:45:48 PM PST 24
Peak memory 202052 kb
Host smart-88288fc3-1005-4c6e-bc23-2d264e221fa8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132900567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2132900567
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.979817647
Short name T579
Test name
Test status
Simulation time 40138842555 ps
CPU time 413.82 seconds
Started Jan 17 02:43:27 PM PST 24
Finished Jan 17 02:50:22 PM PST 24
Peak memory 349804 kb
Host smart-99fb7fcc-6ae9-41e9-8abe-e477eb947772
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979817647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip
le_keys.979817647
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.3610160443
Short name T867
Test name
Test status
Simulation time 1347457135 ps
CPU time 26.34 seconds
Started Jan 17 02:43:30 PM PST 24
Finished Jan 17 02:43:57 PM PST 24
Peak memory 202032 kb
Host smart-20dc7232-8e42-4e09-8541-29ecf7292677
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610160443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.3610160443
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3967734157
Short name T150
Test name
Test status
Simulation time 14414266909 ps
CPU time 322.43 seconds
Started Jan 17 02:43:32 PM PST 24
Finished Jan 17 02:48:55 PM PST 24
Peak memory 202084 kb
Host smart-96fd8535-f782-4293-a608-59f069306860
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967734157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.3967734157
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.4173279742
Short name T515
Test name
Test status
Simulation time 1344611561 ps
CPU time 5.92 seconds
Started Jan 17 02:43:33 PM PST 24
Finished Jan 17 02:43:40 PM PST 24
Peak memory 202396 kb
Host smart-43093bb6-0027-45bf-8ec4-de651909bc33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173279742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.4173279742
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.3092327841
Short name T727
Test name
Test status
Simulation time 27004277081 ps
CPU time 1439.73 seconds
Started Jan 17 02:43:31 PM PST 24
Finished Jan 17 03:07:31 PM PST 24
Peak memory 378492 kb
Host smart-1d812517-1a28-4d69-8ef0-49b86529f9cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092327841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3092327841
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.1500699878
Short name T418
Test name
Test status
Simulation time 389424512 ps
CPU time 7.8 seconds
Started Jan 17 02:43:28 PM PST 24
Finished Jan 17 02:43:37 PM PST 24
Peak memory 202068 kb
Host smart-178d2c7e-6f60-4ffa-96ea-c1d232a32733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500699878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1500699878
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3597178918
Short name T537
Test name
Test status
Simulation time 583267096 ps
CPU time 8440.06 seconds
Started Jan 17 02:43:39 PM PST 24
Finished Jan 17 05:04:21 PM PST 24
Peak memory 633492 kb
Host smart-766e6392-2043-4206-ba12-079ce0cafbb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3597178918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3597178918
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1452267188
Short name T778
Test name
Test status
Simulation time 2975156859 ps
CPU time 216.18 seconds
Started Jan 17 02:43:31 PM PST 24
Finished Jan 17 02:47:07 PM PST 24
Peak memory 202160 kb
Host smart-93a2437b-baa1-458b-9e37-1564131d599b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452267188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1452267188
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.490006922
Short name T809
Test name
Test status
Simulation time 2841199112 ps
CPU time 39.1 seconds
Started Jan 17 02:43:31 PM PST 24
Finished Jan 17 02:44:11 PM PST 24
Peak memory 254320 kb
Host smart-cb63b082-396a-4da8-a736-0d3fd94e3aa4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490006922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.490006922
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3492903264
Short name T26
Test name
Test status
Simulation time 10761845095 ps
CPU time 1082.52 seconds
Started Jan 17 02:43:48 PM PST 24
Finished Jan 17 03:01:51 PM PST 24
Peak memory 375940 kb
Host smart-d80298ab-89e1-462c-950d-de7cd793ae01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492903264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.3492903264
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1766332237
Short name T982
Test name
Test status
Simulation time 11504031 ps
CPU time 0.64 seconds
Started Jan 17 02:44:03 PM PST 24
Finished Jan 17 02:44:07 PM PST 24
Peak memory 201860 kb
Host smart-3252fd16-33fb-455f-bf25-a73e3e41c3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766332237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1766332237
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.2993172876
Short name T712
Test name
Test status
Simulation time 34498611423 ps
CPU time 2378.4 seconds
Started Jan 17 02:43:42 PM PST 24
Finished Jan 17 03:23:21 PM PST 24
Peak memory 202200 kb
Host smart-f32e6fe7-122c-4148-82d1-ce26ca8cf344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993172876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.2993172876
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.2108450088
Short name T477
Test name
Test status
Simulation time 102592182784 ps
CPU time 1444.29 seconds
Started Jan 17 02:43:49 PM PST 24
Finished Jan 17 03:07:54 PM PST 24
Peak memory 378996 kb
Host smart-44ba64d3-d9d8-4385-bf8c-a15aa39a7fbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108450088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.2108450088
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2280382356
Short name T260
Test name
Test status
Simulation time 3649426797 ps
CPU time 134.13 seconds
Started Jan 17 02:43:43 PM PST 24
Finished Jan 17 02:45:58 PM PST 24
Peak memory 369920 kb
Host smart-2a88e5a7-7e74-40ce-b76a-c6cdde272596
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280382356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2280382356
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.206852263
Short name T503
Test name
Test status
Simulation time 19032123398 ps
CPU time 146.93 seconds
Started Jan 17 02:45:10 PM PST 24
Finished Jan 17 02:47:39 PM PST 24
Peak memory 214328 kb
Host smart-2d90c762-e2b1-4c8b-a97d-1429069311ab
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206852263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_mem_partial_access.206852263
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1687834255
Short name T756
Test name
Test status
Simulation time 10359807196 ps
CPU time 157.71 seconds
Started Jan 17 02:44:00 PM PST 24
Finished Jan 17 02:46:39 PM PST 24
Peak memory 202172 kb
Host smart-a3898b5d-bce6-4441-b8c2-96a8c4dbf4d0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687834255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1687834255
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.2761602717
Short name T43
Test name
Test status
Simulation time 41997239755 ps
CPU time 525.86 seconds
Started Jan 17 02:43:43 PM PST 24
Finished Jan 17 02:52:30 PM PST 24
Peak memory 366832 kb
Host smart-63dcacf7-b410-4580-a5e7-3165f2eb782c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761602717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.2761602717
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.3635658958
Short name T532
Test name
Test status
Simulation time 486968877 ps
CPU time 60 seconds
Started Jan 17 02:43:45 PM PST 24
Finished Jan 17 02:44:45 PM PST 24
Peak memory 320672 kb
Host smart-dae6b288-95b1-419d-b18d-a261da109579
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635658958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.3635658958
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3130744979
Short name T950
Test name
Test status
Simulation time 168507021344 ps
CPU time 332.99 seconds
Started Jan 17 02:43:44 PM PST 24
Finished Jan 17 02:49:17 PM PST 24
Peak memory 202240 kb
Host smart-e6f79194-c0ae-4a06-a090-07a9a8e4b677
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130744979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.3130744979
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.459227197
Short name T50
Test name
Test status
Simulation time 362561067 ps
CPU time 5.79 seconds
Started Jan 17 02:43:57 PM PST 24
Finished Jan 17 02:44:04 PM PST 24
Peak memory 202372 kb
Host smart-b1a0d56d-06dc-42c6-a03f-a635803f4c78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459227197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.459227197
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2523922257
Short name T279
Test name
Test status
Simulation time 4458963760 ps
CPU time 979.44 seconds
Started Jan 17 02:43:58 PM PST 24
Finished Jan 17 03:00:19 PM PST 24
Peak memory 379100 kb
Host smart-6c59774a-319e-49b7-8ef8-9fe28c4735c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523922257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2523922257
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.1813614197
Short name T540
Test name
Test status
Simulation time 1292019713 ps
CPU time 125.35 seconds
Started Jan 17 02:43:38 PM PST 24
Finished Jan 17 02:45:44 PM PST 24
Peak memory 355548 kb
Host smart-eb368b0f-8b45-49b1-9a6d-73940a7c5af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813614197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1813614197
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.3785288391
Short name T900
Test name
Test status
Simulation time 53644627845 ps
CPU time 5014.24 seconds
Started Jan 17 02:44:04 PM PST 24
Finished Jan 17 04:07:41 PM PST 24
Peak memory 380744 kb
Host smart-dcf35c96-c637-4813-ad88-79e011a046f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785288391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.3785288391
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1732692600
Short name T794
Test name
Test status
Simulation time 1453462535 ps
CPU time 7110.53 seconds
Started Jan 17 02:44:03 PM PST 24
Finished Jan 17 04:42:38 PM PST 24
Peak memory 676424 kb
Host smart-42fef3cf-20d8-440d-afb6-373ba7098943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1732692600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1732692600
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2125606839
Short name T518
Test name
Test status
Simulation time 18330469810 ps
CPU time 352.81 seconds
Started Jan 17 02:43:43 PM PST 24
Finished Jan 17 02:49:37 PM PST 24
Peak memory 202168 kb
Host smart-834408eb-995b-484c-9339-4e6458544b63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125606839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.2125606839
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3130658048
Short name T759
Test name
Test status
Simulation time 1776414523 ps
CPU time 133.15 seconds
Started Jan 17 02:43:49 PM PST 24
Finished Jan 17 02:46:03 PM PST 24
Peak memory 365696 kb
Host smart-fa695088-889a-479b-9a59-2f5f7dfb6d19
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130658048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.3130658048
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1611756215
Short name T862
Test name
Test status
Simulation time 40731111421 ps
CPU time 1157.2 seconds
Started Jan 17 02:44:09 PM PST 24
Finished Jan 17 03:03:27 PM PST 24
Peak memory 370824 kb
Host smart-18b7d021-3f81-424a-87a9-b955292978e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611756215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.1611756215
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.3733166759
Short name T771
Test name
Test status
Simulation time 15660739 ps
CPU time 0.66 seconds
Started Jan 17 02:44:17 PM PST 24
Finished Jan 17 02:44:18 PM PST 24
Peak memory 201828 kb
Host smart-c51c68da-6cfc-41e1-a68c-9f97c067dd62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733166759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.3733166759
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.4175287600
Short name T711
Test name
Test status
Simulation time 101884857569 ps
CPU time 1133.23 seconds
Started Jan 17 02:44:04 PM PST 24
Finished Jan 17 03:03:00 PM PST 24
Peak memory 202172 kb
Host smart-eb5a98e0-c54a-42ef-9a24-a0e8acc5935a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175287600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.4175287600
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.3640004843
Short name T38
Test name
Test status
Simulation time 73748241450 ps
CPU time 981.58 seconds
Started Jan 17 02:44:09 PM PST 24
Finished Jan 17 03:00:33 PM PST 24
Peak memory 378808 kb
Host smart-f8d9c03a-06bb-4b6c-9b22-a19fd01b1784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640004843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.3640004843
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1250934938
Short name T544
Test name
Test status
Simulation time 56589259584 ps
CPU time 157.99 seconds
Started Jan 17 02:44:10 PM PST 24
Finished Jan 17 02:46:50 PM PST 24
Peak memory 202200 kb
Host smart-c7abd4e9-7426-45a7-bd77-ce6ae2caaf34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250934938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1250934938
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.2558404262
Short name T541
Test name
Test status
Simulation time 2757066046 ps
CPU time 36.66 seconds
Started Jan 17 02:44:03 PM PST 24
Finished Jan 17 02:44:43 PM PST 24
Peak memory 240296 kb
Host smart-95a09955-40c6-47c5-b85a-b9b8bc32ff4b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558404262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.2558404262
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2366052469
Short name T440
Test name
Test status
Simulation time 992685722 ps
CPU time 77.02 seconds
Started Jan 17 02:44:11 PM PST 24
Finished Jan 17 02:45:29 PM PST 24
Peak memory 218424 kb
Host smart-caa745a2-088c-4330-b333-22dccd358a57
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366052469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.2366052469
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.1409079900
Short name T697
Test name
Test status
Simulation time 7121518498 ps
CPU time 146.11 seconds
Started Jan 17 02:44:10 PM PST 24
Finished Jan 17 02:46:38 PM PST 24
Peak memory 202260 kb
Host smart-7207a563-497c-44af-8ff1-d58710038876
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409079900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.1409079900
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2447528226
Short name T970
Test name
Test status
Simulation time 12036674835 ps
CPU time 757.61 seconds
Started Jan 17 02:44:03 PM PST 24
Finished Jan 17 02:56:44 PM PST 24
Peak memory 372900 kb
Host smart-6cf333e9-0909-4ed7-a24b-6b15ef8f921e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447528226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2447528226
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.2288889998
Short name T968
Test name
Test status
Simulation time 1191127341 ps
CPU time 32.05 seconds
Started Jan 17 02:44:03 PM PST 24
Finished Jan 17 02:44:39 PM PST 24
Peak memory 202096 kb
Host smart-60bcaa94-bd48-4221-9dec-ee020b3ab547
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288889998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.2288889998
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.329195824
Short name T270
Test name
Test status
Simulation time 30141414349 ps
CPU time 478.8 seconds
Started Jan 17 02:44:03 PM PST 24
Finished Jan 17 02:52:06 PM PST 24
Peak memory 202216 kb
Host smart-3e654fb5-d380-4028-a349-0ec23b3dcf34
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329195824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.sram_ctrl_partial_access_b2b.329195824
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.4084042769
Short name T516
Test name
Test status
Simulation time 940965885 ps
CPU time 12.66 seconds
Started Jan 17 02:44:09 PM PST 24
Finished Jan 17 02:44:24 PM PST 24
Peak memory 202232 kb
Host smart-bf8a8b3a-f6ab-4121-98a7-340719c15aec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084042769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.4084042769
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.2165738299
Short name T657
Test name
Test status
Simulation time 4552935283 ps
CPU time 417.81 seconds
Started Jan 17 02:44:11 PM PST 24
Finished Jan 17 02:51:10 PM PST 24
Peak memory 356544 kb
Host smart-8b45dc2f-9790-4c6f-a93e-260f5f639733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165738299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2165738299
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.3391116906
Short name T455
Test name
Test status
Simulation time 1006893168 ps
CPU time 36.41 seconds
Started Jan 17 02:44:03 PM PST 24
Finished Jan 17 02:44:43 PM PST 24
Peak memory 275660 kb
Host smart-e41994e9-52e2-4956-86de-5834a7b36a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391116906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3391116906
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1679336302
Short name T310
Test name
Test status
Simulation time 1362911783 ps
CPU time 3417.04 seconds
Started Jan 17 02:44:12 PM PST 24
Finished Jan 17 03:41:14 PM PST 24
Peak memory 628272 kb
Host smart-e10ace65-3a1d-402c-a691-4785029d61ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1679336302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1679336302
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.958518363
Short name T828
Test name
Test status
Simulation time 7960760065 ps
CPU time 407.85 seconds
Started Jan 17 02:44:05 PM PST 24
Finished Jan 17 02:50:55 PM PST 24
Peak memory 202128 kb
Host smart-fb1683c1-cc98-485b-acb8-d04b18c12f1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958518363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_stress_pipeline.958518363
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1015208836
Short name T715
Test name
Test status
Simulation time 770731836 ps
CPU time 45.2 seconds
Started Jan 17 02:44:04 PM PST 24
Finished Jan 17 02:44:52 PM PST 24
Peak memory 283988 kb
Host smart-c8a1d5f4-6931-4d01-87e2-41e2f1da7100
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015208836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1015208836
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.337701381
Short name T745
Test name
Test status
Simulation time 28776184406 ps
CPU time 1414.04 seconds
Started Jan 17 02:38:18 PM PST 24
Finished Jan 17 03:01:53 PM PST 24
Peak memory 371720 kb
Host smart-9b5acd1e-050a-432c-ab18-2444bff35439
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337701381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.sram_ctrl_access_during_key_req.337701381
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3326173781
Short name T458
Test name
Test status
Simulation time 36617555 ps
CPU time 0.66 seconds
Started Jan 17 02:33:46 PM PST 24
Finished Jan 17 02:33:47 PM PST 24
Peak memory 201888 kb
Host smart-2b2aa27d-138a-47de-a111-a4580faef339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326173781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3326173781
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.1169094817
Short name T395
Test name
Test status
Simulation time 71270883438 ps
CPU time 1091.81 seconds
Started Jan 17 02:34:31 PM PST 24
Finished Jan 17 02:52:46 PM PST 24
Peak memory 202088 kb
Host smart-e3016010-3b85-4e3f-9656-c684f2f4c8b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169094817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
1169094817
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.534131003
Short name T642
Test name
Test status
Simulation time 63914400802 ps
CPU time 182.39 seconds
Started Jan 17 02:32:39 PM PST 24
Finished Jan 17 02:35:43 PM PST 24
Peak memory 210340 kb
Host smart-89d7235b-6dde-4825-bc85-ce10edfbf304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534131003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca
lation.534131003
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.4095552102
Short name T340
Test name
Test status
Simulation time 751104652 ps
CPU time 68.92 seconds
Started Jan 17 02:33:27 PM PST 24
Finished Jan 17 02:34:36 PM PST 24
Peak memory 287032 kb
Host smart-8ddfc61b-a90a-44c1-a006-475e9116849c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095552102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.4095552102
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2295140568
Short name T360
Test name
Test status
Simulation time 8688354475 ps
CPU time 151.69 seconds
Started Jan 17 02:33:54 PM PST 24
Finished Jan 17 02:36:29 PM PST 24
Peak memory 211160 kb
Host smart-fb2e8f3b-6ab2-4d83-8003-1c65fe0a0ad6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295140568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.2295140568
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.3939789765
Short name T556
Test name
Test status
Simulation time 7892215663 ps
CPU time 125.19 seconds
Started Jan 17 02:32:43 PM PST 24
Finished Jan 17 02:34:49 PM PST 24
Peak memory 202176 kb
Host smart-4ee1cff3-162a-40b3-bf4d-90b864012f8f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939789765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.3939789765
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1695323177
Short name T835
Test name
Test status
Simulation time 3319393660 ps
CPU time 283.51 seconds
Started Jan 17 02:35:03 PM PST 24
Finished Jan 17 02:39:48 PM PST 24
Peak memory 337136 kb
Host smart-1bc674dd-f546-44a1-bdb7-c55a1d341a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695323177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1695323177
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.372727948
Short name T731
Test name
Test status
Simulation time 2981831938 ps
CPU time 26.33 seconds
Started Jan 17 02:33:07 PM PST 24
Finished Jan 17 02:33:37 PM PST 24
Peak memory 202144 kb
Host smart-dc861e1a-fdf2-4aa0-8f50-389747ef512d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372727948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr
am_ctrl_partial_access.372727948
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4130737204
Short name T624
Test name
Test status
Simulation time 72564264904 ps
CPU time 431.79 seconds
Started Jan 17 02:38:18 PM PST 24
Finished Jan 17 02:45:31 PM PST 24
Peak memory 201952 kb
Host smart-48b46344-9bdc-4b43-ae61-3875fe3ccac4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130737204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.4130737204
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.1455658716
Short name T984
Test name
Test status
Simulation time 363631098 ps
CPU time 6.98 seconds
Started Jan 17 02:34:21 PM PST 24
Finished Jan 17 02:34:31 PM PST 24
Peak memory 202452 kb
Host smart-6eafd22f-a37a-4b61-921b-dc314544902d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455658716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1455658716
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.824596149
Short name T475
Test name
Test status
Simulation time 23993102283 ps
CPU time 719.7 seconds
Started Jan 17 02:34:02 PM PST 24
Finished Jan 17 02:46:07 PM PST 24
Peak memory 378004 kb
Host smart-de15bad9-8845-4aad-a23b-744e54ef8b31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824596149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.824596149
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.749810374
Short name T41
Test name
Test status
Simulation time 869698957 ps
CPU time 3.41 seconds
Started Jan 17 02:33:39 PM PST 24
Finished Jan 17 02:33:44 PM PST 24
Peak memory 220960 kb
Host smart-38c40f68-3c33-4604-a10a-3a48012ff686
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749810374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_sec_cm.749810374
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.3402440436
Short name T807
Test name
Test status
Simulation time 3097283824 ps
CPU time 16.03 seconds
Started Jan 17 02:35:02 PM PST 24
Finished Jan 17 02:35:19 PM PST 24
Peak memory 214372 kb
Host smart-884764f9-4641-4095-808e-7facd57b21d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402440436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3402440436
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2092628653
Short name T385
Test name
Test status
Simulation time 1018343094 ps
CPU time 5609.88 seconds
Started Jan 17 02:34:21 PM PST 24
Finished Jan 17 04:07:55 PM PST 24
Peak memory 608240 kb
Host smart-2fddd787-e870-44f2-bd8a-ffc6c8193d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2092628653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2092628653
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3564253145
Short name T49
Test name
Test status
Simulation time 3942656968 ps
CPU time 309.03 seconds
Started Jan 17 02:32:40 PM PST 24
Finished Jan 17 02:37:50 PM PST 24
Peak memory 202212 kb
Host smart-1cb3a28f-5c59-4602-9a7a-67e54daf8177
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564253145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.3564253145
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3068691558
Short name T368
Test name
Test status
Simulation time 718775140 ps
CPU time 39.87 seconds
Started Jan 17 02:38:19 PM PST 24
Finished Jan 17 02:39:00 PM PST 24
Peak memory 270476 kb
Host smart-d44fb53e-9c78-4840-8fa8-6e31ed9962d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068691558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3068691558
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1121711112
Short name T248
Test name
Test status
Simulation time 14044836346 ps
CPU time 1038.15 seconds
Started Jan 17 02:44:36 PM PST 24
Finished Jan 17 03:01:55 PM PST 24
Peak memory 376044 kb
Host smart-6e088b67-bc43-4f12-86ab-b6519722c2d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121711112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1121711112
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2697440732
Short name T29
Test name
Test status
Simulation time 14059279 ps
CPU time 0.65 seconds
Started Jan 17 02:44:49 PM PST 24
Finished Jan 17 02:44:50 PM PST 24
Peak memory 201784 kb
Host smart-45a72861-b357-456b-9224-d0ee5cef2339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697440732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2697440732
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.3789441269
Short name T241
Test name
Test status
Simulation time 138460007437 ps
CPU time 2390.76 seconds
Started Jan 17 02:44:23 PM PST 24
Finished Jan 17 03:24:14 PM PST 24
Peak memory 202076 kb
Host smart-704e7ebe-0f9d-4355-9743-7ec7ac897187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789441269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.3789441269
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.2041478543
Short name T948
Test name
Test status
Simulation time 6014235978 ps
CPU time 1117.66 seconds
Started Jan 17 02:44:37 PM PST 24
Finished Jan 17 03:03:16 PM PST 24
Peak memory 378048 kb
Host smart-fce6e889-3045-4c1a-a53f-dcd677268e43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041478543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.2041478543
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.145283261
Short name T700
Test name
Test status
Simulation time 32530840492 ps
CPU time 95.56 seconds
Started Jan 17 02:44:36 PM PST 24
Finished Jan 17 02:46:13 PM PST 24
Peak memory 210380 kb
Host smart-52aa0f0c-0e96-4259-90de-5cd53c219d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145283261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc
alation.145283261
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.704395401
Short name T603
Test name
Test status
Simulation time 763738690 ps
CPU time 130.89 seconds
Started Jan 17 02:44:22 PM PST 24
Finished Jan 17 02:46:34 PM PST 24
Peak memory 359980 kb
Host smart-6107e48c-c5c1-492c-9ee8-c075a039c505
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704395401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.704395401
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1200896946
Short name T594
Test name
Test status
Simulation time 18235468980 ps
CPU time 146.23 seconds
Started Jan 17 02:44:51 PM PST 24
Finished Jan 17 02:47:18 PM PST 24
Peak memory 211184 kb
Host smart-431aeefe-5744-4b28-b02c-c76fbdf44f9d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200896946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.1200896946
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.1999944666
Short name T322
Test name
Test status
Simulation time 17126855391 ps
CPU time 246.96 seconds
Started Jan 17 02:44:36 PM PST 24
Finished Jan 17 02:48:43 PM PST 24
Peak memory 202232 kb
Host smart-f355e492-5713-4d60-8dc9-562bfaeef2f6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999944666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.1999944666
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.2066686374
Short name T464
Test name
Test status
Simulation time 5829501854 ps
CPU time 1116.72 seconds
Started Jan 17 02:44:24 PM PST 24
Finished Jan 17 03:03:01 PM PST 24
Peak memory 379040 kb
Host smart-85cefab5-138d-473e-adab-78535109c401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066686374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.2066686374
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.1508589027
Short name T956
Test name
Test status
Simulation time 772105478 ps
CPU time 29.71 seconds
Started Jan 17 02:44:23 PM PST 24
Finished Jan 17 02:44:53 PM PST 24
Peak memory 202084 kb
Host smart-aaee293b-cb79-4b29-b251-d2533a90f2e1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508589027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.1508589027
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.122260715
Short name T870
Test name
Test status
Simulation time 45425217703 ps
CPU time 329.18 seconds
Started Jan 17 02:44:23 PM PST 24
Finished Jan 17 02:49:53 PM PST 24
Peak memory 202152 kb
Host smart-4bee31e0-21e4-4107-a649-9704e688cc37
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122260715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.sram_ctrl_partial_access_b2b.122260715
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.1567268375
Short name T931
Test name
Test status
Simulation time 709416713 ps
CPU time 5.47 seconds
Started Jan 17 02:44:36 PM PST 24
Finished Jan 17 02:44:42 PM PST 24
Peak memory 202416 kb
Host smart-0a9aebe2-8748-4417-828a-579ed2defc18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567268375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1567268375
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.1017469649
Short name T821
Test name
Test status
Simulation time 33479723384 ps
CPU time 1036.81 seconds
Started Jan 17 02:44:36 PM PST 24
Finished Jan 17 03:01:53 PM PST 24
Peak memory 372976 kb
Host smart-76b4853c-5343-483e-9edc-1ee988fdadca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017469649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1017469649
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.3785095800
Short name T300
Test name
Test status
Simulation time 502725440 ps
CPU time 8.95 seconds
Started Jan 17 02:44:14 PM PST 24
Finished Jan 17 02:44:26 PM PST 24
Peak memory 202052 kb
Host smart-be1eab77-3551-47e6-8144-a6b53f0d632e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785095800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3785095800
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3980208432
Short name T507
Test name
Test status
Simulation time 4805471570 ps
CPU time 4115.9 seconds
Started Jan 17 02:44:49 PM PST 24
Finished Jan 17 03:53:26 PM PST 24
Peak memory 695712 kb
Host smart-211ecb06-d9aa-4b90-89e8-697822813047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3980208432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3980208432
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.667040575
Short name T738
Test name
Test status
Simulation time 13785120198 ps
CPU time 223.77 seconds
Started Jan 17 02:44:22 PM PST 24
Finished Jan 17 02:48:07 PM PST 24
Peak memory 202144 kb
Host smart-aebc6c76-65bc-4038-ba46-29b0ff315ba8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667040575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_stress_pipeline.667040575
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.57567675
Short name T691
Test name
Test status
Simulation time 766158450 ps
CPU time 124.96 seconds
Started Jan 17 02:44:37 PM PST 24
Finished Jan 17 02:46:42 PM PST 24
Peak memory 345768 kb
Host smart-c5bacfeb-5b61-4e1c-a216-e2194e61b81a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57567675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_throughput_w_partial_write.57567675
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3773768220
Short name T934
Test name
Test status
Simulation time 23566989312 ps
CPU time 1329.33 seconds
Started Jan 17 02:44:58 PM PST 24
Finished Jan 17 03:07:09 PM PST 24
Peak memory 372896 kb
Host smart-0dd8aeaf-aaad-4cc4-aa24-7812f4a72a0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773768220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.3773768220
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.3375683677
Short name T796
Test name
Test status
Simulation time 33511483 ps
CPU time 0.66 seconds
Started Jan 17 02:45:03 PM PST 24
Finished Jan 17 02:45:06 PM PST 24
Peak memory 201444 kb
Host smart-d0ed4805-fbc9-49d9-b1e5-f57d75fd13b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375683677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.3375683677
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.4160949938
Short name T154
Test name
Test status
Simulation time 9541796061 ps
CPU time 641.99 seconds
Started Jan 17 02:44:56 PM PST 24
Finished Jan 17 02:55:40 PM PST 24
Peak memory 202104 kb
Host smart-21756c01-3506-45da-947f-889e7df1b5af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160949938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.4160949938
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.2417994135
Short name T374
Test name
Test status
Simulation time 74731705326 ps
CPU time 189.21 seconds
Started Jan 17 02:44:58 PM PST 24
Finished Jan 17 02:48:09 PM PST 24
Peak memory 214176 kb
Host smart-9b27b292-fce3-4ce7-a455-201245bc1f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417994135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.2417994135
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.2277506713
Short name T502
Test name
Test status
Simulation time 771529078 ps
CPU time 76.63 seconds
Started Jan 17 02:44:58 PM PST 24
Finished Jan 17 02:46:15 PM PST 24
Peak memory 302280 kb
Host smart-568a3618-f762-4d83-aa74-724e8cf6a9e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277506713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.2277506713
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2863232116
Short name T91
Test name
Test status
Simulation time 20406303082 ps
CPU time 157.84 seconds
Started Jan 17 02:44:58 PM PST 24
Finished Jan 17 02:47:37 PM PST 24
Peak memory 211096 kb
Host smart-bb5424eb-5fe9-43de-920a-fa5cafaa8bd0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863232116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.2863232116
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.3250906221
Short name T465
Test name
Test status
Simulation time 13778489450 ps
CPU time 156.66 seconds
Started Jan 17 02:44:57 PM PST 24
Finished Jan 17 02:47:34 PM PST 24
Peak memory 202124 kb
Host smart-eb27c6a7-94d8-4d09-881b-44a5bc326f10
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250906221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.3250906221
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.3560660345
Short name T848
Test name
Test status
Simulation time 2670278675 ps
CPU time 387.3 seconds
Started Jan 17 02:44:51 PM PST 24
Finished Jan 17 02:51:19 PM PST 24
Peak memory 376080 kb
Host smart-c7c3a384-11cd-474e-8772-ce54852336a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560660345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.3560660345
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.3051085561
Short name T858
Test name
Test status
Simulation time 3040021804 ps
CPU time 25.99 seconds
Started Jan 17 02:44:58 PM PST 24
Finished Jan 17 02:45:26 PM PST 24
Peak memory 202108 kb
Host smart-9152bfed-8b76-4802-9303-a1b254aa7368
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051085561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.3051085561
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3329870882
Short name T602
Test name
Test status
Simulation time 83704217628 ps
CPU time 219.67 seconds
Started Jan 17 02:44:57 PM PST 24
Finished Jan 17 02:48:38 PM PST 24
Peak memory 202068 kb
Host smart-628edb79-6532-4e1d-8022-a33f4f545475
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329870882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.3329870882
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2656752200
Short name T39
Test name
Test status
Simulation time 367154110 ps
CPU time 13.09 seconds
Started Jan 17 02:45:01 PM PST 24
Finished Jan 17 02:45:19 PM PST 24
Peak memory 202440 kb
Host smart-83e85ac2-8f58-41a4-9622-c7af2ff40896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656752200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2656752200
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.653848196
Short name T390
Test name
Test status
Simulation time 24439385174 ps
CPU time 770.14 seconds
Started Jan 17 02:44:57 PM PST 24
Finished Jan 17 02:57:49 PM PST 24
Peak memory 380080 kb
Host smart-c513abe0-8c1b-4f83-8984-d49e609272c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653848196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.653848196
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.269327136
Short name T703
Test name
Test status
Simulation time 723833158 ps
CPU time 18.03 seconds
Started Jan 17 02:44:49 PM PST 24
Finished Jan 17 02:45:08 PM PST 24
Peak memory 222492 kb
Host smart-f94a0909-bf90-4380-a335-9e5aecfeae3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269327136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.269327136
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.1907282858
Short name T378
Test name
Test status
Simulation time 1161904908568 ps
CPU time 6897.64 seconds
Started Jan 17 02:45:02 PM PST 24
Finished Jan 17 04:40:04 PM PST 24
Peak memory 372956 kb
Host smart-769db7bd-37f6-4f2c-87df-1566cad974fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907282858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.1907282858
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2140428240
Short name T548
Test name
Test status
Simulation time 386679516 ps
CPU time 2985.54 seconds
Started Jan 17 02:45:03 PM PST 24
Finished Jan 17 03:34:51 PM PST 24
Peak memory 699032 kb
Host smart-54a2ef6e-5f8a-4bf4-9fcc-86e7a21ff51f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2140428240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2140428240
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3697705974
Short name T621
Test name
Test status
Simulation time 5473654395 ps
CPU time 402.22 seconds
Started Jan 17 02:44:57 PM PST 24
Finished Jan 17 02:51:41 PM PST 24
Peak memory 202116 kb
Host smart-c261a642-5d13-4823-b2c7-43701bccdc9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697705974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3697705974
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3696953322
Short name T264
Test name
Test status
Simulation time 5229116197 ps
CPU time 67.71 seconds
Started Jan 17 02:44:59 PM PST 24
Finished Jan 17 02:46:08 PM PST 24
Peak memory 297308 kb
Host smart-4e376a59-b924-498f-9045-6d600940d48f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696953322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3696953322
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3908020458
Short name T801
Test name
Test status
Simulation time 54951515363 ps
CPU time 559.55 seconds
Started Jan 17 02:45:21 PM PST 24
Finished Jan 17 02:54:41 PM PST 24
Peak memory 367364 kb
Host smart-4ab5433e-140f-4cf3-b033-d88c90b74c6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908020458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.3908020458
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.2084179417
Short name T277
Test name
Test status
Simulation time 42580520 ps
CPU time 0.61 seconds
Started Jan 17 02:45:31 PM PST 24
Finished Jan 17 02:45:32 PM PST 24
Peak memory 201444 kb
Host smart-ad1eed95-fe4d-4a9f-9de9-7ff9e707a047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084179417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.2084179417
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1625821949
Short name T354
Test name
Test status
Simulation time 54159358083 ps
CPU time 560.58 seconds
Started Jan 17 02:45:02 PM PST 24
Finished Jan 17 02:54:26 PM PST 24
Peak memory 202228 kb
Host smart-c34aa596-54d2-4537-9366-11efc924c016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625821949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1625821949
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.2678291436
Short name T924
Test name
Test status
Simulation time 17458180257 ps
CPU time 85.37 seconds
Started Jan 17 02:45:21 PM PST 24
Finished Jan 17 02:46:47 PM PST 24
Peak memory 202228 kb
Host smart-03f758b4-6f28-44df-92d1-dcb9a68dd4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678291436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.2678291436
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.2767181023
Short name T447
Test name
Test status
Simulation time 760975112 ps
CPU time 115.55 seconds
Started Jan 17 02:45:23 PM PST 24
Finished Jan 17 02:47:21 PM PST 24
Peak memory 342180 kb
Host smart-45ce3cf3-370f-4554-a2a1-de26d5f77a84
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767181023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.2767181023
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3482714110
Short name T871
Test name
Test status
Simulation time 3309793300 ps
CPU time 83.33 seconds
Started Jan 17 02:45:22 PM PST 24
Finished Jan 17 02:46:45 PM PST 24
Peak memory 211144 kb
Host smart-adec904f-8554-451c-b94c-0353e9e54ce2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482714110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.3482714110
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.2808936845
Short name T974
Test name
Test status
Simulation time 37252665845 ps
CPU time 286.23 seconds
Started Jan 17 02:45:23 PM PST 24
Finished Jan 17 02:50:12 PM PST 24
Peak memory 202204 kb
Host smart-d912c72c-a8bb-477f-a91c-63523b2ec4c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808936845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.2808936845
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.110708705
Short name T363
Test name
Test status
Simulation time 66396996609 ps
CPU time 1476.99 seconds
Started Jan 17 02:45:02 PM PST 24
Finished Jan 17 03:09:43 PM PST 24
Peak memory 377124 kb
Host smart-99de5a4c-38dd-4f66-9dc3-614c147be0bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110708705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip
le_keys.110708705
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.2662775419
Short name T404
Test name
Test status
Simulation time 1843348854 ps
CPU time 130.74 seconds
Started Jan 17 02:45:07 PM PST 24
Finished Jan 17 02:47:19 PM PST 24
Peak memory 364628 kb
Host smart-20fad07b-784f-4387-9573-5f4dcad8007b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662775419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.2662775419
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4270733449
Short name T321
Test name
Test status
Simulation time 17077305109 ps
CPU time 222.71 seconds
Started Jan 17 02:45:08 PM PST 24
Finished Jan 17 02:48:52 PM PST 24
Peak memory 201996 kb
Host smart-3403526b-c961-40c7-9d76-6bb94f7b42fc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270733449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.4270733449
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.2987171810
Short name T606
Test name
Test status
Simulation time 357787585 ps
CPU time 13.97 seconds
Started Jan 17 02:45:23 PM PST 24
Finished Jan 17 02:45:40 PM PST 24
Peak memory 201964 kb
Host smart-851fae6b-b69a-4b18-a35e-9b9b9c1c10eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987171810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2987171810
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.3468195649
Short name T693
Test name
Test status
Simulation time 22843524872 ps
CPU time 1602.93 seconds
Started Jan 17 02:45:25 PM PST 24
Finished Jan 17 03:12:11 PM PST 24
Peak memory 379076 kb
Host smart-c72a9c65-94a4-4e0b-afa0-252dd64b861b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468195649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3468195649
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.3565805647
Short name T510
Test name
Test status
Simulation time 996490605 ps
CPU time 18.33 seconds
Started Jan 17 02:45:03 PM PST 24
Finished Jan 17 02:45:24 PM PST 24
Peak memory 202116 kb
Host smart-48b2f76a-4fb9-46ee-913a-8404f0cafd92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565805647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3565805647
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.2715841056
Short name T742
Test name
Test status
Simulation time 89499323811 ps
CPU time 3375.67 seconds
Started Jan 17 02:45:23 PM PST 24
Finished Jan 17 03:41:42 PM PST 24
Peak memory 387232 kb
Host smart-6f7cdf89-7623-4505-95e1-539e1e70eb20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715841056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.2715841056
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2274875641
Short name T755
Test name
Test status
Simulation time 5245855851 ps
CPU time 383.67 seconds
Started Jan 17 02:45:02 PM PST 24
Finished Jan 17 02:51:29 PM PST 24
Peak memory 202124 kb
Host smart-7a5f5827-ab76-496e-88d8-75539133cfa2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274875641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.2274875641
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1706167501
Short name T408
Test name
Test status
Simulation time 1474615663 ps
CPU time 38.69 seconds
Started Jan 17 02:45:22 PM PST 24
Finished Jan 17 02:46:01 PM PST 24
Peak memory 253912 kb
Host smart-dda882e6-f305-45aa-b5e8-0060eb037b4d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706167501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1706167501
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.587819594
Short name T572
Test name
Test status
Simulation time 20678605967 ps
CPU time 1463.69 seconds
Started Jan 17 02:45:37 PM PST 24
Finished Jan 17 03:10:02 PM PST 24
Peak memory 373732 kb
Host smart-741244f7-d498-49c3-b99e-7cbb78de0b48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587819594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.sram_ctrl_access_during_key_req.587819594
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.787426789
Short name T397
Test name
Test status
Simulation time 12393836 ps
CPU time 0.64 seconds
Started Jan 17 02:45:45 PM PST 24
Finished Jan 17 02:45:46 PM PST 24
Peak memory 201804 kb
Host smart-7ddb9e37-daf7-47bf-a785-7c09b311a2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787426789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.787426789
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.2408120766
Short name T158
Test name
Test status
Simulation time 19036084712 ps
CPU time 677.79 seconds
Started Jan 17 02:45:32 PM PST 24
Finished Jan 17 02:56:50 PM PST 24
Peak memory 202080 kb
Host smart-7cab86bb-3771-4ff4-a1a4-41818f14d23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408120766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.2408120766
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.3713618505
Short name T814
Test name
Test status
Simulation time 26658359857 ps
CPU time 1071.28 seconds
Started Jan 17 02:45:37 PM PST 24
Finished Jan 17 03:03:29 PM PST 24
Peak memory 376056 kb
Host smart-d829aef6-9220-456a-9be7-2391821adc6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713618505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.3713618505
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.1745752124
Short name T832
Test name
Test status
Simulation time 695475881 ps
CPU time 28.83 seconds
Started Jan 17 02:45:37 PM PST 24
Finished Jan 17 02:46:06 PM PST 24
Peak memory 218452 kb
Host smart-90f1728d-e007-4c58-b430-2b2fca4890bd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745752124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.1745752124
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3827060781
Short name T850
Test name
Test status
Simulation time 8855067367 ps
CPU time 149.32 seconds
Started Jan 17 02:45:36 PM PST 24
Finished Jan 17 02:48:06 PM PST 24
Peak memory 218496 kb
Host smart-80805add-01e3-4103-8cad-aab470eea67e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827060781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.3827060781
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.1349744850
Short name T265
Test name
Test status
Simulation time 82656568273 ps
CPU time 294.03 seconds
Started Jan 17 02:45:39 PM PST 24
Finished Jan 17 02:50:33 PM PST 24
Peak memory 202104 kb
Host smart-255c6f1a-8ebc-4a7e-bea8-edc881c16b30
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349744850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.1349744850
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.3251071969
Short name T836
Test name
Test status
Simulation time 10586914410 ps
CPU time 497.31 seconds
Started Jan 17 02:45:31 PM PST 24
Finished Jan 17 02:53:48 PM PST 24
Peak memory 373960 kb
Host smart-9bc439f6-9709-4077-b18f-008ade92a358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251071969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.3251071969
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.3089911075
Short name T854
Test name
Test status
Simulation time 751068861 ps
CPU time 21.65 seconds
Started Jan 17 02:45:30 PM PST 24
Finished Jan 17 02:45:53 PM PST 24
Peak memory 257696 kb
Host smart-71e237ff-419d-43aa-8047-7a8fd13c8fb6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089911075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.3089911075
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1269640601
Short name T553
Test name
Test status
Simulation time 38229418285 ps
CPU time 414.8 seconds
Started Jan 17 02:45:33 PM PST 24
Finished Jan 17 02:52:28 PM PST 24
Peak memory 202156 kb
Host smart-021473c6-6d27-4e61-84aa-67cc52511883
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269640601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.1269640601
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.1459063951
Short name T257
Test name
Test status
Simulation time 358958466 ps
CPU time 6.59 seconds
Started Jan 17 02:45:38 PM PST 24
Finished Jan 17 02:45:45 PM PST 24
Peak memory 202436 kb
Host smart-ae50364f-978a-497f-a82a-a6a29302c098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459063951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1459063951
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.138232643
Short name T569
Test name
Test status
Simulation time 41024643571 ps
CPU time 1464.16 seconds
Started Jan 17 02:45:38 PM PST 24
Finished Jan 17 03:10:04 PM PST 24
Peak memory 379008 kb
Host smart-6805ee66-afd6-4c0c-921d-ed01bef18593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138232643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.138232643
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.2651697563
Short name T350
Test name
Test status
Simulation time 879799848 ps
CPU time 8.52 seconds
Started Jan 17 02:45:32 PM PST 24
Finished Jan 17 02:45:41 PM PST 24
Peak memory 205944 kb
Host smart-5fc63937-01eb-4b1c-a0a8-d4af770069fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651697563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2651697563
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3834851929
Short name T820
Test name
Test status
Simulation time 1737108676 ps
CPU time 3129.73 seconds
Started Jan 17 02:45:36 PM PST 24
Finished Jan 17 03:37:47 PM PST 24
Peak memory 625660 kb
Host smart-ec846fec-a5d8-41ec-9747-a109df96fe03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3834851929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3834851929
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1319355900
Short name T716
Test name
Test status
Simulation time 5570905213 ps
CPU time 184.36 seconds
Started Jan 17 02:45:30 PM PST 24
Finished Jan 17 02:48:35 PM PST 24
Peak memory 202112 kb
Host smart-3874cbc4-f38a-42ba-88cb-ea217676a103
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319355900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1319355900
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2016769797
Short name T249
Test name
Test status
Simulation time 769029586 ps
CPU time 101.37 seconds
Started Jan 17 02:45:36 PM PST 24
Finished Jan 17 02:47:18 PM PST 24
Peak memory 335324 kb
Host smart-6a8d6f9f-cad6-4203-89ee-d801a95909ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016769797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2016769797
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.213530517
Short name T615
Test name
Test status
Simulation time 32132095004 ps
CPU time 1576.08 seconds
Started Jan 17 02:45:53 PM PST 24
Finished Jan 17 03:12:10 PM PST 24
Peak memory 359728 kb
Host smart-ff333eae-7232-4dc4-b893-f8e7d4dc91cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213530517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.sram_ctrl_access_during_key_req.213530517
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.163324306
Short name T912
Test name
Test status
Simulation time 13990260 ps
CPU time 0.63 seconds
Started Jan 17 02:46:12 PM PST 24
Finished Jan 17 02:46:14 PM PST 24
Peak memory 201868 kb
Host smart-b5db2376-14c5-45b5-8904-5060767e16f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163324306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.163324306
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.2946323863
Short name T721
Test name
Test status
Simulation time 871046249175 ps
CPU time 2994.89 seconds
Started Jan 17 02:45:44 PM PST 24
Finished Jan 17 03:35:39 PM PST 24
Peak memory 202044 kb
Host smart-f8054725-553e-4a2b-bdf6-05b20d20494e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946323863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.2946323863
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.255634768
Short name T699
Test name
Test status
Simulation time 64714771105 ps
CPU time 1069.15 seconds
Started Jan 17 02:45:54 PM PST 24
Finished Jan 17 03:03:44 PM PST 24
Peak memory 373980 kb
Host smart-9203bbed-e222-41c5-b2ce-3c50548b5cc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255634768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl
e.255634768
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.2604993340
Short name T42
Test name
Test status
Simulation time 13742752226 ps
CPU time 136.23 seconds
Started Jan 17 02:45:55 PM PST 24
Finished Jan 17 02:48:12 PM PST 24
Peak memory 210400 kb
Host smart-8400ce39-f75e-4318-a5a9-e2321a27d710
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604993340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.2604993340
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3393881127
Short name T907
Test name
Test status
Simulation time 687743985 ps
CPU time 27.5 seconds
Started Jan 17 02:45:56 PM PST 24
Finished Jan 17 02:46:24 PM PST 24
Peak memory 210296 kb
Host smart-29e679d3-8305-47b6-b25b-77f142fded49
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393881127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3393881127
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1866200546
Short name T899
Test name
Test status
Simulation time 2399680744 ps
CPU time 78.76 seconds
Started Jan 17 02:46:04 PM PST 24
Finished Jan 17 02:47:24 PM PST 24
Peak memory 211652 kb
Host smart-74d2c2b7-5f29-4e9b-96db-c586096dd182
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866200546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1866200546
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.953823308
Short name T239
Test name
Test status
Simulation time 76551179736 ps
CPU time 344.28 seconds
Started Jan 17 02:46:04 PM PST 24
Finished Jan 17 02:51:49 PM PST 24
Peak memory 202328 kb
Host smart-1e3c8177-8234-47ad-9281-548961a8d43d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953823308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl
_mem_walk.953823308
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.3529215263
Short name T932
Test name
Test status
Simulation time 26228575847 ps
CPU time 1447.53 seconds
Started Jan 17 02:45:49 PM PST 24
Finished Jan 17 03:09:57 PM PST 24
Peak memory 380168 kb
Host smart-c71211f7-d5ac-45fe-9dca-ab4d21502d28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529215263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.3529215263
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.1040095860
Short name T689
Test name
Test status
Simulation time 707095071 ps
CPU time 12.11 seconds
Started Jan 17 02:45:53 PM PST 24
Finished Jan 17 02:46:06 PM PST 24
Peak memory 202068 kb
Host smart-4461fff3-ff36-4ea9-a70e-53afaf4f64f7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040095860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.1040095860
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1700626418
Short name T387
Test name
Test status
Simulation time 17090456276 ps
CPU time 421.47 seconds
Started Jan 17 02:45:53 PM PST 24
Finished Jan 17 02:52:56 PM PST 24
Peak memory 202144 kb
Host smart-332a9a01-4bb1-42cc-9d05-b4105c03ecb3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700626418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.1700626418
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.3049195965
Short name T482
Test name
Test status
Simulation time 1355538705 ps
CPU time 13.41 seconds
Started Jan 17 02:46:02 PM PST 24
Finished Jan 17 02:46:17 PM PST 24
Peak memory 202444 kb
Host smart-34c9110b-5833-4641-8936-9c32fc26ffab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049195965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3049195965
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.4091057194
Short name T137
Test name
Test status
Simulation time 10836535188 ps
CPU time 1127.66 seconds
Started Jan 17 02:45:55 PM PST 24
Finished Jan 17 03:04:44 PM PST 24
Peak memory 379664 kb
Host smart-9f152369-d6b0-4ed8-a2e0-94135ff6acc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091057194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.4091057194
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.1298080967
Short name T586
Test name
Test status
Simulation time 845976705 ps
CPU time 20.85 seconds
Started Jan 17 02:45:48 PM PST 24
Finished Jan 17 02:46:09 PM PST 24
Peak memory 238112 kb
Host smart-85fa9762-f8d3-4f01-bfd2-c964d0f712bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298080967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1298080967
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.2317850486
Short name T381
Test name
Test status
Simulation time 150860419084 ps
CPU time 2082.54 seconds
Started Jan 17 02:46:13 PM PST 24
Finished Jan 17 03:20:56 PM PST 24
Peak memory 243176 kb
Host smart-28001534-1593-4f41-8568-732659215907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317850486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.2317850486
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.35061200
Short name T640
Test name
Test status
Simulation time 998885696 ps
CPU time 3377.56 seconds
Started Jan 17 02:46:03 PM PST 24
Finished Jan 17 03:42:22 PM PST 24
Peak memory 589552 kb
Host smart-77052c87-bd3b-4855-b42b-9503115b870f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=35061200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.35061200
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2723070672
Short name T307
Test name
Test status
Simulation time 7226516125 ps
CPU time 311.31 seconds
Started Jan 17 02:45:48 PM PST 24
Finished Jan 17 02:51:00 PM PST 24
Peak memory 202168 kb
Host smart-278319e8-2eb3-48d6-a903-fa8c68c1890c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723070672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.2723070672
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.621187676
Short name T273
Test name
Test status
Simulation time 745223717 ps
CPU time 69.16 seconds
Started Jan 17 02:45:53 PM PST 24
Finished Jan 17 02:47:03 PM PST 24
Peak memory 308512 kb
Host smart-ad3c0e2a-0663-473e-9420-38ffe7e6a327
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621187676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_throughput_w_partial_write.621187676
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1074514098
Short name T843
Test name
Test status
Simulation time 11593348749 ps
CPU time 323.87 seconds
Started Jan 17 02:46:14 PM PST 24
Finished Jan 17 02:51:39 PM PST 24
Peak memory 321796 kb
Host smart-6b561f11-1c7c-4c72-b164-112b9cfea3e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074514098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.1074514098
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.3431187330
Short name T916
Test name
Test status
Simulation time 18579389 ps
CPU time 0.71 seconds
Started Jan 17 02:46:35 PM PST 24
Finished Jan 17 02:46:36 PM PST 24
Peak memory 201888 kb
Host smart-d79a0587-fdf6-448f-b026-4d5e44655a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431187330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.3431187330
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.1731357841
Short name T258
Test name
Test status
Simulation time 19197375240 ps
CPU time 489.16 seconds
Started Jan 17 02:46:14 PM PST 24
Finished Jan 17 02:54:23 PM PST 24
Peak memory 202196 kb
Host smart-dc076903-90c4-4cfc-a28d-1258764ec2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731357841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.1731357841
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.3302437879
Short name T977
Test name
Test status
Simulation time 6810904673 ps
CPU time 277 seconds
Started Jan 17 02:46:23 PM PST 24
Finished Jan 17 02:51:01 PM PST 24
Peak memory 339044 kb
Host smart-12d89eb8-d294-4492-a9a7-d6e4a1f46139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302437879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.3302437879
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.3389830744
Short name T772
Test name
Test status
Simulation time 16289964327 ps
CPU time 111.09 seconds
Started Jan 17 02:46:13 PM PST 24
Finished Jan 17 02:48:05 PM PST 24
Peak memory 202156 kb
Host smart-f63ebac0-de79-4b28-b56b-26f5ffe27be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389830744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.3389830744
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.3836391196
Short name T6
Test name
Test status
Simulation time 1533756736 ps
CPU time 154.56 seconds
Started Jan 17 02:46:14 PM PST 24
Finished Jan 17 02:48:49 PM PST 24
Peak memory 365704 kb
Host smart-8968e3e5-df5a-48cb-a47d-2389e9012ab2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836391196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.3836391196
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1069726228
Short name T92
Test name
Test status
Simulation time 6485749749 ps
CPU time 80.71 seconds
Started Jan 17 02:46:22 PM PST 24
Finished Jan 17 02:47:44 PM PST 24
Peak memory 211700 kb
Host smart-b1332bf2-957b-4cb9-a0f7-a787da4e9d53
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069726228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.1069726228
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.914043788
Short name T439
Test name
Test status
Simulation time 8225251258 ps
CPU time 125.2 seconds
Started Jan 17 02:46:24 PM PST 24
Finished Jan 17 02:48:34 PM PST 24
Peak memory 202224 kb
Host smart-6a0d4076-90d8-4755-a710-34be6e5e06a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914043788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl
_mem_walk.914043788
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.2124879988
Short name T662
Test name
Test status
Simulation time 14096529099 ps
CPU time 1303.54 seconds
Started Jan 17 02:46:15 PM PST 24
Finished Jan 17 03:08:00 PM PST 24
Peak memory 381164 kb
Host smart-f9272613-8bed-46b4-b4c6-cbd589f2bb9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124879988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.2124879988
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1211970792
Short name T933
Test name
Test status
Simulation time 875160097 ps
CPU time 159.73 seconds
Started Jan 17 02:46:14 PM PST 24
Finished Jan 17 02:48:54 PM PST 24
Peak memory 364628 kb
Host smart-f627b0bf-b7c1-4b58-964d-74009affb4d3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211970792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1211970792
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3137510814
Short name T357
Test name
Test status
Simulation time 23490970356 ps
CPU time 539.08 seconds
Started Jan 17 02:46:14 PM PST 24
Finished Jan 17 02:55:14 PM PST 24
Peak memory 202172 kb
Host smart-d2b372eb-6ec5-4b67-917a-27d7b8664191
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137510814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.3137510814
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.591743889
Short name T635
Test name
Test status
Simulation time 1342221003 ps
CPU time 5.64 seconds
Started Jan 17 02:46:23 PM PST 24
Finished Jan 17 02:46:29 PM PST 24
Peak memory 202368 kb
Host smart-dd50d070-6ba7-4e87-8bf2-521fc6893ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591743889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.591743889
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.573170581
Short name T509
Test name
Test status
Simulation time 3984307367 ps
CPU time 1124.7 seconds
Started Jan 17 02:46:21 PM PST 24
Finished Jan 17 03:05:08 PM PST 24
Peak memory 371844 kb
Host smart-3add9614-b78e-44d3-8653-2b8a669d3764
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573170581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.573170581
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.2060971705
Short name T751
Test name
Test status
Simulation time 1615219313 ps
CPU time 40.61 seconds
Started Jan 17 02:46:14 PM PST 24
Finished Jan 17 02:46:55 PM PST 24
Peak memory 273840 kb
Host smart-25e9318c-cfbd-491a-961a-58c3fa5c19d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060971705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2060971705
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.1289746000
Short name T139
Test name
Test status
Simulation time 60668381316 ps
CPU time 3833.3 seconds
Started Jan 17 02:46:24 PM PST 24
Finished Jan 17 03:50:22 PM PST 24
Peak memory 383172 kb
Host smart-ab45221b-86e9-492d-8213-e677b90b723b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289746000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.1289746000
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2804783935
Short name T309
Test name
Test status
Simulation time 1107148327 ps
CPU time 4292.64 seconds
Started Jan 17 02:46:23 PM PST 24
Finished Jan 17 03:58:02 PM PST 24
Peak memory 734772 kb
Host smart-6662eab0-8350-40a1-92f9-ceb6fefa6746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2804783935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2804783935
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3556415480
Short name T774
Test name
Test status
Simulation time 12545328121 ps
CPU time 244.04 seconds
Started Jan 17 02:46:15 PM PST 24
Finished Jan 17 02:50:19 PM PST 24
Peak memory 202028 kb
Host smart-39e0d5de-9182-406c-b33a-b4880bfda364
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556415480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.3556415480
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1327447305
Short name T327
Test name
Test status
Simulation time 1489037601 ps
CPU time 42.32 seconds
Started Jan 17 02:46:15 PM PST 24
Finished Jan 17 02:46:58 PM PST 24
Peak memory 267468 kb
Host smart-c5d3af30-bd56-457a-a5e4-feef993c367d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327447305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1327447305
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1130996288
Short name T328
Test name
Test status
Simulation time 13218234306 ps
CPU time 1059.47 seconds
Started Jan 17 02:46:34 PM PST 24
Finished Jan 17 03:04:14 PM PST 24
Peak memory 371008 kb
Host smart-464b46e9-2a4e-462a-aa56-f4d76e38a761
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130996288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.1130996288
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.4042526961
Short name T424
Test name
Test status
Simulation time 48856055 ps
CPU time 0.64 seconds
Started Jan 17 02:46:47 PM PST 24
Finished Jan 17 02:46:49 PM PST 24
Peak memory 201828 kb
Host smart-04abb72f-593c-4f71-9bf5-89288e8e37bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042526961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.4042526961
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.1197428196
Short name T530
Test name
Test status
Simulation time 44187174925 ps
CPU time 2238.32 seconds
Started Jan 17 02:46:34 PM PST 24
Finished Jan 17 03:23:53 PM PST 24
Peak memory 202216 kb
Host smart-774f0e0d-4065-4b4a-9b37-180f37f6a94e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197428196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.1197428196
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.2415687156
Short name T678
Test name
Test status
Simulation time 13688964408 ps
CPU time 106.99 seconds
Started Jan 17 02:46:31 PM PST 24
Finished Jan 17 02:48:19 PM PST 24
Peak memory 202232 kb
Host smart-ab2cdbb8-2e0d-4091-adec-a580bb008cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415687156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.2415687156
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.1967709914
Short name T789
Test name
Test status
Simulation time 2672332422 ps
CPU time 27.45 seconds
Started Jan 17 02:46:31 PM PST 24
Finished Jan 17 02:46:59 PM PST 24
Peak memory 210428 kb
Host smart-ad7a7867-bb0c-4c0a-99bd-5491275e50ab
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967709914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.1967709914
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1579590496
Short name T74
Test name
Test status
Simulation time 3804803604 ps
CPU time 75.3 seconds
Started Jan 17 02:46:41 PM PST 24
Finished Jan 17 02:47:57 PM PST 24
Peak memory 211168 kb
Host smart-3849ab77-812b-4cea-8ee2-709bb4ff8300
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579590496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.1579590496
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.203627069
Short name T872
Test name
Test status
Simulation time 10322338759 ps
CPU time 152.91 seconds
Started Jan 17 02:46:39 PM PST 24
Finished Jan 17 02:49:13 PM PST 24
Peak memory 202108 kb
Host smart-ddf245e9-8130-4aae-ba65-dc4e6457ce09
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203627069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_mem_walk.203627069
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.4252024369
Short name T151
Test name
Test status
Simulation time 19917008415 ps
CPU time 1767.73 seconds
Started Jan 17 02:46:30 PM PST 24
Finished Jan 17 03:15:58 PM PST 24
Peak memory 380068 kb
Host smart-8ca6775e-aed5-4659-80c2-71f0ca39d896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252024369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.4252024369
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.1242806903
Short name T767
Test name
Test status
Simulation time 784373120 ps
CPU time 47.62 seconds
Started Jan 17 02:46:35 PM PST 24
Finished Jan 17 02:47:23 PM PST 24
Peak memory 272616 kb
Host smart-20c19ca4-dab0-421e-8f46-f991e5c742f3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242806903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.1242806903
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4059761670
Short name T868
Test name
Test status
Simulation time 21347765425 ps
CPU time 256.71 seconds
Started Jan 17 02:46:30 PM PST 24
Finished Jan 17 02:50:47 PM PST 24
Peak memory 202092 kb
Host smart-cb9a2b38-3555-4cd4-96b0-c4f3fb48cf3a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059761670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.4059761670
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.1816037402
Short name T480
Test name
Test status
Simulation time 354863262 ps
CPU time 6.55 seconds
Started Jan 17 02:46:38 PM PST 24
Finished Jan 17 02:46:46 PM PST 24
Peak memory 202216 kb
Host smart-3f8337d1-46ac-4175-853e-741e6e290bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816037402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1816037402
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.3563422785
Short name T547
Test name
Test status
Simulation time 16001133982 ps
CPU time 1032.8 seconds
Started Jan 17 02:46:39 PM PST 24
Finished Jan 17 03:03:53 PM PST 24
Peak memory 377024 kb
Host smart-19faffae-3056-4316-88db-fb71ed95e824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563422785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3563422785
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.683878140
Short name T320
Test name
Test status
Simulation time 1619729883 ps
CPU time 37.06 seconds
Started Jan 17 02:46:29 PM PST 24
Finished Jan 17 02:47:07 PM PST 24
Peak memory 202288 kb
Host smart-6b7d9887-ed73-4e87-a7b1-2bb9fe0b12b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683878140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.683878140
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2939352307
Short name T57
Test name
Test status
Simulation time 507628968 ps
CPU time 6229.76 seconds
Started Jan 17 02:46:39 PM PST 24
Finished Jan 17 04:30:30 PM PST 24
Peak memory 654888 kb
Host smart-f4717852-f1a6-4284-86d2-16026eb63419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2939352307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2939352307
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1077363700
Short name T613
Test name
Test status
Simulation time 14346956391 ps
CPU time 299.16 seconds
Started Jan 17 02:46:31 PM PST 24
Finished Jan 17 02:51:31 PM PST 24
Peak memory 202204 kb
Host smart-a70d7b8b-3d8f-4789-b239-e7002214fb93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077363700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1077363700
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2983636827
Short name T245
Test name
Test status
Simulation time 883104584 ps
CPU time 103.29 seconds
Started Jan 17 02:46:30 PM PST 24
Finished Jan 17 02:48:14 PM PST 24
Peak memory 321780 kb
Host smart-ae76e7e3-cef8-49db-a195-c7760b9a2c77
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983636827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2983636827
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3187757561
Short name T927
Test name
Test status
Simulation time 15135116746 ps
CPU time 381.78 seconds
Started Jan 17 02:46:56 PM PST 24
Finished Jan 17 02:53:18 PM PST 24
Peak memory 341384 kb
Host smart-0bbe3bce-b24c-43b2-840e-079e5a16a4cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187757561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.3187757561
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.3026706712
Short name T719
Test name
Test status
Simulation time 23202311 ps
CPU time 0.65 seconds
Started Jan 17 02:47:01 PM PST 24
Finished Jan 17 02:47:02 PM PST 24
Peak memory 201448 kb
Host smart-93a876fa-4ed4-4e0f-9696-8093f581e2e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026706712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.3026706712
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.1296607714
Short name T888
Test name
Test status
Simulation time 58090797218 ps
CPU time 1939.05 seconds
Started Jan 17 02:46:47 PM PST 24
Finished Jan 17 03:19:07 PM PST 24
Peak memory 202160 kb
Host smart-66a1e238-3c24-4c4b-b7f3-5527992f2df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296607714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.1296607714
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3717276230
Short name T685
Test name
Test status
Simulation time 12312168433 ps
CPU time 305.17 seconds
Started Jan 17 02:46:59 PM PST 24
Finished Jan 17 02:52:05 PM PST 24
Peak memory 210420 kb
Host smart-1712f586-8d40-4a72-a511-bc85965bb4fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717276230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3717276230
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3177820633
Short name T392
Test name
Test status
Simulation time 773173408 ps
CPU time 67.85 seconds
Started Jan 17 02:46:48 PM PST 24
Finished Jan 17 02:47:57 PM PST 24
Peak memory 295204 kb
Host smart-cfb45fdb-71a7-482c-9110-36e1a6f3d4e2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177820633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3177820633
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2159298619
Short name T570
Test name
Test status
Simulation time 10625745464 ps
CPU time 82.84 seconds
Started Jan 17 02:46:54 PM PST 24
Finished Jan 17 02:48:19 PM PST 24
Peak memory 218492 kb
Host smart-53dd35fb-f345-416d-8bde-b358bf9a1a71
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159298619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.2159298619
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.3132141292
Short name T592
Test name
Test status
Simulation time 13908819876 ps
CPU time 298.94 seconds
Started Jan 17 02:46:54 PM PST 24
Finished Jan 17 02:51:55 PM PST 24
Peak memory 202228 kb
Host smart-95470449-f163-4644-b9c9-6da531eb5a84
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132141292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.3132141292
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.4234222569
Short name T725
Test name
Test status
Simulation time 93480539970 ps
CPU time 1243.48 seconds
Started Jan 17 02:46:48 PM PST 24
Finished Jan 17 03:07:32 PM PST 24
Peak memory 381276 kb
Host smart-85acdcbe-139d-4c8f-bc3f-6311ee8585bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234222569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.4234222569
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.3429304449
Short name T706
Test name
Test status
Simulation time 425094944 ps
CPU time 37.89 seconds
Started Jan 17 02:46:47 PM PST 24
Finished Jan 17 02:47:26 PM PST 24
Peak memory 268652 kb
Host smart-4957752a-6341-473a-8939-bec37a52744e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429304449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.3429304449
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1664676905
Short name T377
Test name
Test status
Simulation time 40023900113 ps
CPU time 246.98 seconds
Started Jan 17 02:46:47 PM PST 24
Finished Jan 17 02:50:55 PM PST 24
Peak memory 202164 kb
Host smart-f681d2a4-ff9b-48a4-8dad-c9ba29e67f85
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664676905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.1664676905
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.1774153598
Short name T365
Test name
Test status
Simulation time 752487734 ps
CPU time 6.53 seconds
Started Jan 17 02:46:54 PM PST 24
Finished Jan 17 02:47:03 PM PST 24
Peak memory 202408 kb
Host smart-f4afbe15-1875-4eec-9a05-c530312cd97f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774153598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1774153598
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3038220942
Short name T852
Test name
Test status
Simulation time 45794806310 ps
CPU time 701.12 seconds
Started Jan 17 02:46:55 PM PST 24
Finished Jan 17 02:58:38 PM PST 24
Peak memory 376796 kb
Host smart-7ef03e95-12d0-4d4f-af04-79139611c1e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038220942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3038220942
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.2393571799
Short name T4
Test name
Test status
Simulation time 3307692543 ps
CPU time 28.43 seconds
Started Jan 17 02:46:46 PM PST 24
Finished Jan 17 02:47:15 PM PST 24
Peak memory 202152 kb
Host smart-4546a6e1-ae47-47f9-bae0-0f1bdd464170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393571799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2393571799
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2933757553
Short name T786
Test name
Test status
Simulation time 433409878 ps
CPU time 5131.45 seconds
Started Jan 17 02:47:00 PM PST 24
Finished Jan 17 04:12:32 PM PST 24
Peak memory 610748 kb
Host smart-2c107056-6150-485b-8f4c-45d5dcd0d3e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2933757553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2933757553
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3084177316
Short name T352
Test name
Test status
Simulation time 5782641751 ps
CPU time 431.66 seconds
Started Jan 17 02:46:48 PM PST 24
Finished Jan 17 02:54:02 PM PST 24
Peak memory 202144 kb
Host smart-566f7cfa-b9b7-47d1-bff8-12a4c9809262
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084177316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.3084177316
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1189854553
Short name T318
Test name
Test status
Simulation time 770294676 ps
CPU time 66.07 seconds
Started Jan 17 02:46:53 PM PST 24
Finished Jan 17 02:48:02 PM PST 24
Peak memory 297108 kb
Host smart-db381fc0-ab31-4ad8-b3d9-f27c0f82c05c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189854553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1189854553
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.573953248
Short name T356
Test name
Test status
Simulation time 8841578884 ps
CPU time 1758.01 seconds
Started Jan 17 02:47:14 PM PST 24
Finished Jan 17 03:16:33 PM PST 24
Peak memory 373116 kb
Host smart-ad8c56c5-5a6e-4a70-bf3b-37063df863e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573953248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 48.sram_ctrl_access_during_key_req.573953248
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.1873060328
Short name T481
Test name
Test status
Simulation time 14290250 ps
CPU time 0.65 seconds
Started Jan 17 02:47:28 PM PST 24
Finished Jan 17 02:47:30 PM PST 24
Peak memory 201876 kb
Host smart-c12b69c0-1a01-4cde-a1b6-9216ec8762f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873060328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.1873060328
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.1234417833
Short name T514
Test name
Test status
Simulation time 368253845937 ps
CPU time 2181 seconds
Started Jan 17 02:46:59 PM PST 24
Finished Jan 17 03:23:21 PM PST 24
Peak memory 202160 kb
Host smart-1c2ca04e-ce30-4dff-9b9f-9adb00418294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234417833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.1234417833
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.385759964
Short name T985
Test name
Test status
Simulation time 48227974890 ps
CPU time 155.74 seconds
Started Jan 17 02:47:14 PM PST 24
Finished Jan 17 02:49:51 PM PST 24
Peak memory 210420 kb
Host smart-8a7c545a-f643-48f8-abfe-5b60f7c2e443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385759964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc
alation.385759964
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.750510401
Short name T588
Test name
Test status
Simulation time 1033443316 ps
CPU time 141.56 seconds
Started Jan 17 02:47:09 PM PST 24
Finished Jan 17 02:49:34 PM PST 24
Peak memory 358528 kb
Host smart-f08c3781-3ebf-4b9c-a60d-b73370010758
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750510401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.sram_ctrl_max_throughput.750510401
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.835123721
Short name T610
Test name
Test status
Simulation time 19911173600 ps
CPU time 167.78 seconds
Started Jan 17 02:47:21 PM PST 24
Finished Jan 17 02:50:09 PM PST 24
Peak memory 211048 kb
Host smart-38a00eec-626a-43b3-b56c-0f73ab3f8961
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835123721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_mem_partial_access.835123721
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.932517122
Short name T909
Test name
Test status
Simulation time 16421377540 ps
CPU time 248.39 seconds
Started Jan 17 02:47:20 PM PST 24
Finished Jan 17 02:51:30 PM PST 24
Peak memory 202016 kb
Host smart-0af64a0b-d94b-4e6d-ba13-ed0f06f5fd5e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932517122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl
_mem_walk.932517122
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.3467064009
Short name T16
Test name
Test status
Simulation time 75017591220 ps
CPU time 992.48 seconds
Started Jan 17 02:46:58 PM PST 24
Finished Jan 17 03:03:31 PM PST 24
Peak memory 380128 kb
Host smart-f3e30d53-ccf5-41e9-b89b-28fbe16604e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467064009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.3467064009
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.2604636271
Short name T884
Test name
Test status
Simulation time 1604584238 ps
CPU time 31.63 seconds
Started Jan 17 02:47:11 PM PST 24
Finished Jan 17 02:47:45 PM PST 24
Peak memory 202088 kb
Host smart-85b53450-125b-4028-93d3-c85965040242
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604636271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.2604636271
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.558122076
Short name T695
Test name
Test status
Simulation time 24103781604 ps
CPU time 541.58 seconds
Started Jan 17 02:47:10 PM PST 24
Finished Jan 17 02:56:15 PM PST 24
Peak memory 202144 kb
Host smart-fc926726-25b6-4175-9a59-8ebfbab5e1a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558122076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.sram_ctrl_partial_access_b2b.558122076
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1032759784
Short name T826
Test name
Test status
Simulation time 707169509 ps
CPU time 13.71 seconds
Started Jan 17 02:47:21 PM PST 24
Finished Jan 17 02:47:35 PM PST 24
Peak memory 202404 kb
Host smart-fc29e69a-f655-4cf0-b90c-b915c2652a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032759784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1032759784
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.1015621688
Short name T523
Test name
Test status
Simulation time 12922486996 ps
CPU time 280.66 seconds
Started Jan 17 02:47:15 PM PST 24
Finished Jan 17 02:51:56 PM PST 24
Peak memory 366584 kb
Host smart-a0070982-6e43-4a42-8e2e-1763565e0c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015621688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1015621688
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.180725494
Short name T849
Test name
Test status
Simulation time 1166348690 ps
CPU time 61.12 seconds
Started Jan 17 02:47:00 PM PST 24
Finished Jan 17 02:48:01 PM PST 24
Peak memory 303328 kb
Host smart-c970fa13-4d04-4cde-8a5e-ff3775a843e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180725494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.180725494
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.911446907
Short name T489
Test name
Test status
Simulation time 4156693061 ps
CPU time 5171.02 seconds
Started Jan 17 02:47:20 PM PST 24
Finished Jan 17 04:13:32 PM PST 24
Peak memory 789288 kb
Host smart-27e9f463-d8ad-4a59-9903-cdc41711bae0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=911446907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.911446907
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2688734502
Short name T335
Test name
Test status
Simulation time 16487838964 ps
CPU time 336.3 seconds
Started Jan 17 02:47:08 PM PST 24
Finished Jan 17 02:52:49 PM PST 24
Peak memory 202168 kb
Host smart-6b403353-2647-482e-b880-da400108997c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688734502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.2688734502
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.4129215899
Short name T623
Test name
Test status
Simulation time 5585155469 ps
CPU time 180.25 seconds
Started Jan 17 02:47:16 PM PST 24
Finished Jan 17 02:50:17 PM PST 24
Peak memory 373248 kb
Host smart-3fa17760-5716-4d30-b5f3-141435c08826
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129215899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.4129215899
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.457098149
Short name T291
Test name
Test status
Simulation time 3844724268 ps
CPU time 611.96 seconds
Started Jan 17 02:47:34 PM PST 24
Finished Jan 17 02:57:47 PM PST 24
Peak memory 353448 kb
Host smart-75d9951e-31b7-48c1-8248-5f2306d4c274
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457098149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.sram_ctrl_access_during_key_req.457098149
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.2690296456
Short name T27
Test name
Test status
Simulation time 23375357 ps
CPU time 0.68 seconds
Started Jan 17 02:47:54 PM PST 24
Finished Jan 17 02:47:56 PM PST 24
Peak memory 202100 kb
Host smart-22d5f5f1-bcd1-43a7-ab4d-c1033437d811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690296456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.2690296456
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2477991115
Short name T336
Test name
Test status
Simulation time 9445977850 ps
CPU time 570.35 seconds
Started Jan 17 02:47:34 PM PST 24
Finished Jan 17 02:57:05 PM PST 24
Peak memory 202144 kb
Host smart-03e87ebe-0939-48e2-8c82-ca2ae8dba0bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477991115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2477991115
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.3398596412
Short name T953
Test name
Test status
Simulation time 8240565830 ps
CPU time 223.98 seconds
Started Jan 17 02:47:38 PM PST 24
Finished Jan 17 02:51:22 PM PST 24
Peak memory 210424 kb
Host smart-e976f046-731b-4183-a0fb-b233a97d11fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398596412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.3398596412
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.2637613859
Short name T450
Test name
Test status
Simulation time 2800992533 ps
CPU time 39.49 seconds
Started Jan 17 02:47:34 PM PST 24
Finished Jan 17 02:48:15 PM PST 24
Peak memory 253380 kb
Host smart-d39a786e-36b2-44c3-b5a5-aee16f57f3d0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637613859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.2637613859
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2006617396
Short name T383
Test name
Test status
Simulation time 9970113738 ps
CPU time 156.43 seconds
Started Jan 17 02:47:43 PM PST 24
Finished Jan 17 02:50:21 PM PST 24
Peak memory 211580 kb
Host smart-cd008d9a-722c-4e88-a4be-37e1cec9d2f5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006617396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2006617396
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.1954464139
Short name T744
Test name
Test status
Simulation time 13779180823 ps
CPU time 290.8 seconds
Started Jan 17 02:47:43 PM PST 24
Finished Jan 17 02:52:36 PM PST 24
Peak memory 202188 kb
Host smart-8dd69cf9-7984-45b4-a586-10d6e390c72d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954464139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.1954464139
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.271170897
Short name T470
Test name
Test status
Simulation time 112463403393 ps
CPU time 1797.77 seconds
Started Jan 17 02:47:37 PM PST 24
Finished Jan 17 03:17:36 PM PST 24
Peak memory 380164 kb
Host smart-17f08a63-89b3-48c5-bd42-cd8e46e70817
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271170897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip
le_keys.271170897
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.4192609556
Short name T631
Test name
Test status
Simulation time 9213425028 ps
CPU time 100.59 seconds
Started Jan 17 02:47:34 PM PST 24
Finished Jan 17 02:49:15 PM PST 24
Peak memory 363740 kb
Host smart-8d5a0f9e-25c8-4aad-998f-8c6317e2e018
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192609556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.4192609556
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3096841444
Short name T393
Test name
Test status
Simulation time 8029346741 ps
CPU time 516.37 seconds
Started Jan 17 02:47:35 PM PST 24
Finished Jan 17 02:56:12 PM PST 24
Peak memory 202124 kb
Host smart-80326cf4-e22f-49ad-b02a-593f01666c98
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096841444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.3096841444
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.1808124430
Short name T533
Test name
Test status
Simulation time 693395384 ps
CPU time 13.6 seconds
Started Jan 17 02:47:46 PM PST 24
Finished Jan 17 02:48:01 PM PST 24
Peak memory 202336 kb
Host smart-5266b1c0-119c-439e-8ece-7761a3110e53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808124430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1808124430
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.2385224505
Short name T784
Test name
Test status
Simulation time 14172560880 ps
CPU time 1298.91 seconds
Started Jan 17 02:47:44 PM PST 24
Finished Jan 17 03:09:26 PM PST 24
Peak memory 378068 kb
Host smart-40c1c7c1-cc96-4d56-8ae0-0f659361a31c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385224505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2385224505
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.856360153
Short name T746
Test name
Test status
Simulation time 3141168534 ps
CPU time 14.75 seconds
Started Jan 17 02:47:31 PM PST 24
Finished Jan 17 02:47:46 PM PST 24
Peak memory 202144 kb
Host smart-a5d7ccc3-a8b6-456e-bc5d-375952ca67cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856360153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.856360153
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.2729628096
Short name T591
Test name
Test status
Simulation time 1173609458876 ps
CPU time 7875.12 seconds
Started Jan 17 02:47:43 PM PST 24
Finished Jan 17 04:59:00 PM PST 24
Peak memory 377036 kb
Host smart-69d7d905-e29e-4739-b1fe-a634f24afd5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729628096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.2729628096
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4215262154
Short name T391
Test name
Test status
Simulation time 5116101759 ps
CPU time 4219.87 seconds
Started Jan 17 02:47:44 PM PST 24
Finished Jan 17 03:58:07 PM PST 24
Peak memory 640336 kb
Host smart-d12a569b-a631-4bb0-abe5-bdebb633225b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4215262154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.4215262154
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3210825069
Short name T527
Test name
Test status
Simulation time 13091204525 ps
CPU time 236.93 seconds
Started Jan 17 02:47:37 PM PST 24
Finished Jan 17 02:51:34 PM PST 24
Peak memory 202208 kb
Host smart-f2a81510-90fa-405d-a6a5-d71efef2ec16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210825069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.3210825069
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3895560071
Short name T896
Test name
Test status
Simulation time 699645736 ps
CPU time 27.25 seconds
Started Jan 17 02:47:34 PM PST 24
Finished Jan 17 02:48:02 PM PST 24
Peak memory 210368 kb
Host smart-f7fa6ecc-64a2-441b-80ce-e72578da9e18
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895560071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3895560071
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2653505511
Short name T284
Test name
Test status
Simulation time 10479634582 ps
CPU time 253.93 seconds
Started Jan 17 02:33:00 PM PST 24
Finished Jan 17 02:37:16 PM PST 24
Peak memory 314628 kb
Host smart-904b4dc7-9433-49d6-a1ed-0222c5679e45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653505511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.2653505511
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.725658508
Short name T577
Test name
Test status
Simulation time 43033498 ps
CPU time 0.66 seconds
Started Jan 17 02:34:36 PM PST 24
Finished Jan 17 02:34:39 PM PST 24
Peak memory 201444 kb
Host smart-9a6b8211-3247-4da3-82c2-231d13f6a6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725658508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.725658508
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.390594455
Short name T376
Test name
Test status
Simulation time 123005474382 ps
CPU time 1706.38 seconds
Started Jan 17 02:32:54 PM PST 24
Finished Jan 17 03:01:21 PM PST 24
Peak memory 202256 kb
Host smart-a211d1fe-1496-4a2a-9c98-dd83203fd092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390594455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.390594455
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.1621034869
Short name T831
Test name
Test status
Simulation time 17735393158 ps
CPU time 204.86 seconds
Started Jan 17 02:32:57 PM PST 24
Finished Jan 17 02:36:23 PM PST 24
Peak memory 202140 kb
Host smart-b9b49130-86ef-4d79-8b40-bf234e791310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621034869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.1621034869
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.3409775813
Short name T251
Test name
Test status
Simulation time 726977530 ps
CPU time 41.62 seconds
Started Jan 17 02:33:00 PM PST 24
Finished Jan 17 02:33:44 PM PST 24
Peak memory 251268 kb
Host smart-53c5d5e3-4a8d-4b34-b06d-8f9578792b33
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409775813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.3409775813
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1074745540
Short name T471
Test name
Test status
Simulation time 5185873667 ps
CPU time 151.49 seconds
Started Jan 17 02:33:44 PM PST 24
Finished Jan 17 02:36:18 PM PST 24
Peak memory 211760 kb
Host smart-47cf3e70-e566-40b4-882f-d5740d55737d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074745540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.1074745540
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.1809914724
Short name T371
Test name
Test status
Simulation time 17906460779 ps
CPU time 253.8 seconds
Started Jan 17 02:32:57 PM PST 24
Finished Jan 17 02:37:12 PM PST 24
Peak memory 202128 kb
Host smart-7c44cdb3-bbb1-43dd-87d9-e2cea7887a86
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809914724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.1809914724
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.156579797
Short name T617
Test name
Test status
Simulation time 53969745246 ps
CPU time 1363.4 seconds
Started Jan 17 02:32:46 PM PST 24
Finished Jan 17 02:55:34 PM PST 24
Peak memory 380052 kb
Host smart-7bfa9f72-25f3-4d57-9e89-5daa58e5dddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156579797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl
e_keys.156579797
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.1158318850
Short name T837
Test name
Test status
Simulation time 479846979 ps
CPU time 64.26 seconds
Started Jan 17 02:32:58 PM PST 24
Finished Jan 17 02:34:06 PM PST 24
Peak memory 316632 kb
Host smart-a1e99c14-b4bb-461d-8fdb-bd7d0073af58
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158318850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.1158318850
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.157945696
Short name T853
Test name
Test status
Simulation time 17597583560 ps
CPU time 436.43 seconds
Started Jan 17 02:32:55 PM PST 24
Finished Jan 17 02:40:13 PM PST 24
Peak memory 202028 kb
Host smart-86fc32c4-9429-4599-bf39-de5d37fc1e8c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157945696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_partial_access_b2b.157945696
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.2292690687
Short name T287
Test name
Test status
Simulation time 1273544874 ps
CPU time 14.22 seconds
Started Jan 17 02:33:19 PM PST 24
Finished Jan 17 02:33:34 PM PST 24
Peak memory 202452 kb
Host smart-f98fe16d-6ac9-4598-ad91-87310fb404e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292690687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2292690687
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.3390538693
Short name T763
Test name
Test status
Simulation time 3571053989 ps
CPU time 879.13 seconds
Started Jan 17 02:33:32 PM PST 24
Finished Jan 17 02:48:12 PM PST 24
Peak memory 376608 kb
Host smart-f37d8c19-f31e-4294-be65-67d5de70317c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390538693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3390538693
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.2593319934
Short name T873
Test name
Test status
Simulation time 783650935 ps
CPU time 157.66 seconds
Started Jan 17 02:34:05 PM PST 24
Finished Jan 17 02:36:45 PM PST 24
Peak memory 370764 kb
Host smart-2258d4d0-ffcc-49d6-81f3-2033f210e491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593319934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2593319934
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.3802681155
Short name T802
Test name
Test status
Simulation time 88810785598 ps
CPU time 6489.95 seconds
Started Jan 17 02:35:08 PM PST 24
Finished Jan 17 04:23:20 PM PST 24
Peak memory 381108 kb
Host smart-d3f9726b-4edc-4a96-9004-a20182336e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802681155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.3802681155
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.773719284
Short name T583
Test name
Test status
Simulation time 3938024016 ps
CPU time 3661.6 seconds
Started Jan 17 02:34:56 PM PST 24
Finished Jan 17 03:35:59 PM PST 24
Peak memory 712684 kb
Host smart-b157232f-cbe6-4b9b-bb54-a46e0c2d53bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=773719284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.773719284
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2963312861
Short name T253
Test name
Test status
Simulation time 8929169192 ps
CPU time 368.12 seconds
Started Jan 17 02:33:40 PM PST 24
Finished Jan 17 02:39:49 PM PST 24
Peak memory 202156 kb
Host smart-a164b8a1-a177-4ba5-887d-ba2b4acb798b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963312861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.2963312861
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.727843650
Short name T453
Test name
Test status
Simulation time 5999593307 ps
CPU time 172.91 seconds
Started Jan 17 02:32:56 PM PST 24
Finished Jan 17 02:35:50 PM PST 24
Peak memory 367848 kb
Host smart-98d160cc-57c5-4f80-a84f-1e713d8c1c51
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727843650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.727843650
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3449789275
Short name T957
Test name
Test status
Simulation time 2432146949 ps
CPU time 450.03 seconds
Started Jan 17 02:34:00 PM PST 24
Finished Jan 17 02:41:31 PM PST 24
Peak memory 355556 kb
Host smart-28cf8b26-bd4c-4866-869b-9efb18257549
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449789275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.3449789275
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.1065732837
Short name T608
Test name
Test status
Simulation time 53869352 ps
CPU time 0.65 seconds
Started Jan 17 02:33:04 PM PST 24
Finished Jan 17 02:33:07 PM PST 24
Peak memory 201564 kb
Host smart-5868822e-a665-4142-924c-9cf09a0c5df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065732837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.1065732837
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.660358993
Short name T487
Test name
Test status
Simulation time 179578722556 ps
CPU time 2793.44 seconds
Started Jan 17 02:33:02 PM PST 24
Finished Jan 17 03:19:37 PM PST 24
Peak memory 202208 kb
Host smart-62d57832-9e9a-4830-92b6-bca4f654bf8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660358993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.660358993
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.4186657066
Short name T433
Test name
Test status
Simulation time 2416724044 ps
CPU time 571.43 seconds
Started Jan 17 02:33:32 PM PST 24
Finished Jan 17 02:43:05 PM PST 24
Peak memory 375916 kb
Host smart-9d198bed-0ef5-4c9c-966c-4c78743614a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186657066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.4186657066
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.2350142729
Short name T152
Test name
Test status
Simulation time 8104262088 ps
CPU time 18.16 seconds
Started Jan 17 02:33:23 PM PST 24
Finished Jan 17 02:33:42 PM PST 24
Peak memory 210392 kb
Host smart-e12acda7-2f14-4d57-af16-4a8c629ed97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350142729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.2350142729
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.3646155975
Short name T542
Test name
Test status
Simulation time 3039079036 ps
CPU time 77.23 seconds
Started Jan 17 02:33:00 PM PST 24
Finished Jan 17 02:34:19 PM PST 24
Peak memory 311604 kb
Host smart-59909fbd-ef37-4396-bdc0-5b83fc9d61a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646155975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.3646155975
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2230483235
Short name T798
Test name
Test status
Simulation time 4663206858 ps
CPU time 80.23 seconds
Started Jan 17 02:33:01 PM PST 24
Finished Jan 17 02:34:23 PM PST 24
Peak memory 211148 kb
Host smart-244c183f-0311-4347-954a-2a1f2a2f9c8c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230483235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.2230483235
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.1351560501
Short name T275
Test name
Test status
Simulation time 4110378734 ps
CPU time 251.64 seconds
Started Jan 17 02:33:32 PM PST 24
Finished Jan 17 02:37:45 PM PST 24
Peak memory 202072 kb
Host smart-87279712-ca66-44e7-8df8-67e7d149cf8e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351560501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.1351560501
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.1579718959
Short name T490
Test name
Test status
Simulation time 27124389792 ps
CPU time 1174.85 seconds
Started Jan 17 02:35:37 PM PST 24
Finished Jan 17 02:55:18 PM PST 24
Peak memory 379984 kb
Host smart-00ba3e50-ae37-4360-bb09-7783f295874b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579718959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.1579718959
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.468071703
Short name T355
Test name
Test status
Simulation time 2636900130 ps
CPU time 31.41 seconds
Started Jan 17 02:33:44 PM PST 24
Finished Jan 17 02:34:18 PM PST 24
Peak memory 202156 kb
Host smart-3f215cc1-496e-4bf5-87bb-56555113f8ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468071703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.468071703
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2365944334
Short name T161
Test name
Test status
Simulation time 9413057104 ps
CPU time 330.41 seconds
Started Jan 17 02:33:04 PM PST 24
Finished Jan 17 02:38:36 PM PST 24
Peak memory 202128 kb
Host smart-d9bf0e5d-063a-4fd0-bd1a-560631af1bb6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365944334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.2365944334
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.3446763384
Short name T312
Test name
Test status
Simulation time 3372955744 ps
CPU time 6.23 seconds
Started Jan 17 02:34:52 PM PST 24
Finished Jan 17 02:35:01 PM PST 24
Peak memory 202540 kb
Host smart-342612da-046b-424d-8197-7139f6c20297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446763384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3446763384
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3219569119
Short name T894
Test name
Test status
Simulation time 4901124289 ps
CPU time 1539.82 seconds
Started Jan 17 02:33:07 PM PST 24
Finished Jan 17 02:58:50 PM PST 24
Peak memory 377032 kb
Host smart-96fff40d-c448-4d52-9662-b34ebc05ee34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219569119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3219569119
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.2172148667
Short name T855
Test name
Test status
Simulation time 793553094 ps
CPU time 164.68 seconds
Started Jan 17 02:34:16 PM PST 24
Finished Jan 17 02:37:02 PM PST 24
Peak memory 375084 kb
Host smart-ec365b96-6dd2-4b8c-83b6-2a04b2b7238a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172148667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2172148667
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.3984786994
Short name T885
Test name
Test status
Simulation time 73679436953 ps
CPU time 4720.46 seconds
Started Jan 17 02:34:20 PM PST 24
Finished Jan 17 03:53:03 PM PST 24
Peak memory 380144 kb
Host smart-a6026bbc-f389-4e4e-a06c-9ba97b9caaa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984786994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.3984786994
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3782382324
Short name T687
Test name
Test status
Simulation time 1717570738 ps
CPU time 2485.39 seconds
Started Jan 17 02:32:59 PM PST 24
Finished Jan 17 03:14:28 PM PST 24
Peak memory 587308 kb
Host smart-f1fa7a55-5c7c-4003-9c56-8ecea0db3e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3782382324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3782382324
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1509583068
Short name T636
Test name
Test status
Simulation time 60538559731 ps
CPU time 384.82 seconds
Started Jan 17 02:34:58 PM PST 24
Finished Jan 17 02:41:28 PM PST 24
Peak memory 202172 kb
Host smart-ac6a892f-7839-4149-a5cf-eb23aa6d19eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509583068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.1509583068
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2079727651
Short name T20
Test name
Test status
Simulation time 703565280 ps
CPU time 26.07 seconds
Started Jan 17 02:33:27 PM PST 24
Finished Jan 17 02:33:54 PM PST 24
Peak memory 210352 kb
Host smart-c9a8f464-279e-4a71-9c51-63f28c845d58
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079727651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2079727651
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1770741619
Short name T743
Test name
Test status
Simulation time 6797082147 ps
CPU time 720.06 seconds
Started Jan 17 02:33:23 PM PST 24
Finished Jan 17 02:45:24 PM PST 24
Peak memory 353380 kb
Host smart-fdf64d69-9c96-49be-bb6e-4d75665649b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770741619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.1770741619
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.320673224
Short name T825
Test name
Test status
Simulation time 11668206 ps
CPU time 0.64 seconds
Started Jan 17 02:33:39 PM PST 24
Finished Jan 17 02:33:41 PM PST 24
Peak memory 201884 kb
Host smart-8608a7bc-b50c-476d-9104-92e82e58322a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320673224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.320673224
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.2012809398
Short name T665
Test name
Test status
Simulation time 313494904261 ps
CPU time 1871.62 seconds
Started Jan 17 02:33:23 PM PST 24
Finished Jan 17 03:04:36 PM PST 24
Peak memory 202168 kb
Host smart-0a9995b3-0ee9-4fbb-8501-d273052e7242
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012809398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
2012809398
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.2513927643
Short name T136
Test name
Test status
Simulation time 5976064566 ps
CPU time 157.95 seconds
Started Jan 17 02:33:16 PM PST 24
Finished Jan 17 02:35:57 PM PST 24
Peak memory 308528 kb
Host smart-17005c87-3506-4303-950d-5cb460c8df2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513927643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.2513927643
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.4262336283
Short name T468
Test name
Test status
Simulation time 768258565 ps
CPU time 101.98 seconds
Started Jan 17 02:33:33 PM PST 24
Finished Jan 17 02:35:16 PM PST 24
Peak memory 321704 kb
Host smart-ed090897-0958-44db-9aab-ef9825746d08
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262336283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.4262336283
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1756368256
Short name T701
Test name
Test status
Simulation time 1823117816 ps
CPU time 75.85 seconds
Started Jan 17 02:33:31 PM PST 24
Finished Jan 17 02:34:48 PM PST 24
Peak memory 211168 kb
Host smart-ab19d8e7-f376-4898-80cc-c45cdfbc6e1f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756368256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.1756368256
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.923643947
Short name T898
Test name
Test status
Simulation time 53013371144 ps
CPU time 305.56 seconds
Started Jan 17 02:33:42 PM PST 24
Finished Jan 17 02:38:52 PM PST 24
Peak memory 202160 kb
Host smart-9f43a456-e5d3-4641-bcd6-461d4553b29c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923643947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_
mem_walk.923643947
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.3966413525
Short name T803
Test name
Test status
Simulation time 8354828369 ps
CPU time 907.92 seconds
Started Jan 17 02:35:07 PM PST 24
Finished Jan 17 02:50:17 PM PST 24
Peak memory 378076 kb
Host smart-8745c03a-15eb-4e54-8beb-0139970de6ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966413525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.3966413525
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.126597943
Short name T598
Test name
Test status
Simulation time 8357269365 ps
CPU time 28.69 seconds
Started Jan 17 02:35:18 PM PST 24
Finished Jan 17 02:35:47 PM PST 24
Peak memory 202164 kb
Host smart-53a61824-de7d-426d-a617-40dd6ba892ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126597943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr
am_ctrl_partial_access.126597943
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3035195128
Short name T713
Test name
Test status
Simulation time 13681603494 ps
CPU time 318.41 seconds
Started Jan 17 02:33:07 PM PST 24
Finished Jan 17 02:38:29 PM PST 24
Peak memory 202200 kb
Host smart-52a5b584-8478-4a67-8763-fbb69d7354b8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035195128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.3035195128
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3997161958
Short name T585
Test name
Test status
Simulation time 713415926 ps
CPU time 6.7 seconds
Started Jan 17 02:33:25 PM PST 24
Finished Jan 17 02:33:32 PM PST 24
Peak memory 202404 kb
Host smart-ea5af259-8700-48d2-ae9a-e5186df33180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997161958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3997161958
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.1513144943
Short name T511
Test name
Test status
Simulation time 9053636525 ps
CPU time 1014.92 seconds
Started Jan 17 02:33:16 PM PST 24
Finished Jan 17 02:50:14 PM PST 24
Peak memory 375972 kb
Host smart-154ed2fc-0f12-4fd4-b5f5-bb3af62cf9fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513144943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1513144943
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.211502428
Short name T962
Test name
Test status
Simulation time 5284593228 ps
CPU time 28.07 seconds
Started Jan 17 02:33:10 PM PST 24
Finished Jan 17 02:33:40 PM PST 24
Peak memory 202192 kb
Host smart-9f727203-2646-44fb-b1eb-0265bb23faa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211502428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.211502428
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.3201129100
Short name T472
Test name
Test status
Simulation time 181864793375 ps
CPU time 4635.81 seconds
Started Jan 17 02:33:15 PM PST 24
Finished Jan 17 03:50:36 PM PST 24
Peak memory 388300 kb
Host smart-76548eb0-fdaf-4122-9354-3d3bb9fc9579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201129100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.3201129100
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.240263474
Short name T804
Test name
Test status
Simulation time 790737507 ps
CPU time 2426.14 seconds
Started Jan 17 02:33:31 PM PST 24
Finished Jan 17 03:13:58 PM PST 24
Peak memory 591556 kb
Host smart-730eb70f-63d5-4880-b09a-b02278bcb31d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=240263474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.240263474
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.966123824
Short name T923
Test name
Test status
Simulation time 4865386139 ps
CPU time 323.64 seconds
Started Jan 17 02:33:55 PM PST 24
Finished Jan 17 02:39:21 PM PST 24
Peak memory 202152 kb
Host smart-e57fb92c-2a28-4d17-9c55-1f6d4e2cd47b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966123824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_stress_pipeline.966123824
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1951409950
Short name T612
Test name
Test status
Simulation time 3629505296 ps
CPU time 58.64 seconds
Started Jan 17 02:33:14 PM PST 24
Finished Jan 17 02:34:18 PM PST 24
Peak memory 284040 kb
Host smart-252e4fe9-c313-461d-8115-28ff7a7f5f99
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951409950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1951409950
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2395988585
Short name T290
Test name
Test status
Simulation time 55598380889 ps
CPU time 478.48 seconds
Started Jan 17 02:33:50 PM PST 24
Finished Jan 17 02:41:50 PM PST 24
Peak memory 329068 kb
Host smart-524e5041-c4a4-4dcd-8f3c-b2e029f03cc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395988585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2395988585
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.3666418186
Short name T398
Test name
Test status
Simulation time 51351482 ps
CPU time 0.66 seconds
Started Jan 17 02:35:45 PM PST 24
Finished Jan 17 02:35:47 PM PST 24
Peak memory 201432 kb
Host smart-a80eadf6-42b4-4724-a9ff-6cae79da5e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666418186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.3666418186
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.1411467481
Short name T498
Test name
Test status
Simulation time 81121201927 ps
CPU time 1407.42 seconds
Started Jan 17 02:38:20 PM PST 24
Finished Jan 17 03:01:49 PM PST 24
Peak memory 201960 kb
Host smart-3e30092d-b03c-415d-a6bb-5c0e26f67e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411467481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
1411467481
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.836263797
Short name T47
Test name
Test status
Simulation time 9198963774 ps
CPU time 579.63 seconds
Started Jan 17 02:34:11 PM PST 24
Finished Jan 17 02:43:51 PM PST 24
Peak memory 370012 kb
Host smart-bb3eb075-11d3-4d4a-a830-65ec506d9a3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836263797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable
.836263797
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.2070872481
Short name T272
Test name
Test status
Simulation time 9944704240 ps
CPU time 103.82 seconds
Started Jan 17 02:34:37 PM PST 24
Finished Jan 17 02:36:23 PM PST 24
Peak memory 210448 kb
Host smart-72417b2d-e6a8-42c0-a518-b232aa71efb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070872481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.2070872481
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.3741766237
Short name T160
Test name
Test status
Simulation time 2696375961 ps
CPU time 60.59 seconds
Started Jan 17 02:37:41 PM PST 24
Finished Jan 17 02:38:44 PM PST 24
Peak memory 301480 kb
Host smart-ce2eb6ba-27fe-4177-9b79-45e989e29c88
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741766237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.3741766237
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1639893602
Short name T286
Test name
Test status
Simulation time 21397906114 ps
CPU time 84.54 seconds
Started Jan 17 02:33:26 PM PST 24
Finished Jan 17 02:34:51 PM PST 24
Peak memory 218492 kb
Host smart-c83be7dd-2a0b-485c-9157-ca14650ec6ee
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639893602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1639893602
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.3694525636
Short name T573
Test name
Test status
Simulation time 17950652414 ps
CPU time 136.19 seconds
Started Jan 17 02:34:45 PM PST 24
Finished Jan 17 02:37:02 PM PST 24
Peak memory 202268 kb
Host smart-3a2b97af-4ca6-443a-a31d-0223a3c6e783
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694525636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.3694525636
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.3102840835
Short name T839
Test name
Test status
Simulation time 9358166870 ps
CPU time 1304.05 seconds
Started Jan 17 02:34:40 PM PST 24
Finished Jan 17 02:56:25 PM PST 24
Peak memory 372916 kb
Host smart-9e7c2f9e-6e89-47d1-8d69-a64d5f5f5dc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102840835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.3102840835
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.2449504348
Short name T303
Test name
Test status
Simulation time 1318179019 ps
CPU time 80.1 seconds
Started Jan 17 02:37:39 PM PST 24
Finished Jan 17 02:39:03 PM PST 24
Peak memory 352944 kb
Host smart-0149d93a-e49b-48d6-bbe5-7140b9a9f2da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449504348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.2449504348
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4042701536
Short name T299
Test name
Test status
Simulation time 26210975280 ps
CPU time 435.25 seconds
Started Jan 17 02:33:35 PM PST 24
Finished Jan 17 02:40:54 PM PST 24
Peak memory 202124 kb
Host smart-3a22a94f-b3d5-45e2-b365-75e8f6a4a99b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042701536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.4042701536
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.1211506437
Short name T283
Test name
Test status
Simulation time 347293677 ps
CPU time 13.7 seconds
Started Jan 17 02:33:24 PM PST 24
Finished Jan 17 02:33:38 PM PST 24
Peak memory 202436 kb
Host smart-be2911f2-2aa1-41ba-82c6-16a3aee73c74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211506437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1211506437
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.2734227867
Short name T400
Test name
Test status
Simulation time 9002160225 ps
CPU time 488.86 seconds
Started Jan 17 02:33:23 PM PST 24
Finished Jan 17 02:41:33 PM PST 24
Peak memory 367820 kb
Host smart-fc49b6d1-b4dc-4238-8105-3135d0ba6000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734227867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2734227867
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.2346141379
Short name T416
Test name
Test status
Simulation time 4946982216 ps
CPU time 14.39 seconds
Started Jan 17 02:33:17 PM PST 24
Finished Jan 17 02:33:34 PM PST 24
Peak memory 202160 kb
Host smart-3248d554-4f08-4885-8355-d6bc2dd25c5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346141379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2346141379
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.2570506124
Short name T905
Test name
Test status
Simulation time 313388239110 ps
CPU time 6728.75 seconds
Started Jan 17 02:33:44 PM PST 24
Finished Jan 17 04:25:56 PM PST 24
Peak memory 382296 kb
Host smart-66af9816-5049-4168-ade1-16694d5be27f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570506124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.2570506124
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1752967248
Short name T660
Test name
Test status
Simulation time 1344248076 ps
CPU time 3846.96 seconds
Started Jan 17 02:34:02 PM PST 24
Finished Jan 17 03:38:15 PM PST 24
Peak memory 540744 kb
Host smart-59c6e77e-e48d-4107-954d-007a1e8969b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1752967248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1752967248
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4193897008
Short name T952
Test name
Test status
Simulation time 22784165103 ps
CPU time 447.9 seconds
Started Jan 17 02:34:17 PM PST 24
Finished Jan 17 02:41:47 PM PST 24
Peak memory 202156 kb
Host smart-f9641fa3-61bc-4674-b863-9c673038170c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193897008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.4193897008
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3546066646
Short name T632
Test name
Test status
Simulation time 720660415 ps
CPU time 29.08 seconds
Started Jan 17 02:35:59 PM PST 24
Finished Jan 17 02:36:29 PM PST 24
Peak memory 234612 kb
Host smart-e17cddf9-56d4-4886-baec-cca28635d734
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546066646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3546066646
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1286143919
Short name T726
Test name
Test status
Simulation time 11106936187 ps
CPU time 619.48 seconds
Started Jan 17 02:37:39 PM PST 24
Finished Jan 17 02:48:02 PM PST 24
Peak memory 376624 kb
Host smart-8f91c755-f477-4f81-9496-f59e1c7c4c12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286143919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.1286143919
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.545827277
Short name T444
Test name
Test status
Simulation time 12013975 ps
CPU time 0.65 seconds
Started Jan 17 02:36:00 PM PST 24
Finished Jan 17 02:36:01 PM PST 24
Peak memory 201824 kb
Host smart-06418753-b74a-4b16-a6ff-47937106768a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545827277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.545827277
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.2423964107
Short name T243
Test name
Test status
Simulation time 200081408720 ps
CPU time 946.9 seconds
Started Jan 17 02:34:17 PM PST 24
Finished Jan 17 02:50:05 PM PST 24
Peak memory 202184 kb
Host smart-e85c3c61-e93d-4862-b2d9-8d9b618c4dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423964107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
2423964107
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.4192572335
Short name T971
Test name
Test status
Simulation time 3460388667 ps
CPU time 34.81 seconds
Started Jan 17 02:34:19 PM PST 24
Finished Jan 17 02:34:54 PM PST 24
Peak memory 243584 kb
Host smart-b407e6c0-cad9-4884-950e-bdfd01619e7d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192572335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.4192572335
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3011425957
Short name T407
Test name
Test status
Simulation time 2393371679 ps
CPU time 72.08 seconds
Started Jan 17 02:38:02 PM PST 24
Finished Jan 17 02:39:19 PM PST 24
Peak memory 211468 kb
Host smart-77bfffea-d8a8-4f16-9d15-d02df0e26df7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011425957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.3011425957
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.812280299
Short name T520
Test name
Test status
Simulation time 4112693722 ps
CPU time 234.93 seconds
Started Jan 17 02:37:39 PM PST 24
Finished Jan 17 02:41:38 PM PST 24
Peak memory 201652 kb
Host smart-bb2aa1fb-1ccc-4e39-ba89-488e2c375ec5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812280299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
mem_walk.812280299
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.2662493017
Short name T890
Test name
Test status
Simulation time 50889841568 ps
CPU time 851.6 seconds
Started Jan 17 02:34:58 PM PST 24
Finished Jan 17 02:49:15 PM PST 24
Peak memory 377136 kb
Host smart-0e4e0301-bb6a-40fc-b1a4-d89f80907bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662493017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.2662493017
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.823598253
Short name T584
Test name
Test status
Simulation time 1008406176 ps
CPU time 143.76 seconds
Started Jan 17 02:35:45 PM PST 24
Finished Jan 17 02:38:10 PM PST 24
Peak memory 373824 kb
Host smart-01631d73-393e-491c-b19b-9c6508b57209
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823598253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr
am_ctrl_partial_access.823598253
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2149647799
Short name T120
Test name
Test status
Simulation time 6637317026 ps
CPU time 403.37 seconds
Started Jan 17 02:35:48 PM PST 24
Finished Jan 17 02:42:32 PM PST 24
Peak memory 202208 kb
Host smart-52776434-0d4c-4b1b-9d45-01d543582405
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149647799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2149647799
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.3406921051
Short name T242
Test name
Test status
Simulation time 1406156205 ps
CPU time 7.03 seconds
Started Jan 17 02:33:59 PM PST 24
Finished Jan 17 02:34:08 PM PST 24
Peak memory 202396 kb
Host smart-29bdd871-2f17-4c17-a1fe-9952b59368b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406921051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3406921051
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.1265297814
Short name T979
Test name
Test status
Simulation time 9900721430 ps
CPU time 459.68 seconds
Started Jan 17 02:37:41 PM PST 24
Finished Jan 17 02:45:23 PM PST 24
Peak memory 375812 kb
Host smart-ff8ee829-4108-4c12-86cc-8c618e2ea42e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265297814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1265297814
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.2083535000
Short name T879
Test name
Test status
Simulation time 6512384684 ps
CPU time 35.42 seconds
Started Jan 17 02:33:47 PM PST 24
Finished Jan 17 02:34:23 PM PST 24
Peak memory 202172 kb
Host smart-a24f9ac2-b050-4da4-9b09-0fd9f627a998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083535000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2083535000
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.2520096985
Short name T969
Test name
Test status
Simulation time 344694711804 ps
CPU time 9391.11 seconds
Started Jan 17 02:34:09 PM PST 24
Finished Jan 17 05:10:42 PM PST 24
Peak memory 382172 kb
Host smart-35541fcf-6e74-4ec6-aab0-04ab961c9404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520096985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.2520096985
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1721228466
Short name T512
Test name
Test status
Simulation time 328745016 ps
CPU time 2946.62 seconds
Started Jan 17 02:38:18 PM PST 24
Finished Jan 17 03:27:26 PM PST 24
Peak memory 676212 kb
Host smart-3fab0f40-e072-4882-92f5-3578e13fe200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1721228466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1721228466
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2497222302
Short name T121
Test name
Test status
Simulation time 18607117036 ps
CPU time 302.19 seconds
Started Jan 17 02:34:26 PM PST 24
Finished Jan 17 02:39:30 PM PST 24
Peak memory 202152 kb
Host smart-9d7c42c2-9251-4f70-b527-98a12b144356
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497222302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.2497222302
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3450966062
Short name T156
Test name
Test status
Simulation time 5904887768 ps
CPU time 122.77 seconds
Started Jan 17 02:33:53 PM PST 24
Finished Jan 17 02:35:56 PM PST 24
Peak memory 350324 kb
Host smart-39868b5f-e9b3-4729-a999-963b14dbbfba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450966062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3450966062
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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