Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14951638

1

T2

4336

T3

5440

T4

61886

full_word

135973674

1

T2

44474

T3

53774

T4

3237

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	150925042	1			T2	48810		T3	59214		T4	65123
auto[TlIntgErrCmd]	87	1			T43	8		T44	5		T104	6
auto[TlIntgErrData]	88	1			T43	5		T44	10		T104	6
auto[TlIntgErrBoth]	95	1			T43	7		T44	5		T104	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73000283

1

T2

24426

T3

29782

T4

32505

auto[1]

77925029

1

T2

24384

T3

29432

T4

32618

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7357645	1			T2	2210		T3	2745		T4	32205
auto[TlIntgErrNone]	partial	auto[1]	7593747	1			T2	2126		T3	2695		T4	29681
auto[TlIntgErrNone]	full_word	auto[0]	65642517	1			T2	22216		T3	27037		T4	300
auto[TlIntgErrNone]	full_word	auto[1]	70331133	1			T2	22258		T3	26737		T4	2937
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T43	2		T44	3		T104	5
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T43	6		T44	1		T104	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T44	1		T113	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T90	1		T114	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T43	3		T44	4		T104	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T43	1		T44	4		T104	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T43	1		T44	2		T72	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T104	1		T111	1		T90	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T43	2		T44	2		T104	5
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T43	4		T44	3		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T43	1		T72	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T111	1		T109	2		-	-