Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	796344	1			T10	2145		T12	8676		T15	29087
auto[1]	10326066	1			T2	16175		T3	10337		T4	3867
auto[2]	622288	1			T10	1613		T12	7790		T15	24649
auto[3]	10166048	1			T2	16118		T3	10149		T4	3952

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13328871	1			T2	26744		T3	16932		T4	12
auto[1]	2048018	1			T2	2668		T3	1698		T4	168
auto[2]	2083689	1			T2	2631		T3	1683		T4	455
auto[3]	4450168	1			T2	250		T3	173		T4	7184

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8639247

1

T2

32291

T3

20486

T4

7819

auto[1]

13271499

1

T2

2

T12

1

T13

266619

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	322465	1			T10	1786		T12	7186		T6	15
auto[0]	auto[0]	auto[1]	33275	1			T10	179		T12	723		T6	1
auto[0]	auto[0]	auto[2]	33131	1			T10	159		T12	695		T15	1
auto[0]	auto[0]	auto[3]	52324	1			T10	21		T12	71		T15	4
auto[0]	auto[1]	auto[0]	2807135	1			T2	13317		T3	8534		T5	10
auto[0]	auto[1]	auto[1]	304460	1			T2	1385		T3	821		T4	31
auto[0]	auto[1]	auto[2]	328912	1			T2	1348		T3	895		T4	122
auto[0]	auto[1]	auto[3]	551725	1			T2	125		T3	87		T4	3714
auto[0]	auto[2]	auto[0]	233150	1			T10	1365		T12	6422		T6	16
auto[0]	auto[2]	auto[1]	27354	1			T10	134		T12	701		T127	289
auto[0]	auto[2]	auto[2]	23337	1			T10	104		T12	590		T127	393
auto[0]	auto[2]	auto[3]	37924	1			T10	10		T12	77		T15	1
auto[0]	auto[3]	auto[0]	2727411	1			T2	13425		T3	8398		T4	12
auto[0]	auto[3]	auto[1]	315800	1			T2	1283		T3	877		T4	137
auto[0]	auto[3]	auto[2]	334077	1			T2	1283		T3	788		T4	333
auto[0]	auto[3]	auto[3]	506767	1			T2	125		T3	86		T4	3470
auto[1]	auto[0]	auto[0]	11551	1			T12	1		T15	923		T103	553
auto[1]	auto[0]	auto[1]	52478	1			T15	4281		T103	2345		T126	1511
auto[1]	auto[0]	auto[2]	52777	1			T15	4314		T103	2374		T126	1500
auto[1]	auto[0]	auto[3]	238343	1			T15	19564		T103	10598		T126	6837
auto[1]	auto[1]	auto[0]	3608962	1			T13	109473		T94	2016		T15	157
auto[1]	auto[1]	auto[1]	649988	1			T13	11319		T16	1		T94	9017
auto[1]	auto[1]	auto[2]	625891	1			T13	11010		T17	1		T94	8950
auto[1]	auto[1]	auto[3]	1448993	1			T13	1071		T94	40790		T15	19635
auto[1]	auto[2]	auto[0]	10201	1			T15	869		T127	2		T103	477
auto[1]	auto[2]	auto[1]	45664	1			T15	3941		T103	2211		T126	934
auto[1]	auto[2]	auto[2]	44572	1			T15	3585		T103	1537		T126	1670
auto[1]	auto[2]	auto[3]	200086	1			T15	16253		T103	7031		T126	7225
auto[1]	auto[3]	auto[0]	3607996	1			T2	2		T13	110320		T16	1
auto[1]	auto[3]	auto[1]	618999	1			T13	11146		T94	8929		T15	331
auto[1]	auto[3]	auto[2]	640992	1			T13	11113		T94	9045		T15	3784
auto[1]	auto[3]	auto[3]	1414006	1			T13	1167		T94	40913		T15	16504