Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	959562625	124857	0	0
ctrl_regwen_rd_A	959562625	9708	0	0
exec_rd_A	959562625	8696	0	0
exec_regwen_rd_A	959562625	9696	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959562625	124857	0	0
T9	8448	0	0	0
T26	810	0	0	0
T27	1005	0	0	0
T30	99759	2026	0	0
T31	0	596	0	0
T32	0	1787	0	0
T34	35688	0	0	0
T37	688281	0	0	0
T38	894644	0	0	0
T39	160668	0	0	0
T43	0	4	0	0
T44	0	1	0	0
T45	0	29	0	0
T46	0	688	0	0
T47	0	17	0	0
T48	0	217	0	0
T49	0	6	0	0
T53	394119	0	0	0
T54	691472	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959562625	9708	0	0
T9	8448	0	0	0
T26	810	0	0	0
T27	1005	0	0	0
T30	99759	436	0	0
T32	0	427	0	0
T34	35688	0	0	0
T37	688281	0	0	0
T38	894644	0	0	0
T39	160668	0	0	0
T45	0	6	0	0
T47	0	31	0	0
T49	0	13	0	0
T51	0	56	0	0
T53	394119	0	0	0
T54	691472	0	0	0
T55	0	127	0	0
T56	0	23	0	0
T61	0	7	0	0
T98	0	9	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959562625	8696	0	0
T9	8448	0	0	0
T26	810	0	0	0
T27	1005	0	0	0
T30	99759	338	0	0
T32	0	382	0	0
T34	35688	0	0	0
T37	688281	0	0	0
T38	894644	0	0	0
T39	160668	0	0	0
T45	0	8	0	0
T47	0	24	0	0
T49	0	20	0	0
T51	0	36	0	0
T53	394119	0	0	0
T54	691472	0	0	0
T55	0	46	0	0
T56	0	15	0	0
T61	0	9	0	0
T98	0	7	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959562625	9696	0	0
T9	8448	0	0	0
T26	810	0	0	0
T27	1005	0	0	0
T30	99759	382	0	0
T32	0	335	0	0
T34	35688	0	0	0
T37	688281	0	0	0
T38	894644	0	0	0
T39	160668	0	0	0
T45	0	3	0	0
T47	0	21	0	0
T49	0	7	0	0
T51	0	65	0	0
T53	394119	0	0	0
T54	691472	0	0	0
T55	0	64	0	0
T56	0	17	0	0
T98	0	7	0	0
T105	0	44	0	0