Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14744686	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122651255

1

T2

98303

T3

150888

T4

1643

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	67327994	1			T2	32768		T3	83110		T4	16207
values[0x0]	33569514	1			T2	32789		T3	40087		T4	5254
values[0x1]	36498433	1			T2	32746		T3	42727		T4	11106

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7527330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

129868611

1

T2

98303

T3

158396

T4

14750

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	449601	1			T2	347		T3	656		T4	4
valid_sources[0x01]	443318	1			T2	323		T3	632		T5	17
valid_sources[0x02]	438562	1			T2	351		T3	660		T5	10
valid_sources[0x03]	792023	1			T2	500		T3	607		T5	22
valid_sources[0x04]	444693	1			T2	460		T3	618		T5	5
valid_sources[0x05]	487487	1			T2	334		T3	653		T5	16
valid_sources[0x06]	439329	1			T2	331		T3	656		T5	18
valid_sources[0x07]	464299	1			T2	427		T3	668		T4	6
valid_sources[0x08]	466877	1			T2	459		T3	663		T5	29
valid_sources[0x09]	1953052	1			T2	250		T3	689		T4	349
valid_sources[0x0a]	485738	1			T2	343		T3	632		T5	20
valid_sources[0x0b]	449828	1			T2	401		T3	636		T5	25
valid_sources[0x0c]	432219	1			T2	423		T3	640		T4	689
valid_sources[0x0d]	1688939	1			T2	304		T3	669		T5	19
valid_sources[0x0e]	461490	1			T2	352		T3	652		T5	22
valid_sources[0x0f]	450052	1			T2	297		T3	666		T5	32
valid_sources[0x10]	446785	1			T2	414		T3	607		T4	165
valid_sources[0x11]	429611	1			T2	506		T3	602		T4	296
valid_sources[0x12]	517440	1			T2	402		T3	643		T5	19
valid_sources[0x13]	2696275	1			T2	378		T3	642		T5	22
valid_sources[0x14]	446159	1			T2	274		T3	619		T4	140
valid_sources[0x15]	447401	1			T2	526		T3	624		T4	48
valid_sources[0x16]	484259	1			T2	305		T3	628		T4	2
valid_sources[0x17]	478968	1			T2	445		T3	632		T4	209
valid_sources[0x18]	443620	1			T2	358		T3	645		T5	12
valid_sources[0x19]	434351	1			T2	475		T3	665		T4	1717
valid_sources[0x1a]	445249	1			T2	365		T3	618		T5	18
valid_sources[0x1b]	461257	1			T2	295		T3	641		T4	236
valid_sources[0x1c]	446670	1			T2	359		T3	645		T5	16
valid_sources[0x1d]	440392	1			T2	342		T3	652		T4	97
valid_sources[0x1e]	437490	1			T2	311		T3	639		T4	723
valid_sources[0x1f]	459866	1			T2	319		T3	686		T4	430
valid_sources[0x20]	452421	1			T2	326		T3	658		T4	4
valid_sources[0x21]	468825	1			T2	348		T3	651		T5	20
valid_sources[0x22]	481265	1			T2	357		T3	635		T5	21
valid_sources[0x23]	433610	1			T2	307		T3	641		T4	94
valid_sources[0x24]	478374	1			T2	468		T3	637		T5	23
valid_sources[0x25]	452180	1			T2	332		T3	605		T6	3261
valid_sources[0x26]	450784	1			T2	494		T3	702		T4	253
valid_sources[0x27]	962353	1			T2	345		T3	684		T4	88
valid_sources[0x28]	467959	1			T2	378		T3	695		T5	10
valid_sources[0x29]	438351	1			T2	402		T3	640		T5	26
valid_sources[0x2a]	472320	1			T2	298		T3	681		T4	1
valid_sources[0x2b]	1428568	1			T2	454		T3	595		T4	530
valid_sources[0x2c]	453063	1			T2	401		T3	680		T5	23
valid_sources[0x2d]	430108	1			T2	403		T3	689		T5	19
valid_sources[0x2e]	476536	1			T2	379		T3	663		T5	8
valid_sources[0x2f]	492120	1			T2	312		T3	622		T5	20
valid_sources[0x30]	473323	1			T2	586		T3	702		T5	24
valid_sources[0x31]	474837	1			T2	409		T3	662		T5	43
valid_sources[0x32]	593719	1			T2	303		T3	637		T4	140
valid_sources[0x33]	438729	1			T2	369		T3	642		T5	11
valid_sources[0x34]	470420	1			T2	346		T3	667		T6	3260
valid_sources[0x35]	438202	1			T2	374		T3	630		T4	132
valid_sources[0x36]	449398	1			T2	400		T3	674		T5	17
valid_sources[0x37]	447723	1			T2	320		T3	606		T5	12
valid_sources[0x38]	471016	1			T2	430		T3	612		T5	21
valid_sources[0x39]	650322	1			T2	270		T3	677		T5	19
valid_sources[0x3a]	467869	1			T2	466		T3	619		T5	10
valid_sources[0x3b]	1158712	1			T2	513		T3	656		T5	19
valid_sources[0x3c]	442435	1			T2	411		T3	705		T5	13
valid_sources[0x3d]	1213785	1			T2	386		T3	613		T5	6
valid_sources[0x3e]	555030	1			T2	441		T3	714		T5	10
valid_sources[0x3f]	438732	1			T2	374		T3	646		T4	341
valid_sources[0x40]	437310	1			T2	405		T3	630		T5	13
valid_sources[0x41]	429670	1			T2	258		T3	611		T4	363
valid_sources[0x42]	473239	1			T2	435		T3	680		T5	14
valid_sources[0x43]	430124	1			T2	407		T3	687		T5	23
valid_sources[0x44]	452303	1			T2	365		T3	687		T5	17
valid_sources[0x45]	463933	1			T2	482		T3	662		T4	98
valid_sources[0x46]	437719	1			T2	276		T3	660		T4	445
valid_sources[0x47]	430953	1			T2	295		T3	647		T5	8
valid_sources[0x48]	492811	1			T2	388		T3	654		T4	168
valid_sources[0x49]	646149	1			T2	386		T3	653		T5	12
valid_sources[0x4a]	484813	1			T2	387		T3	707		T4	89
valid_sources[0x4b]	433129	1			T2	380		T3	693		T5	16
valid_sources[0x4c]	448654	1			T2	420		T3	661		T5	6
valid_sources[0x4d]	527217	1			T2	428		T3	646		T5	11
valid_sources[0x4e]	434666	1			T2	403		T3	612		T5	13
valid_sources[0x4f]	464538	1			T2	252		T3	699		T5	13
valid_sources[0x50]	455504	1			T2	518		T3	661		T5	14
valid_sources[0x51]	479608	1			T2	336		T3	683		T5	20
valid_sources[0x52]	478485	1			T2	412		T3	687		T5	25
valid_sources[0x53]	429190	1			T2	421		T3	628		T4	281
valid_sources[0x54]	543577	1			T2	417		T3	677		T5	9
valid_sources[0x55]	433708	1			T2	397		T3	641		T5	16
valid_sources[0x56]	466187	1			T2	468		T3	657		T5	18
valid_sources[0x57]	438001	1			T2	312		T3	590		T5	10
valid_sources[0x58]	1050487	1			T2	419		T3	657		T5	30
valid_sources[0x59]	439198	1			T2	432		T3	634		T5	22
valid_sources[0x5a]	723164	1			T2	378		T3	675		T5	15
valid_sources[0x5b]	434142	1			T2	382		T3	617		T4	59
valid_sources[0x5c]	442295	1			T2	379		T3	679		T5	21
valid_sources[0x5d]	456502	1			T2	344		T3	664		T5	11
valid_sources[0x5e]	470638	1			T2	467		T3	612		T5	22
valid_sources[0x5f]	476375	1			T2	418		T3	624		T5	18
valid_sources[0x60]	500512	1			T2	357		T3	627		T4	53
valid_sources[0x61]	443374	1			T2	378		T3	644		T5	12
valid_sources[0x62]	439931	1			T2	334		T3	641		T4	43
valid_sources[0x63]	432748	1			T2	394		T3	659		T5	7
valid_sources[0x64]	477964	1			T2	272		T3	643		T5	3
valid_sources[0x65]	445408	1			T2	332		T3	628		T5	20
valid_sources[0x66]	437826	1			T2	433		T3	650		T4	741
valid_sources[0x67]	450248	1			T2	455		T3	588		T5	14
valid_sources[0x68]	436507	1			T2	430		T3	624		T4	521
valid_sources[0x69]	456819	1			T2	361		T3	645		T5	7
valid_sources[0x6a]	437366	1			T2	399		T3	643		T5	7
valid_sources[0x6b]	441465	1			T2	301		T3	676		T5	17
valid_sources[0x6c]	502963	1			T2	415		T3	652		T5	16
valid_sources[0x6d]	441562	1			T2	349		T3	671		T5	24
valid_sources[0x6e]	460542	1			T2	467		T3	640		T4	4
valid_sources[0x6f]	449566	1			T2	331		T3	631		T5	21
valid_sources[0x70]	468210	1			T2	251		T3	668		T4	253
valid_sources[0x71]	435673	1			T2	401		T3	645		T4	1024
valid_sources[0x72]	468267	1			T2	453		T3	683		T4	418
valid_sources[0x73]	456936	1			T2	366		T3	644		T5	11
valid_sources[0x74]	442780	1			T2	430		T3	652		T5	31
valid_sources[0x75]	482863	1			T2	435		T3	595		T5	15
valid_sources[0x76]	432506	1			T2	318		T3	644		T4	24
valid_sources[0x77]	475884	1			T2	403		T3	715		T4	1079
valid_sources[0x78]	520819	1			T2	351		T3	604		T4	39
valid_sources[0x79]	463729	1			T2	396		T3	690		T4	79
valid_sources[0x7a]	439246	1			T2	331		T3	673		T5	6
valid_sources[0x7b]	432228	1			T2	281		T3	647		T5	9
valid_sources[0x7c]	469436	1			T2	283		T3	629		T4	335
valid_sources[0x7d]	442763	1			T2	381		T3	670		T5	6
valid_sources[0x7e]	520969	1			T2	456		T3	604		T4	794
valid_sources[0x7f]	470743	1			T2	244		T3	625		T5	12
valid_sources[0x80]	486653	1			T2	337		T3	657		T4	202

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59910092

1

T2

32768

T3

75521

T4

137

values[0x0]

all_enables

biggest_size

31374218

1

T2

32789

T3

37868

T4

772

values[0x1]

all_enables

biggest_size

31366945

1

T2

32746

T3

37499

T4

734

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39820745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140919

1

T1

7

T3

13

T10

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39842895	1			T3	282694		T4	4729		T6	32787
values[0x0]	57577	1			T1	14		T3	18		T6	1
values[0x1]	61192	1			T1	9		T3	16		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26554823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13406841

1

T1

8

T3

94343

T4

1574

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	118556	1			T3	1087		T6	149		T5	21
valid_sources[0x01]	118463	1			T3	1122		T6	131		T5	38
valid_sources[0x02]	161543	1			T1	2		T3	1052		T6	109
valid_sources[0x03]	234154	1			T3	1114		T6	131		T5	26
valid_sources[0x04]	117860	1			T3	1155		T6	141		T5	25
valid_sources[0x05]	141469	1			T3	1121		T6	114		T5	19
valid_sources[0x06]	258878	1			T3	1104		T6	118		T5	28
valid_sources[0x07]	124849	1			T3	1077		T6	127		T10	1
valid_sources[0x08]	157333	1			T3	1058		T6	158		T5	26
valid_sources[0x09]	117522	1			T3	1021		T6	119		T5	28
valid_sources[0x0a]	151557	1			T3	1157		T6	136		T5	42
valid_sources[0x0b]	150483	1			T3	1052		T6	152		T5	32
valid_sources[0x0c]	117475	1			T3	1077		T6	138		T5	23
valid_sources[0x0d]	116529	1			T3	1203		T6	117		T5	23
valid_sources[0x0e]	120721	1			T3	1113		T6	132		T5	28
valid_sources[0x0f]	118564	1			T3	1143		T6	131		T5	34
valid_sources[0x10]	149761	1			T3	1169		T6	140		T5	29
valid_sources[0x11]	118412	1			T3	1180		T6	122		T5	27
valid_sources[0x12]	116806	1			T3	1068		T6	128		T5	33
valid_sources[0x13]	137396	1			T3	1094		T6	133		T5	26
valid_sources[0x14]	118968	1			T3	1094		T6	88		T5	31
valid_sources[0x15]	352839	1			T3	1104		T6	122		T5	33
valid_sources[0x16]	120786	1			T1	1		T3	1096		T6	123
valid_sources[0x17]	174577	1			T3	1011		T6	149		T5	25
valid_sources[0x18]	124089	1			T3	1113		T6	138		T5	32
valid_sources[0x19]	185464	1			T1	4		T3	1129		T6	132
valid_sources[0x1a]	116990	1			T3	1197		T6	122		T5	19
valid_sources[0x1b]	116803	1			T3	1105		T6	128		T5	31
valid_sources[0x1c]	118077	1			T3	1077		T6	132		T5	24
valid_sources[0x1d]	119171	1			T3	1190		T6	117		T5	30
valid_sources[0x1e]	149902	1			T3	1114		T6	150		T5	30
valid_sources[0x1f]	122080	1			T3	1124		T6	103		T5	24
valid_sources[0x20]	151738	1			T3	1059		T6	115		T5	27
valid_sources[0x21]	118376	1			T3	1144		T6	144		T5	24
valid_sources[0x22]	122880	1			T3	1206		T6	116		T5	31
valid_sources[0x23]	155187	1			T3	1074		T6	122		T5	29
valid_sources[0x24]	120510	1			T3	1186		T6	118		T5	26
valid_sources[0x25]	117941	1			T3	1142		T6	114		T5	35
valid_sources[0x26]	119002	1			T3	1017		T6	99		T5	37
valid_sources[0x27]	218046	1			T3	1173		T6	101		T5	27
valid_sources[0x28]	120525	1			T3	1066		T6	134		T5	31
valid_sources[0x29]	153762	1			T3	1124		T6	151		T5	34
valid_sources[0x2a]	414517	1			T3	1098		T6	167		T5	25
valid_sources[0x2b]	121742	1			T3	1118		T6	128		T5	35
valid_sources[0x2c]	150916	1			T3	1266		T6	124		T5	22
valid_sources[0x2d]	120096	1			T3	1075		T6	117		T5	21
valid_sources[0x2e]	117654	1			T3	1085		T6	159		T5	24
valid_sources[0x2f]	369641	1			T3	1163		T6	144		T5	27
valid_sources[0x30]	116666	1			T3	1072		T6	136		T5	28
valid_sources[0x31]	119687	1			T3	1171		T6	132		T5	23
valid_sources[0x32]	117830	1			T3	1097		T6	146		T5	29
valid_sources[0x33]	117639	1			T3	1077		T6	103		T5	32
valid_sources[0x34]	117914	1			T3	1039		T6	153		T5	34
valid_sources[0x35]	122240	1			T3	1066		T6	142		T5	27
valid_sources[0x36]	117539	1			T3	1094		T6	162		T5	29
valid_sources[0x37]	132645	1			T3	1118		T6	116		T5	33
valid_sources[0x38]	185806	1			T3	1030		T6	130		T5	26
valid_sources[0x39]	122165	1			T3	1131		T6	105		T5	30
valid_sources[0x3a]	118180	1			T3	1040		T6	135		T5	18
valid_sources[0x3b]	134603	1			T3	1164		T6	111		T5	27
valid_sources[0x3c]	365265	1			T3	1155		T6	156		T5	28
valid_sources[0x3d]	265178	1			T3	1063		T6	135		T5	29
valid_sources[0x3e]	119080	1			T3	1180		T6	131		T5	24
valid_sources[0x3f]	117512	1			T3	1129		T6	130		T5	28
valid_sources[0x40]	413386	1			T3	1103		T6	132		T5	24
valid_sources[0x41]	117431	1			T3	1067		T6	147		T5	27
valid_sources[0x42]	116711	1			T3	1154		T6	118		T5	26
valid_sources[0x43]	155296	1			T3	1160		T6	120		T5	34
valid_sources[0x44]	124337	1			T3	1161		T6	185		T10	1
valid_sources[0x45]	199154	1			T3	1159		T6	150		T5	24
valid_sources[0x46]	118582	1			T3	1181		T6	139		T5	26
valid_sources[0x47]	129704	1			T3	1174		T6	116		T5	25
valid_sources[0x48]	117439	1			T3	1216		T6	166		T5	28
valid_sources[0x49]	218961	1			T3	992		T6	144		T5	37
valid_sources[0x4a]	133552	1			T3	1150		T6	135		T5	28
valid_sources[0x4b]	121085	1			T3	1081		T6	83		T5	23
valid_sources[0x4c]	122821	1			T3	1137		T6	123		T5	31
valid_sources[0x4d]	123360	1			T3	1018		T6	127		T5	30
valid_sources[0x4e]	182612	1			T3	1125		T6	108		T5	31
valid_sources[0x4f]	116928	1			T3	1115		T6	158		T5	34
valid_sources[0x50]	200656	1			T3	1116		T6	126		T5	31
valid_sources[0x51]	118644	1			T3	1075		T6	155		T5	22
valid_sources[0x52]	118365	1			T3	1107		T6	106		T5	26
valid_sources[0x53]	120019	1			T3	1130		T6	136		T5	28
valid_sources[0x54]	117439	1			T3	1016		T6	115		T5	28
valid_sources[0x55]	118802	1			T3	1053		T6	160		T5	32
valid_sources[0x56]	529954	1			T3	1079		T6	110		T5	17
valid_sources[0x57]	119112	1			T3	1139		T6	109		T5	26
valid_sources[0x58]	117929	1			T3	1235		T6	132		T5	22
valid_sources[0x59]	118650	1			T3	1128		T6	100		T5	29
valid_sources[0x5a]	167064	1			T3	1031		T6	129		T5	28
valid_sources[0x5b]	118501	1			T3	987		T6	111		T5	31
valid_sources[0x5c]	132652	1			T3	1083		T6	126		T5	27
valid_sources[0x5d]	118647	1			T3	1084		T6	114		T5	38
valid_sources[0x5e]	331279	1			T3	1120		T6	135		T5	19
valid_sources[0x5f]	199999	1			T1	1		T3	1034		T6	127
valid_sources[0x60]	150484	1			T3	1042		T6	104		T5	30
valid_sources[0x61]	384854	1			T3	1141		T6	134		T5	28
valid_sources[0x62]	118732	1			T3	1068		T6	125		T5	29
valid_sources[0x63]	334785	1			T3	1142		T6	100		T5	28
valid_sources[0x64]	116372	1			T3	1038		T6	143		T5	19
valid_sources[0x65]	118906	1			T3	1154		T6	108		T5	26
valid_sources[0x66]	136224	1			T3	1134		T6	151		T5	23
valid_sources[0x67]	118954	1			T3	1053		T6	117		T5	26
valid_sources[0x68]	119673	1			T3	1170		T6	132		T5	34
valid_sources[0x69]	117186	1			T3	1094		T6	123		T5	35
valid_sources[0x6a]	118949	1			T3	1067		T6	115		T5	26
valid_sources[0x6b]	188683	1			T3	1022		T6	110		T5	19
valid_sources[0x6c]	119438	1			T3	1183		T6	152		T5	26
valid_sources[0x6d]	118900	1			T1	1		T3	1126		T6	160
valid_sources[0x6e]	115756	1			T3	1022		T6	86		T5	25
valid_sources[0x6f]	135314	1			T3	1117		T6	111		T5	34
valid_sources[0x70]	266492	1			T3	1078		T6	94		T5	22
valid_sources[0x71]	219425	1			T3	1161		T6	138		T5	30
valid_sources[0x72]	316756	1			T3	1064		T6	100		T5	29
valid_sources[0x73]	122197	1			T3	1198		T6	102		T5	28
valid_sources[0x74]	119024	1			T3	1142		T6	141		T5	32
valid_sources[0x75]	183991	1			T3	1184		T6	135		T5	31
valid_sources[0x76]	151340	1			T3	1134		T6	119		T5	36
valid_sources[0x77]	118149	1			T3	1071		T6	126		T5	14
valid_sources[0x78]	118767	1			T3	1214		T6	134		T5	25
valid_sources[0x79]	118846	1			T3	1153		T6	133		T5	23
valid_sources[0x7a]	119379	1			T3	1055		T6	127		T5	34
valid_sources[0x7b]	119080	1			T3	1075		T6	135		T5	27
valid_sources[0x7c]	115739	1			T3	1157		T6	96		T5	24
valid_sources[0x7d]	117581	1			T3	1029		T6	155		T5	24
valid_sources[0x7e]	119284	1			T3	1003		T6	161		T5	34
valid_sources[0x7f]	134138	1			T3	1006		T6	114		T5	30
valid_sources[0x80]	119609	1			T3	1059		T6	126		T5	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38682

1

T11

9

T13

1

T14

1263

values[0x0]

all_enables

biggest_size

51805

1

T1

5

T3

9

T10

1

values[0x1]

all_enables

biggest_size

50432

1

T1

2

T3

4

T10

1