Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14774113

1

T3

15036

T4

30924

T5

388

full_word

120806218

1

T2

98303

T3

150888

T4

1643

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	135580011	1			T2	98303		T3	165924		T4	32567
auto[TlIntgErrCmd]	115	1			T47	2		T48	4		T49	5
auto[TlIntgErrData]	100	1			T47	5		T48	2		T49	3
auto[TlIntgErrBoth]	105	1			T47	3		T48	4		T49	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65401655

1

T2

32768

T3

83110

T4

16207

auto[1]

70178676

1

T2

65535

T3

82814

T4

16360

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7282146	1			T3	7589		T4	16070		T5	172
auto[TlIntgErrNone]	partial	auto[1]	7491669	1			T3	7447		T4	14854		T5	216
auto[TlIntgErrNone]	full_word	auto[0]	58119370	1			T2	32768		T3	75521		T4	137
auto[TlIntgErrNone]	full_word	auto[1]	62686826	1			T2	65535		T3	75367		T4	1506
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T49	3		T95	1		T96	8
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T47	1		T48	3		T49	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T47	1		T48	1		T100	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T104	1		T97	1		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1			T47	1		T48	1		T95	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T47	3		T48	1		T49	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T96	1		T106	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T47	1		T96	1		T103	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T47	1		T48	1		T95	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T47	1		T48	3		T49	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T104	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T47	1		T95	1		T104	1