Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	786905	1			T14	2		T15	14700		T16	22118
auto[1]	10101685	1			T3	33986		T4	1919		T6	3252
auto[2]	637184	1			T15	13072		T16	18944		T7	3
auto[3]	9958035	1			T3	34174		T4	1993		T6	3268

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13045194	1			T3	56596		T4	9		T6	6520
auto[1]	1990597	1			T3	5472		T4	87		T5	1
auto[2]	2030129	1			T3	5545		T4	259		T5	2
auto[3]	4417889	1			T3	547		T4	3557		T11	15

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8325170

1

T3

68153

T4

3912

T6

6520

auto[1]

13158639

1

T3

7

T12

243346

T20

86911

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	274572	1			T14	1		T7	3		T29	1955
auto[0]	auto[0]	auto[1]	28652	1			T7	1		T29	183		T75	14
auto[0]	auto[0]	auto[2]	28468	1			T14	1		T7	1		T29	194
auto[0]	auto[0]	auto[3]	68408	1			T29	17		T75	2203		T84	8540
auto[0]	auto[1]	auto[0]	2645376	1			T3	28193		T6	3252		T5	1
auto[0]	auto[1]	auto[1]	291143	1			T3	2724		T4	12		T5	1
auto[0]	auto[1]	auto[2]	315620	1			T3	2806		T4	64		T11	34
auto[0]	auto[1]	auto[3]	595366	1			T3	261		T4	1843		T11	9
auto[0]	auto[2]	auto[0]	217051	1			T7	2		T29	693		T75	1
auto[0]	auto[2]	auto[1]	27048	1			T7	1		T29	71		T75	107
auto[0]	auto[2]	auto[2]	20888	1			T29	121		T75	12		T8	1
auto[0]	auto[2]	auto[3]	49340	1			T29	7		T75	1965		T84	5908
auto[0]	auto[3]	auto[0]	2588535	1			T3	28397		T4	9		T6	3268
auto[0]	auto[3]	auto[1]	305000	1			T3	2747		T4	75		T11	22
auto[0]	auto[3]	auto[2]	324619	1			T3	2739		T4	195		T5	2
auto[0]	auto[3]	auto[3]	545084	1			T3	286		T4	1714		T11	6
auto[1]	auto[0]	auto[0]	12688	1			T15	498		T16	757		T67	721
auto[1]	auto[0]	auto[1]	57515	1			T15	2183		T16	3315		T67	3347
auto[1]	auto[0]	auto[2]	57694	1			T15	2098		T16	3276		T67	3377
auto[1]	auto[0]	auto[3]	258908	1			T15	9921		T16	14770		T67	15201
auto[1]	auto[1]	auto[0]	3649031	1			T3	2		T12	101758		T20	1410
auto[1]	auto[1]	auto[1]	634516	1			T12	8996		T20	6448		T21	15477
auto[1]	auto[1]	auto[2]	608142	1			T12	10031		T20	6378		T21	17104
auto[1]	auto[1]	auto[3]	1362491	1			T12	922		T20	29386		T21	69440
auto[1]	auto[2]	auto[0]	10880	1			T15	288		T16	693		T67	748
auto[1]	auto[2]	auto[1]	48637	1			T15	1354		T16	2937		T67	3100
auto[1]	auto[2]	auto[2]	48028	1			T15	2104		T16	2818		T67	2235
auto[1]	auto[2]	auto[3]	215312	1			T15	9326		T16	12496		T67	10182
auto[1]	auto[3]	auto[0]	3647061	1			T3	4		T12	101546		T20	1409
auto[1]	auto[3]	auto[1]	598086	1			T3	1		T12	10128		T20	6430
auto[1]	auto[3]	auto[2]	626670	1			T12	9080		T20	6399		T21	15628
auto[1]	auto[3]	auto[3]	1322980	1			T12	885		T20	29051		T21	69617