Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	940690071	120454	0	0
ctrl_regwen_rd_A	940690071	7043	0	0
exec_rd_A	940690071	6545	0	0
exec_regwen_rd_A	940690071	7100	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940690071	120454	0	0
T14	293845	5269	0	0
T15	191524	0	0	0
T16	142671	0	0	0
T17	361952	0	0	0
T21	634505	0	0	0
T23	495486	0	0	0
T31	959	0	0	0
T34	47396	2022	0	0
T35	0	1377	0	0
T50	0	4337	0	0
T51	0	461	0	0
T52	0	1	0	0
T53	0	17	0	0
T54	0	39	0	0
T55	0	337	0	0
T56	0	215	0	0
T59	69015	0	0	0
T60	73922	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940690071	7043	0	0
T14	293845	1093	0	0
T15	191524	0	0	0
T17	361952	0	0	0
T21	634505	0	0	0
T23	495486	0	0	0
T31	959	0	0	0
T49	0	32	0	0
T51	13442	79	0	0
T53	34969	20	0	0
T61	998	11	0	0
T64	1431	13	0	0
T69	0	9	0	0
T70	0	28	0	0
T72	0	45	0	0
T93	0	60	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940690071	6545	0	0
T14	293845	868	0	0
T15	191524	0	0	0
T17	361952	0	0	0
T21	634505	0	0	0
T23	495486	0	0	0
T31	959	0	0	0
T49	0	33	0	0
T51	13442	15	0	0
T52	34365	6	0	0
T53	34969	25	0	0
T61	998	5	0	0
T64	0	7	0	0
T69	0	9	0	0
T70	0	61	0	0
T72	0	18	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940690071	7100	0	0
T14	293845	1143	0	0
T15	191524	0	0	0
T17	361952	0	0	0
T21	634505	0	0	0
T23	495486	0	0	0
T31	959	0	0	0
T49	0	23	0	0
T51	13442	59	0	0
T52	34365	8	0	0
T53	34969	29	0	0
T61	998	12	0	0
T64	0	6	0	0
T70	0	68	0	0
T72	0	29	0	0
T93	0	78	0	0