| T266 |
/workspace/coverage/default/49.sram_ctrl_bijection.1719797438 |
|
|
Feb 04 01:52:47 PM PST 24 |
Feb 04 02:26:44 PM PST 24 |
31766344630 ps |
| T267 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1037742988 |
|
|
Feb 04 01:43:50 PM PST 24 |
Feb 04 02:18:26 PM PST 24 |
2075784744 ps |
| T268 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2025840415 |
|
|
Feb 04 01:42:20 PM PST 24 |
Feb 04 02:10:51 PM PST 24 |
9519246892 ps |
| T269 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2339191429 |
|
|
Feb 04 01:47:24 PM PST 24 |
Feb 04 01:55:17 PM PST 24 |
73726278084 ps |
| T116 |
/workspace/coverage/default/16.sram_ctrl_regwen.1342064813 |
|
|
Feb 04 01:42:20 PM PST 24 |
Feb 04 01:58:58 PM PST 24 |
20792680674 ps |
| T270 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3961005824 |
|
|
Feb 04 01:52:02 PM PST 24 |
Feb 04 01:54:02 PM PST 24 |
1978487470 ps |
| T271 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1093412338 |
|
|
Feb 04 01:40:42 PM PST 24 |
Feb 04 01:52:24 PM PST 24 |
71489386798 ps |
| T272 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.3067590320 |
|
|
Feb 04 01:44:37 PM PST 24 |
Feb 04 01:48:33 PM PST 24 |
4024427693 ps |
| T273 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.4026036291 |
|
|
Feb 04 01:45:17 PM PST 24 |
Feb 04 01:45:32 PM PST 24 |
691977795 ps |
| T274 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2518723519 |
|
|
Feb 04 01:38:51 PM PST 24 |
Feb 04 01:42:12 PM PST 24 |
6286383617 ps |
| T275 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3117336227 |
|
|
Feb 04 01:52:20 PM PST 24 |
Feb 04 02:00:09 PM PST 24 |
10271593115 ps |
| T114 |
/workspace/coverage/default/49.sram_ctrl_stress_all.4150246850 |
|
|
Feb 04 01:53:09 PM PST 24 |
Feb 04 02:38:21 PM PST 24 |
65286346716 ps |
| T276 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.51966966 |
|
|
Feb 04 01:42:45 PM PST 24 |
Feb 04 01:42:54 PM PST 24 |
2406333613 ps |
| T277 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2062982504 |
|
|
Feb 04 01:50:10 PM PST 24 |
Feb 04 01:50:38 PM PST 24 |
1286725038 ps |
| T278 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2273169958 |
|
|
Feb 04 01:41:36 PM PST 24 |
Feb 04 01:41:42 PM PST 24 |
368582817 ps |
| T279 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.375366738 |
|
|
Feb 04 01:40:30 PM PST 24 |
Feb 04 03:04:31 PM PST 24 |
1705026661 ps |
| T280 |
/workspace/coverage/default/31.sram_ctrl_bijection.885573611 |
|
|
Feb 04 01:46:43 PM PST 24 |
Feb 04 02:06:32 PM PST 24 |
329283590359 ps |
| T281 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3996276156 |
|
|
Feb 04 01:44:49 PM PST 24 |
Feb 04 01:47:17 PM PST 24 |
39001063613 ps |
| T282 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.3677502980 |
|
|
Feb 04 01:48:45 PM PST 24 |
Feb 04 02:13:50 PM PST 24 |
15397615163 ps |
| T283 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3154895159 |
|
|
Feb 04 01:50:42 PM PST 24 |
Feb 04 02:11:30 PM PST 24 |
40284167266 ps |
| T284 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3696241638 |
|
|
Feb 04 01:41:10 PM PST 24 |
Feb 04 01:41:45 PM PST 24 |
6417718338 ps |
| T285 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.95702489 |
|
|
Feb 04 01:48:12 PM PST 24 |
Feb 04 01:52:25 PM PST 24 |
4109768677 ps |
| T286 |
/workspace/coverage/default/35.sram_ctrl_smoke.591602697 |
|
|
Feb 04 01:47:55 PM PST 24 |
Feb 04 01:48:23 PM PST 24 |
1666003820 ps |
| T287 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.1781035500 |
|
|
Feb 04 01:49:55 PM PST 24 |
Feb 04 02:01:06 PM PST 24 |
17663535909 ps |
| T288 |
/workspace/coverage/default/36.sram_ctrl_executable.3692879975 |
|
|
Feb 04 01:48:44 PM PST 24 |
Feb 04 01:56:48 PM PST 24 |
6655436996 ps |
| T289 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2276481150 |
|
|
Feb 04 01:48:46 PM PST 24 |
Feb 04 01:49:18 PM PST 24 |
2823599165 ps |
| T290 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3692651732 |
|
|
Feb 04 01:42:44 PM PST 24 |
Feb 04 01:48:39 PM PST 24 |
4446461986 ps |
| T291 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2651183819 |
|
|
Feb 04 01:42:37 PM PST 24 |
Feb 04 01:43:50 PM PST 24 |
2032051621 ps |
| T292 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3803555899 |
|
|
Feb 04 01:43:24 PM PST 24 |
Feb 04 01:43:39 PM PST 24 |
1257897301 ps |
| T293 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1740875548 |
|
|
Feb 04 01:48:54 PM PST 24 |
Feb 04 01:55:31 PM PST 24 |
29394392235 ps |
| T294 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1773527033 |
|
|
Feb 04 01:41:36 PM PST 24 |
Feb 04 01:48:55 PM PST 24 |
71014439980 ps |
| T295 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1060233310 |
|
|
Feb 04 01:46:15 PM PST 24 |
Feb 04 01:53:38 PM PST 24 |
6743003023 ps |
| T296 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1021250550 |
|
|
Feb 04 01:50:23 PM PST 24 |
Feb 04 02:10:34 PM PST 24 |
32348013446 ps |
| T297 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3078428594 |
|
|
Feb 04 01:38:14 PM PST 24 |
Feb 04 01:39:42 PM PST 24 |
1648180906 ps |
| T112 |
/workspace/coverage/default/49.sram_ctrl_regwen.2356306727 |
|
|
Feb 04 01:52:59 PM PST 24 |
Feb 04 02:01:57 PM PST 24 |
7333655599 ps |
| T27 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1605575274 |
|
|
Feb 04 01:37:31 PM PST 24 |
Feb 04 01:37:34 PM PST 24 |
342045733 ps |
| T40 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.111439215 |
|
|
Feb 04 01:46:36 PM PST 24 |
Feb 04 01:52:33 PM PST 24 |
61812507134 ps |
| T298 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1494927744 |
|
|
Feb 04 01:46:35 PM PST 24 |
Feb 04 01:47:58 PM PST 24 |
487594396 ps |
| T299 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3326505400 |
|
|
Feb 04 01:52:02 PM PST 24 |
Feb 04 01:52:18 PM PST 24 |
1398817063 ps |
| T300 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.977765433 |
|
|
Feb 04 01:47:23 PM PST 24 |
Feb 04 01:47:38 PM PST 24 |
354516018 ps |
| T301 |
/workspace/coverage/default/27.sram_ctrl_alert_test.467181168 |
|
|
Feb 04 01:45:46 PM PST 24 |
Feb 04 01:45:48 PM PST 24 |
19100903 ps |
| T302 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2617298419 |
|
|
Feb 04 01:36:58 PM PST 24 |
Feb 04 01:37:24 PM PST 24 |
4591756494 ps |
| T303 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.675177280 |
|
|
Feb 04 01:39:49 PM PST 24 |
Feb 04 01:40:52 PM PST 24 |
5134449805 ps |
| T304 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.938867131 |
|
|
Feb 04 01:37:39 PM PST 24 |
Feb 04 02:01:37 PM PST 24 |
34122750440 ps |
| T305 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.502825243 |
|
|
Feb 04 01:45:34 PM PST 24 |
Feb 04 01:49:38 PM PST 24 |
15759197882 ps |
| T306 |
/workspace/coverage/default/20.sram_ctrl_smoke.60173330 |
|
|
Feb 04 01:43:17 PM PST 24 |
Feb 04 01:43:40 PM PST 24 |
2570220281 ps |
| T307 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.409445362 |
|
|
Feb 04 01:52:00 PM PST 24 |
Feb 04 02:29:35 PM PST 24 |
11113907224 ps |
| T308 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3242457821 |
|
|
Feb 04 01:51:16 PM PST 24 |
Feb 04 02:10:11 PM PST 24 |
54222943200 ps |
| T309 |
/workspace/coverage/default/32.sram_ctrl_regwen.244406228 |
|
|
Feb 04 01:47:15 PM PST 24 |
Feb 04 02:06:15 PM PST 24 |
70704310182 ps |
| T310 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1710295045 |
|
|
Feb 04 01:47:46 PM PST 24 |
Feb 04 01:47:55 PM PST 24 |
855455551 ps |
| T311 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1323305840 |
|
|
Feb 04 01:46:58 PM PST 24 |
Feb 04 01:47:14 PM PST 24 |
1403789655 ps |
| T312 |
/workspace/coverage/default/5.sram_ctrl_smoke.427696548 |
|
|
Feb 04 01:37:54 PM PST 24 |
Feb 04 01:39:13 PM PST 24 |
3268084882 ps |
| T313 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3318140298 |
|
|
Feb 04 01:43:47 PM PST 24 |
Feb 04 01:43:55 PM PST 24 |
1410857537 ps |
| T314 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3948083205 |
|
|
Feb 04 01:39:12 PM PST 24 |
Feb 04 02:50:28 PM PST 24 |
394476510 ps |
| T315 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1386124201 |
|
|
Feb 04 01:48:50 PM PST 24 |
Feb 04 02:44:11 PM PST 24 |
4359642239 ps |
| T316 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3258033371 |
|
|
Feb 04 01:41:35 PM PST 24 |
Feb 04 01:41:37 PM PST 24 |
26738019 ps |
| T317 |
/workspace/coverage/default/38.sram_ctrl_bijection.525635738 |
|
|
Feb 04 01:49:04 PM PST 24 |
Feb 04 01:58:42 PM PST 24 |
46531172897 ps |
| T318 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1560237154 |
|
|
Feb 04 01:44:16 PM PST 24 |
Feb 04 01:50:55 PM PST 24 |
36638989384 ps |
| T319 |
/workspace/coverage/default/9.sram_ctrl_executable.779794020 |
|
|
Feb 04 01:40:48 PM PST 24 |
Feb 04 01:55:39 PM PST 24 |
12944012995 ps |
| T320 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2310684221 |
|
|
Feb 04 01:38:50 PM PST 24 |
Feb 04 02:03:54 PM PST 24 |
26909300110 ps |
| T115 |
/workspace/coverage/default/21.sram_ctrl_regwen.4225638867 |
|
|
Feb 04 01:43:46 PM PST 24 |
Feb 04 01:51:16 PM PST 24 |
8073947251 ps |
| T321 |
/workspace/coverage/default/45.sram_ctrl_alert_test.945546068 |
|
|
Feb 04 01:51:52 PM PST 24 |
Feb 04 01:51:54 PM PST 24 |
98055645 ps |
| T322 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.309226047 |
|
|
Feb 04 01:47:13 PM PST 24 |
Feb 04 03:25:43 PM PST 24 |
1361059790 ps |
| T323 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2624597105 |
|
|
Feb 04 01:52:49 PM PST 24 |
Feb 04 02:10:13 PM PST 24 |
16399025665 ps |
| T324 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3508271296 |
|
|
Feb 04 01:42:33 PM PST 24 |
Feb 04 02:08:56 PM PST 24 |
16104957738 ps |
| T325 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.1627476374 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:37:55 PM PST 24 |
2594827402 ps |
| T326 |
/workspace/coverage/default/4.sram_ctrl_alert_test.1679795480 |
|
|
Feb 04 01:37:56 PM PST 24 |
Feb 04 01:37:58 PM PST 24 |
33782408 ps |
| T327 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.920853440 |
|
|
Feb 04 01:48:31 PM PST 24 |
Feb 04 02:39:21 PM PST 24 |
192268543 ps |
| T328 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3293593292 |
|
|
Feb 04 01:39:55 PM PST 24 |
Feb 04 03:15:24 PM PST 24 |
2415822811 ps |
| T329 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2671296235 |
|
|
Feb 04 01:38:12 PM PST 24 |
Feb 04 01:39:56 PM PST 24 |
763233762 ps |
| T330 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.200158636 |
|
|
Feb 04 01:45:45 PM PST 24 |
Feb 04 01:57:15 PM PST 24 |
63211117055 ps |
| T331 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.721019324 |
|
|
Feb 04 01:41:59 PM PST 24 |
Feb 04 01:42:06 PM PST 24 |
1257130032 ps |
| T332 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3179036714 |
|
|
Feb 04 01:50:06 PM PST 24 |
Feb 04 01:50:15 PM PST 24 |
2076116796 ps |
| T333 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2043923139 |
|
|
Feb 04 01:52:11 PM PST 24 |
Feb 04 01:52:42 PM PST 24 |
6236228751 ps |
| T334 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3355139172 |
|
|
Feb 04 01:43:13 PM PST 24 |
Feb 04 03:15:47 PM PST 24 |
868339979 ps |
| T335 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.875031954 |
|
|
Feb 04 01:50:42 PM PST 24 |
Feb 04 02:08:13 PM PST 24 |
10864151964 ps |
| T336 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.4232939646 |
|
|
Feb 04 01:39:12 PM PST 24 |
Feb 04 01:43:22 PM PST 24 |
10434705050 ps |
| T337 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.640004570 |
|
|
Feb 04 01:37:42 PM PST 24 |
Feb 04 01:39:07 PM PST 24 |
10483775685 ps |
| T338 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3441318741 |
|
|
Feb 04 01:40:50 PM PST 24 |
Feb 04 01:45:01 PM PST 24 |
32819165870 ps |
| T339 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2696583622 |
|
|
Feb 04 01:37:41 PM PST 24 |
Feb 04 01:37:43 PM PST 24 |
35066380 ps |
| T340 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3287136485 |
|
|
Feb 04 01:43:14 PM PST 24 |
Feb 04 01:45:37 PM PST 24 |
1853579188 ps |
| T341 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3699990784 |
|
|
Feb 04 01:39:12 PM PST 24 |
Feb 04 01:42:13 PM PST 24 |
3177696364 ps |
| T342 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1638585334 |
|
|
Feb 04 01:51:18 PM PST 24 |
Feb 04 01:52:43 PM PST 24 |
3158321789 ps |
| T343 |
/workspace/coverage/default/44.sram_ctrl_smoke.1068994674 |
|
|
Feb 04 01:51:18 PM PST 24 |
Feb 04 01:52:09 PM PST 24 |
698076346 ps |
| T344 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1656091954 |
|
|
Feb 04 01:42:51 PM PST 24 |
Feb 04 01:47:37 PM PST 24 |
14311942511 ps |
| T345 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4131994308 |
|
|
Feb 04 01:39:26 PM PST 24 |
Feb 04 01:40:30 PM PST 24 |
1491177252 ps |
| T346 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.4070156516 |
|
|
Feb 04 01:41:08 PM PST 24 |
Feb 04 01:45:13 PM PST 24 |
2776754495 ps |
| T347 |
/workspace/coverage/default/1.sram_ctrl_smoke.3849676024 |
|
|
Feb 04 01:36:51 PM PST 24 |
Feb 04 01:38:17 PM PST 24 |
2232657679 ps |
| T348 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.859121990 |
|
|
Feb 04 01:41:30 PM PST 24 |
Feb 04 01:44:16 PM PST 24 |
19552800956 ps |
| T349 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3299272762 |
|
|
Feb 04 01:47:16 PM PST 24 |
Feb 04 01:49:43 PM PST 24 |
1604359069 ps |
| T350 |
/workspace/coverage/default/33.sram_ctrl_stress_all.3098034081 |
|
|
Feb 04 01:47:34 PM PST 24 |
Feb 04 03:46:28 PM PST 24 |
391468065573 ps |
| T351 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2876665349 |
|
|
Feb 04 01:36:51 PM PST 24 |
Feb 04 01:39:51 PM PST 24 |
13094486915 ps |
| T352 |
/workspace/coverage/default/39.sram_ctrl_alert_test.2425145308 |
|
|
Feb 04 01:49:43 PM PST 24 |
Feb 04 01:49:45 PM PST 24 |
16047194 ps |
| T353 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.168526193 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:46:22 PM PST 24 |
1543995936 ps |
| T354 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1460157238 |
|
|
Feb 04 01:52:22 PM PST 24 |
Feb 04 02:00:39 PM PST 24 |
19197381228 ps |
| T355 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3215246200 |
|
|
Feb 04 01:51:12 PM PST 24 |
Feb 04 02:29:20 PM PST 24 |
3868009056 ps |
| T356 |
/workspace/coverage/default/17.sram_ctrl_executable.3147626397 |
|
|
Feb 04 01:42:37 PM PST 24 |
Feb 04 01:48:11 PM PST 24 |
20340775405 ps |
| T357 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.1439033583 |
|
|
Feb 04 01:41:52 PM PST 24 |
Feb 04 01:44:36 PM PST 24 |
4952017427 ps |
| T358 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1301377412 |
|
|
Feb 04 01:47:58 PM PST 24 |
Feb 04 01:48:17 PM PST 24 |
353214505 ps |
| T359 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3771788084 |
|
|
Feb 04 01:49:57 PM PST 24 |
Feb 04 01:50:03 PM PST 24 |
701585770 ps |
| T360 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1431909151 |
|
|
Feb 04 01:46:14 PM PST 24 |
Feb 04 02:03:52 PM PST 24 |
60528384632 ps |
| T361 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1216534001 |
|
|
Feb 04 01:42:49 PM PST 24 |
Feb 04 02:08:02 PM PST 24 |
23743344475 ps |
| T362 |
/workspace/coverage/default/49.sram_ctrl_partial_access.581286785 |
|
|
Feb 04 01:52:49 PM PST 24 |
Feb 04 01:53:52 PM PST 24 |
460670892 ps |
| T363 |
/workspace/coverage/default/25.sram_ctrl_alert_test.103878107 |
|
|
Feb 04 01:45:12 PM PST 24 |
Feb 04 01:45:15 PM PST 24 |
12631657 ps |
| T364 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2410483063 |
|
|
Feb 04 01:49:17 PM PST 24 |
Feb 04 01:50:28 PM PST 24 |
7292753806 ps |
| T365 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.747731584 |
|
|
Feb 04 01:51:16 PM PST 24 |
Feb 04 01:51:32 PM PST 24 |
651504529 ps |
| T366 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2250458754 |
|
|
Feb 04 01:46:53 PM PST 24 |
Feb 04 01:46:55 PM PST 24 |
23561875 ps |
| T367 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.943843596 |
|
|
Feb 04 01:50:16 PM PST 24 |
Feb 04 01:50:35 PM PST 24 |
490124249 ps |
| T368 |
/workspace/coverage/default/47.sram_ctrl_regwen.3848510644 |
|
|
Feb 04 01:52:14 PM PST 24 |
Feb 04 02:01:34 PM PST 24 |
28600054682 ps |
| T369 |
/workspace/coverage/default/42.sram_ctrl_partial_access.1338305246 |
|
|
Feb 04 01:50:24 PM PST 24 |
Feb 04 01:50:40 PM PST 24 |
1066003880 ps |
| T370 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2893836669 |
|
|
Feb 04 01:47:25 PM PST 24 |
Feb 04 01:48:35 PM PST 24 |
1536645986 ps |
| T371 |
/workspace/coverage/default/38.sram_ctrl_partial_access.1483226827 |
|
|
Feb 04 01:49:17 PM PST 24 |
Feb 04 01:49:39 PM PST 24 |
1129668509 ps |
| T372 |
/workspace/coverage/default/6.sram_ctrl_executable.2930094081 |
|
|
Feb 04 01:38:46 PM PST 24 |
Feb 04 01:58:42 PM PST 24 |
44922372225 ps |
| T373 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.335945409 |
|
|
Feb 04 01:50:43 PM PST 24 |
Feb 04 01:51:15 PM PST 24 |
816566769 ps |
| T374 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3783179393 |
|
|
Feb 04 01:45:46 PM PST 24 |
Feb 04 01:46:01 PM PST 24 |
3052893546 ps |
| T375 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2853359426 |
|
|
Feb 04 01:51:13 PM PST 24 |
Feb 04 01:55:53 PM PST 24 |
19400645325 ps |
| T376 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1650731792 |
|
|
Feb 04 01:45:44 PM PST 24 |
Feb 04 01:51:16 PM PST 24 |
8103214402 ps |
| T377 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.4094321531 |
|
|
Feb 04 01:46:43 PM PST 24 |
Feb 04 01:51:09 PM PST 24 |
25374162636 ps |
| T378 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1762715622 |
|
|
Feb 04 01:42:57 PM PST 24 |
Feb 04 01:58:38 PM PST 24 |
12529600999 ps |
| T379 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1022343148 |
|
|
Feb 04 01:46:40 PM PST 24 |
Feb 04 01:51:33 PM PST 24 |
13149296425 ps |
| T380 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3859410138 |
|
|
Feb 04 01:44:03 PM PST 24 |
Feb 04 01:48:16 PM PST 24 |
4106621352 ps |
| T381 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2501254662 |
|
|
Feb 04 01:46:34 PM PST 24 |
Feb 04 01:47:37 PM PST 24 |
2943091274 ps |
| T382 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.1194908456 |
|
|
Feb 04 01:46:02 PM PST 24 |
Feb 04 01:47:32 PM PST 24 |
12725604722 ps |
| T383 |
/workspace/coverage/default/23.sram_ctrl_smoke.432468575 |
|
|
Feb 04 01:44:16 PM PST 24 |
Feb 04 01:45:44 PM PST 24 |
1474964608 ps |
| T384 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1419865517 |
|
|
Feb 04 01:49:46 PM PST 24 |
Feb 04 01:51:23 PM PST 24 |
2785327279 ps |
| T385 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1454104928 |
|
|
Feb 04 01:42:48 PM PST 24 |
Feb 04 01:43:59 PM PST 24 |
7188010806 ps |
| T386 |
/workspace/coverage/default/5.sram_ctrl_regwen.175577008 |
|
|
Feb 04 01:38:36 PM PST 24 |
Feb 04 01:51:09 PM PST 24 |
2920912908 ps |
| T387 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.193379389 |
|
|
Feb 04 01:41:17 PM PST 24 |
Feb 04 02:04:32 PM PST 24 |
17743086367 ps |
| T388 |
/workspace/coverage/default/22.sram_ctrl_executable.1843859776 |
|
|
Feb 04 01:44:04 PM PST 24 |
Feb 04 01:53:09 PM PST 24 |
5935717620 ps |
| T389 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3405743671 |
|
|
Feb 04 01:36:49 PM PST 24 |
Feb 04 03:15:26 PM PST 24 |
1088596504809 ps |
| T390 |
/workspace/coverage/default/24.sram_ctrl_regwen.2244237776 |
|
|
Feb 04 01:44:57 PM PST 24 |
Feb 04 01:57:20 PM PST 24 |
4664879539 ps |
| T391 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2689850069 |
|
|
Feb 04 01:42:24 PM PST 24 |
Feb 04 02:04:06 PM PST 24 |
71284157836 ps |
| T392 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.4262912026 |
|
|
Feb 04 01:49:39 PM PST 24 |
Feb 04 01:50:58 PM PST 24 |
33641709086 ps |
| T393 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1363422261 |
|
|
Feb 04 01:50:27 PM PST 24 |
Feb 04 01:53:27 PM PST 24 |
1665708289 ps |
| T394 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3789019651 |
|
|
Feb 04 01:40:51 PM PST 24 |
Feb 04 01:47:07 PM PST 24 |
73179843249 ps |
| T395 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.389601969 |
|
|
Feb 04 01:37:41 PM PST 24 |
Feb 04 01:41:16 PM PST 24 |
3335606910 ps |
| T396 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1525466579 |
|
|
Feb 04 01:40:50 PM PST 24 |
Feb 04 01:45:59 PM PST 24 |
8074297665 ps |
| T397 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3146681397 |
|
|
Feb 04 01:44:06 PM PST 24 |
Feb 04 01:45:00 PM PST 24 |
2843010553 ps |
| T398 |
/workspace/coverage/default/37.sram_ctrl_partial_access.924359609 |
|
|
Feb 04 01:49:04 PM PST 24 |
Feb 04 01:49:30 PM PST 24 |
10624310012 ps |
| T399 |
/workspace/coverage/default/17.sram_ctrl_bijection.156729779 |
|
|
Feb 04 01:42:37 PM PST 24 |
Feb 04 02:00:17 PM PST 24 |
34320540481 ps |
| T400 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.550235957 |
|
|
Feb 04 01:52:49 PM PST 24 |
Feb 04 01:59:36 PM PST 24 |
36810963998 ps |
| T401 |
/workspace/coverage/default/48.sram_ctrl_stress_all.581577037 |
|
|
Feb 04 01:52:52 PM PST 24 |
Feb 04 02:56:27 PM PST 24 |
62695726780 ps |
| T402 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1035185668 |
|
|
Feb 04 01:38:52 PM PST 24 |
Feb 04 01:39:01 PM PST 24 |
358647075 ps |
| T403 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.312467357 |
|
|
Feb 04 01:38:25 PM PST 24 |
Feb 04 04:08:44 PM PST 24 |
1459716037 ps |
| T404 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1165910069 |
|
|
Feb 04 01:48:47 PM PST 24 |
Feb 04 01:48:54 PM PST 24 |
1346224542 ps |
| T405 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1503163966 |
|
|
Feb 04 01:52:58 PM PST 24 |
Feb 04 01:54:14 PM PST 24 |
9407223013 ps |
| T406 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3017845977 |
|
|
Feb 04 01:41:32 PM PST 24 |
Feb 04 01:44:06 PM PST 24 |
38267851412 ps |
| T407 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.2272376069 |
|
|
Feb 04 01:46:14 PM PST 24 |
Feb 04 01:49:16 PM PST 24 |
28557242847 ps |
| T408 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.2628016518 |
|
|
Feb 04 01:50:43 PM PST 24 |
Feb 04 01:55:52 PM PST 24 |
43053290475 ps |
| T409 |
/workspace/coverage/default/36.sram_ctrl_smoke.9195714 |
|
|
Feb 04 01:48:29 PM PST 24 |
Feb 04 01:49:02 PM PST 24 |
399926265 ps |
| T410 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3916195504 |
|
|
Feb 04 01:42:42 PM PST 24 |
Feb 04 03:15:40 PM PST 24 |
75679501645 ps |
| T411 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2634701489 |
|
|
Feb 04 01:42:55 PM PST 24 |
Feb 04 01:43:27 PM PST 24 |
6491219742 ps |
| T412 |
/workspace/coverage/default/5.sram_ctrl_executable.4070886369 |
|
|
Feb 04 01:38:23 PM PST 24 |
Feb 04 01:56:59 PM PST 24 |
26323422097 ps |
| T413 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2294709892 |
|
|
Feb 04 01:44:25 PM PST 24 |
Feb 04 01:45:57 PM PST 24 |
6076760693 ps |
| T414 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3550539743 |
|
|
Feb 04 01:45:45 PM PST 24 |
Feb 04 02:00:19 PM PST 24 |
125970939252 ps |
| T415 |
/workspace/coverage/default/23.sram_ctrl_partial_access.3644117069 |
|
|
Feb 04 01:44:14 PM PST 24 |
Feb 04 01:44:51 PM PST 24 |
922854370 ps |
| T416 |
/workspace/coverage/default/42.sram_ctrl_alert_test.4989751 |
|
|
Feb 04 01:50:27 PM PST 24 |
Feb 04 01:50:30 PM PST 24 |
16927011 ps |
| T417 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1555124627 |
|
|
Feb 04 01:46:43 PM PST 24 |
Feb 04 01:46:45 PM PST 24 |
13979234 ps |
| T418 |
/workspace/coverage/default/3.sram_ctrl_smoke.373900556 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:38:07 PM PST 24 |
1090161521 ps |
| T419 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1625270397 |
|
|
Feb 04 01:45:16 PM PST 24 |
Feb 04 02:15:07 PM PST 24 |
9809909246 ps |
| T420 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.4028834467 |
|
|
Feb 04 01:41:36 PM PST 24 |
Feb 04 01:59:17 PM PST 24 |
75659164200 ps |
| T421 |
/workspace/coverage/default/34.sram_ctrl_regwen.3712759159 |
|
|
Feb 04 01:47:58 PM PST 24 |
Feb 04 02:03:40 PM PST 24 |
57241768398 ps |
| T422 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1924948666 |
|
|
Feb 04 01:52:27 PM PST 24 |
Feb 04 01:52:33 PM PST 24 |
38002744 ps |
| T423 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.4275462313 |
|
|
Feb 04 01:42:21 PM PST 24 |
Feb 04 01:45:16 PM PST 24 |
7944719656 ps |
| T424 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2810054238 |
|
|
Feb 04 01:40:43 PM PST 24 |
Feb 04 01:43:04 PM PST 24 |
8943057900 ps |
| T425 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.3468557173 |
|
|
Feb 04 01:38:34 PM PST 24 |
Feb 04 01:43:07 PM PST 24 |
28699731507 ps |
| T426 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1462872064 |
|
|
Feb 04 01:51:35 PM PST 24 |
Feb 04 02:39:58 PM PST 24 |
1076849383 ps |
| T427 |
/workspace/coverage/default/15.sram_ctrl_partial_access.472421528 |
|
|
Feb 04 01:42:14 PM PST 24 |
Feb 04 01:43:27 PM PST 24 |
3335110746 ps |
| T428 |
/workspace/coverage/default/22.sram_ctrl_bijection.1053027054 |
|
|
Feb 04 01:43:50 PM PST 24 |
Feb 04 02:17:09 PM PST 24 |
324157671602 ps |
| T429 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.940996566 |
|
|
Feb 04 01:52:02 PM PST 24 |
Feb 04 01:53:29 PM PST 24 |
26077329772 ps |
| T430 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3268347248 |
|
|
Feb 04 01:42:15 PM PST 24 |
Feb 04 01:43:00 PM PST 24 |
1557908991 ps |
| T431 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2208442884 |
|
|
Feb 04 01:42:14 PM PST 24 |
Feb 04 01:42:45 PM PST 24 |
2631670040 ps |
| T432 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.379027187 |
|
|
Feb 04 01:50:42 PM PST 24 |
Feb 04 01:50:49 PM PST 24 |
357332399 ps |
| T433 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1735102189 |
|
|
Feb 04 01:41:32 PM PST 24 |
Feb 04 01:42:05 PM PST 24 |
688490261 ps |
| T434 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1673598537 |
|
|
Feb 04 01:52:12 PM PST 24 |
Feb 04 01:56:31 PM PST 24 |
18742210644 ps |
| T435 |
/workspace/coverage/default/3.sram_ctrl_stress_all.584529333 |
|
|
Feb 04 01:37:42 PM PST 24 |
Feb 04 02:16:44 PM PST 24 |
189198280246 ps |
| T436 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.1670832766 |
|
|
Feb 04 01:43:47 PM PST 24 |
Feb 04 01:45:13 PM PST 24 |
1475321528 ps |
| T437 |
/workspace/coverage/default/48.sram_ctrl_bijection.232470954 |
|
|
Feb 04 01:52:22 PM PST 24 |
Feb 04 02:09:48 PM PST 24 |
67078475733 ps |
| T438 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2979604956 |
|
|
Feb 04 01:42:06 PM PST 24 |
Feb 04 01:42:18 PM PST 24 |
1299473180 ps |
| T439 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1794149468 |
|
|
Feb 04 01:37:41 PM PST 24 |
Feb 04 01:38:13 PM PST 24 |
4229490159 ps |
| T440 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2333575810 |
|
|
Feb 04 01:45:45 PM PST 24 |
Feb 04 01:50:44 PM PST 24 |
81332899037 ps |
| T441 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3686169674 |
|
|
Feb 04 01:51:53 PM PST 24 |
Feb 04 01:52:19 PM PST 24 |
5684398587 ps |
| T442 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1737605527 |
|
|
Feb 04 01:46:36 PM PST 24 |
Feb 04 01:51:55 PM PST 24 |
20646637871 ps |
| T443 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2529798435 |
|
|
Feb 04 01:46:03 PM PST 24 |
Feb 04 01:47:03 PM PST 24 |
6476788674 ps |
| T444 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.934754080 |
|
|
Feb 04 01:52:01 PM PST 24 |
Feb 04 02:07:19 PM PST 24 |
37834631832 ps |
| T445 |
/workspace/coverage/default/26.sram_ctrl_regwen.3276425532 |
|
|
Feb 04 01:45:34 PM PST 24 |
Feb 04 01:55:02 PM PST 24 |
15488141235 ps |
| T446 |
/workspace/coverage/default/18.sram_ctrl_bijection.700967076 |
|
|
Feb 04 01:42:48 PM PST 24 |
Feb 04 02:17:22 PM PST 24 |
96034202634 ps |
| T447 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2329692664 |
|
|
Feb 04 01:46:44 PM PST 24 |
Feb 04 02:14:55 PM PST 24 |
108770973647 ps |
| T448 |
/workspace/coverage/default/13.sram_ctrl_partial_access.4215245060 |
|
|
Feb 04 01:41:35 PM PST 24 |
Feb 04 01:41:49 PM PST 24 |
3071754000 ps |
| T449 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.17973328 |
|
|
Feb 04 01:38:53 PM PST 24 |
Feb 04 02:04:28 PM PST 24 |
139895148417 ps |
| T450 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2582910363 |
|
|
Feb 04 01:46:43 PM PST 24 |
Feb 04 01:52:41 PM PST 24 |
5580306604 ps |
| T451 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2859317716 |
|
|
Feb 04 01:52:01 PM PST 24 |
Feb 04 01:52:03 PM PST 24 |
13404043 ps |
| T452 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2164709083 |
|
|
Feb 04 01:47:12 PM PST 24 |
Feb 04 01:52:32 PM PST 24 |
85097632225 ps |
| T453 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3103585498 |
|
|
Feb 04 01:41:18 PM PST 24 |
Feb 04 01:48:13 PM PST 24 |
29413504732 ps |
| T454 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3591861489 |
|
|
Feb 04 01:50:29 PM PST 24 |
Feb 04 01:50:42 PM PST 24 |
1346892675 ps |
| T455 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2152429956 |
|
|
Feb 04 01:52:19 PM PST 24 |
Feb 04 01:53:50 PM PST 24 |
1533723246 ps |
| T456 |
/workspace/coverage/default/0.sram_ctrl_regwen.4226190436 |
|
|
Feb 04 01:36:50 PM PST 24 |
Feb 04 02:05:42 PM PST 24 |
7767881463 ps |
| T457 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.881839800 |
|
|
Feb 04 01:46:40 PM PST 24 |
Feb 04 01:58:01 PM PST 24 |
10372257938 ps |
| T458 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.776962364 |
|
|
Feb 04 01:46:13 PM PST 24 |
Feb 04 01:47:01 PM PST 24 |
738700792 ps |
| T459 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1477139284 |
|
|
Feb 04 01:45:46 PM PST 24 |
Feb 04 02:27:04 PM PST 24 |
859438540 ps |
| T460 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2379824050 |
|
|
Feb 04 01:51:34 PM PST 24 |
Feb 04 02:03:51 PM PST 24 |
7757851905 ps |
| T461 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3490851977 |
|
|
Feb 04 01:43:03 PM PST 24 |
Feb 04 03:05:23 PM PST 24 |
474537887825 ps |
| T462 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2851761882 |
|
|
Feb 04 01:42:36 PM PST 24 |
Feb 04 01:42:37 PM PST 24 |
28811714 ps |
| T463 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3637710742 |
|
|
Feb 04 01:37:58 PM PST 24 |
Feb 04 01:38:06 PM PST 24 |
706274815 ps |
| T464 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2453072436 |
|
|
Feb 04 01:37:42 PM PST 24 |
Feb 04 01:42:57 PM PST 24 |
86068763888 ps |
| T465 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3769159961 |
|
|
Feb 04 01:41:18 PM PST 24 |
Feb 04 03:42:07 PM PST 24 |
2436962986 ps |
| T466 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2737856911 |
|
|
Feb 04 01:40:50 PM PST 24 |
Feb 04 01:41:12 PM PST 24 |
1855421892 ps |
| T467 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.517494078 |
|
|
Feb 04 01:49:44 PM PST 24 |
Feb 04 01:49:51 PM PST 24 |
345331458 ps |
| T468 |
/workspace/coverage/default/15.sram_ctrl_bijection.2131805633 |
|
|
Feb 04 01:42:14 PM PST 24 |
Feb 04 01:57:11 PM PST 24 |
74018686590 ps |
| T469 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.4120481870 |
|
|
Feb 04 01:37:31 PM PST 24 |
Feb 04 01:38:06 PM PST 24 |
835046401 ps |
| T470 |
/workspace/coverage/default/24.sram_ctrl_stress_all.91215093 |
|
|
Feb 04 01:44:56 PM PST 24 |
Feb 04 02:38:16 PM PST 24 |
129958223325 ps |
| T471 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2264865962 |
|
|
Feb 04 01:51:16 PM PST 24 |
Feb 04 01:53:56 PM PST 24 |
8557720518 ps |
| T472 |
/workspace/coverage/default/4.sram_ctrl_smoke.2897701976 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:38:09 PM PST 24 |
2784212968 ps |
| T473 |
/workspace/coverage/default/28.sram_ctrl_bijection.2731469491 |
|
|
Feb 04 01:45:59 PM PST 24 |
Feb 04 02:04:53 PM PST 24 |
60616104131 ps |
| T474 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.4266358546 |
|
|
Feb 04 01:43:46 PM PST 24 |
Feb 04 01:46:34 PM PST 24 |
39760115017 ps |
| T475 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1821096087 |
|
|
Feb 04 01:51:17 PM PST 24 |
Feb 04 02:05:57 PM PST 24 |
19614048627 ps |
| T476 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3739886866 |
|
|
Feb 04 01:52:11 PM PST 24 |
Feb 04 01:59:34 PM PST 24 |
5566333820 ps |
| T477 |
/workspace/coverage/default/22.sram_ctrl_alert_test.4095302230 |
|
|
Feb 04 01:44:14 PM PST 24 |
Feb 04 01:44:16 PM PST 24 |
15020029 ps |
| T478 |
/workspace/coverage/default/21.sram_ctrl_partial_access.3889326060 |
|
|
Feb 04 01:43:46 PM PST 24 |
Feb 04 01:44:59 PM PST 24 |
815486997 ps |
| T479 |
/workspace/coverage/default/22.sram_ctrl_smoke.4165184439 |
|
|
Feb 04 01:43:50 PM PST 24 |
Feb 04 01:44:00 PM PST 24 |
846091679 ps |
| T480 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.573945079 |
|
|
Feb 04 01:38:52 PM PST 24 |
Feb 04 01:39:52 PM PST 24 |
733099031 ps |
| T481 |
/workspace/coverage/default/40.sram_ctrl_executable.725489382 |
|
|
Feb 04 01:49:59 PM PST 24 |
Feb 04 01:56:18 PM PST 24 |
2828271242 ps |
| T482 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.308600427 |
|
|
Feb 04 01:43:02 PM PST 24 |
Feb 04 02:02:02 PM PST 24 |
23013036312 ps |
| T483 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2035791563 |
|
|
Feb 04 01:47:43 PM PST 24 |
Feb 04 01:50:10 PM PST 24 |
6204032850 ps |
| T484 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3403567660 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:46:02 PM PST 24 |
2724604139 ps |
| T485 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.201551648 |
|
|
Feb 04 01:50:26 PM PST 24 |
Feb 04 01:52:31 PM PST 24 |
763901613 ps |
| T486 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3779023580 |
|
|
Feb 04 01:51:34 PM PST 24 |
Feb 04 01:52:12 PM PST 24 |
1435087874 ps |
| T487 |
/workspace/coverage/default/0.sram_ctrl_smoke.664728694 |
|
|
Feb 04 01:36:41 PM PST 24 |
Feb 04 01:37:27 PM PST 24 |
880193199 ps |
| T488 |
/workspace/coverage/default/9.sram_ctrl_regwen.3646477113 |
|
|
Feb 04 01:40:39 PM PST 24 |
Feb 04 01:57:58 PM PST 24 |
50113686228 ps |
| T489 |
/workspace/coverage/default/8.sram_ctrl_bijection.761367203 |
|
|
Feb 04 01:39:25 PM PST 24 |
Feb 04 02:12:27 PM PST 24 |
399022239529 ps |
| T490 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.659279712 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:46:14 PM PST 24 |
48517676647 ps |
| T491 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.843785881 |
|
|
Feb 04 01:40:48 PM PST 24 |
Feb 04 01:43:07 PM PST 24 |
11675704321 ps |
| T492 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1121346064 |
|
|
Feb 04 01:36:52 PM PST 24 |
Feb 04 01:38:06 PM PST 24 |
26212673761 ps |
| T493 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.4027196076 |
|
|
Feb 04 01:44:04 PM PST 24 |
Feb 04 01:52:20 PM PST 24 |
2356997692 ps |
| T494 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.196623362 |
|
|
Feb 04 01:49:19 PM PST 24 |
Feb 04 01:49:31 PM PST 24 |
353489645 ps |
| T495 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1915166471 |
|
|
Feb 04 01:46:14 PM PST 24 |
Feb 04 01:48:49 PM PST 24 |
3146570851 ps |
| T496 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.231410619 |
|
|
Feb 04 01:48:53 PM PST 24 |
Feb 04 01:53:20 PM PST 24 |
4155698289 ps |
| T497 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1927210523 |
|
|
Feb 04 01:38:47 PM PST 24 |
Feb 04 01:40:35 PM PST 24 |
1495217972 ps |
| T498 |
/workspace/coverage/default/28.sram_ctrl_executable.677093392 |
|
|
Feb 04 01:46:02 PM PST 24 |
Feb 04 01:47:23 PM PST 24 |
3055619414 ps |
| T499 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1736104007 |
|
|
Feb 04 01:41:08 PM PST 24 |
Feb 04 01:49:30 PM PST 24 |
19169378999 ps |
| T500 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.750855373 |
|
|
Feb 04 01:44:38 PM PST 24 |
Feb 04 01:49:19 PM PST 24 |
40081074984 ps |
| T501 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3338844876 |
|
|
Feb 04 01:48:11 PM PST 24 |
Feb 04 02:09:49 PM PST 24 |
30428846798 ps |
| T502 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1506351173 |
|
|
Feb 04 01:37:20 PM PST 24 |
Feb 04 01:37:24 PM PST 24 |
15417737 ps |
| T503 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1045946417 |
|
|
Feb 04 01:49:35 PM PST 24 |
Feb 04 01:55:36 PM PST 24 |
4275110107 ps |
| T504 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1817681963 |
|
|
Feb 04 01:37:32 PM PST 24 |
Feb 04 02:06:51 PM PST 24 |
1183192859 ps |
| T505 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2627770422 |
|
|
Feb 04 01:40:48 PM PST 24 |
Feb 04 01:40:54 PM PST 24 |
347128141 ps |
| T506 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1991737674 |
|
|
Feb 04 01:39:09 PM PST 24 |
Feb 04 01:41:53 PM PST 24 |
30308548386 ps |
| T507 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4083778451 |
|
|
Feb 04 01:45:23 PM PST 24 |
Feb 04 01:46:13 PM PST 24 |
7185733302 ps |
| T508 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2592322017 |
|
|
Feb 04 01:46:45 PM PST 24 |
Feb 04 01:47:29 PM PST 24 |
3942323137 ps |
| T509 |
/workspace/coverage/default/13.sram_ctrl_regwen.2056945117 |
|
|
Feb 04 01:41:33 PM PST 24 |
Feb 04 01:42:18 PM PST 24 |
10458661267 ps |