T510 |
/workspace/coverage/default/0.sram_ctrl_executable.3518053182 |
|
|
Feb 04 01:36:51 PM PST 24 |
Feb 04 01:45:14 PM PST 24 |
30764684215 ps |
T511 |
/workspace/coverage/default/34.sram_ctrl_bijection.2521215268 |
|
|
Feb 04 01:47:47 PM PST 24 |
Feb 04 02:17:49 PM PST 24 |
159840418388 ps |
T512 |
/workspace/coverage/default/48.sram_ctrl_smoke.2626377467 |
|
|
Feb 04 01:52:22 PM PST 24 |
Feb 04 01:52:40 PM PST 24 |
1409033422 ps |
T513 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3080166816 |
|
|
Feb 04 01:41:18 PM PST 24 |
Feb 04 01:42:39 PM PST 24 |
15612683688 ps |
T514 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.2821169008 |
|
|
Feb 04 01:41:17 PM PST 24 |
Feb 04 01:43:21 PM PST 24 |
784161057 ps |
T515 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.622521546 |
|
|
Feb 04 01:46:40 PM PST 24 |
Feb 04 01:46:45 PM PST 24 |
590699623 ps |
T516 |
/workspace/coverage/default/24.sram_ctrl_alert_test.998891568 |
|
|
Feb 04 01:44:54 PM PST 24 |
Feb 04 01:44:58 PM PST 24 |
15792963 ps |
T517 |
/workspace/coverage/default/3.sram_ctrl_bijection.709510799 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 02:04:19 PM PST 24 |
52030672884 ps |
T518 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2145640382 |
|
|
Feb 04 01:46:36 PM PST 24 |
Feb 04 01:48:20 PM PST 24 |
3554715212 ps |
T519 |
/workspace/coverage/default/27.sram_ctrl_bijection.1294822586 |
|
|
Feb 04 01:45:49 PM PST 24 |
Feb 04 02:27:44 PM PST 24 |
120091841179 ps |
T520 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1326978673 |
|
|
Feb 04 01:36:57 PM PST 24 |
Feb 04 01:39:05 PM PST 24 |
10380489171 ps |
T521 |
/workspace/coverage/default/39.sram_ctrl_bijection.2179543815 |
|
|
Feb 04 01:49:38 PM PST 24 |
Feb 04 02:26:54 PM PST 24 |
526568829515 ps |
T522 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2058205494 |
|
|
Feb 04 01:41:33 PM PST 24 |
Feb 04 01:41:36 PM PST 24 |
15291052 ps |
T523 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2799693742 |
|
|
Feb 04 01:43:04 PM PST 24 |
Feb 04 01:45:01 PM PST 24 |
1771783877 ps |
T524 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3119661839 |
|
|
Feb 04 01:46:15 PM PST 24 |
Feb 04 01:49:29 PM PST 24 |
10454711415 ps |
T525 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1042592596 |
|
|
Feb 04 01:38:55 PM PST 24 |
Feb 04 01:43:59 PM PST 24 |
4548957610 ps |
T526 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.544021841 |
|
|
Feb 04 01:37:41 PM PST 24 |
Feb 04 02:10:01 PM PST 24 |
200066472 ps |
T527 |
/workspace/coverage/default/25.sram_ctrl_bijection.793873433 |
|
|
Feb 04 01:44:55 PM PST 24 |
Feb 04 02:20:34 PM PST 24 |
261375250328 ps |
T528 |
/workspace/coverage/default/23.sram_ctrl_alert_test.4231309270 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:44:38 PM PST 24 |
46395337 ps |
T529 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2647784860 |
|
|
Feb 04 01:43:24 PM PST 24 |
Feb 04 01:43:51 PM PST 24 |
2771042782 ps |
T530 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2225506283 |
|
|
Feb 04 01:39:10 PM PST 24 |
Feb 04 02:10:01 PM PST 24 |
36649783225 ps |
T531 |
/workspace/coverage/default/7.sram_ctrl_executable.853644535 |
|
|
Feb 04 01:39:11 PM PST 24 |
Feb 04 01:48:05 PM PST 24 |
13037536262 ps |
T532 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.151369329 |
|
|
Feb 04 01:50:08 PM PST 24 |
Feb 04 02:00:09 PM PST 24 |
62513895048 ps |
T533 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2472957808 |
|
|
Feb 04 01:44:17 PM PST 24 |
Feb 04 01:47:10 PM PST 24 |
2327877043 ps |
T534 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1916846687 |
|
|
Feb 04 01:49:45 PM PST 24 |
Feb 04 01:54:54 PM PST 24 |
12025794279 ps |
T535 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3695286094 |
|
|
Feb 04 01:43:39 PM PST 24 |
Feb 04 01:46:28 PM PST 24 |
10764724409 ps |
T536 |
/workspace/coverage/default/48.sram_ctrl_alert_test.566922763 |
|
|
Feb 04 01:52:50 PM PST 24 |
Feb 04 01:52:51 PM PST 24 |
11474226 ps |
T537 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1332455681 |
|
|
Feb 04 01:42:15 PM PST 24 |
Feb 04 01:45:29 PM PST 24 |
1719363897 ps |
T538 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1518706131 |
|
|
Feb 04 01:40:51 PM PST 24 |
Feb 04 02:04:44 PM PST 24 |
9385493352 ps |
T539 |
/workspace/coverage/default/22.sram_ctrl_stress_all.983914717 |
|
|
Feb 04 01:44:33 PM PST 24 |
Feb 04 02:47:35 PM PST 24 |
408400157793 ps |
T540 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2118542023 |
|
|
Feb 04 01:52:49 PM PST 24 |
Feb 04 01:55:06 PM PST 24 |
3087230345 ps |
T541 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3295744425 |
|
|
Feb 04 01:53:09 PM PST 24 |
Feb 04 01:53:10 PM PST 24 |
13637655 ps |
T542 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2134394497 |
|
|
Feb 04 01:48:16 PM PST 24 |
Feb 04 01:49:46 PM PST 24 |
2340483040 ps |
T543 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2125746163 |
|
|
Feb 04 01:50:25 PM PST 24 |
Feb 04 01:50:28 PM PST 24 |
38870830 ps |
T544 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1555725676 |
|
|
Feb 04 01:50:09 PM PST 24 |
Feb 04 02:09:01 PM PST 24 |
9947667213 ps |
T545 |
/workspace/coverage/default/45.sram_ctrl_bijection.2805494758 |
|
|
Feb 04 01:51:21 PM PST 24 |
Feb 04 02:19:27 PM PST 24 |
76076268097 ps |
T546 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2706474671 |
|
|
Feb 04 01:42:14 PM PST 24 |
Feb 04 01:59:35 PM PST 24 |
7867446014 ps |
T547 |
/workspace/coverage/default/44.sram_ctrl_bijection.1295934716 |
|
|
Feb 04 01:51:13 PM PST 24 |
Feb 04 02:32:04 PM PST 24 |
206938267545 ps |
T548 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2940833923 |
|
|
Feb 04 01:36:50 PM PST 24 |
Feb 04 01:36:52 PM PST 24 |
45947298 ps |
T549 |
/workspace/coverage/default/43.sram_ctrl_regwen.720857091 |
|
|
Feb 04 01:50:45 PM PST 24 |
Feb 04 01:53:27 PM PST 24 |
14736048768 ps |
T550 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2665600910 |
|
|
Feb 04 01:40:51 PM PST 24 |
Feb 04 01:41:21 PM PST 24 |
2796812398 ps |
T551 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3014860298 |
|
|
Feb 04 01:46:00 PM PST 24 |
Feb 04 01:46:17 PM PST 24 |
3303092872 ps |
T552 |
/workspace/coverage/default/23.sram_ctrl_bijection.2673810542 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:55:43 PM PST 24 |
45304019125 ps |
T553 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1111388299 |
|
|
Feb 04 01:36:43 PM PST 24 |
Feb 04 01:52:30 PM PST 24 |
86755742002 ps |
T554 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2696035620 |
|
|
Feb 04 01:43:12 PM PST 24 |
Feb 04 01:45:33 PM PST 24 |
5536116127 ps |
T555 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2167780633 |
|
|
Feb 04 01:39:10 PM PST 24 |
Feb 04 01:41:29 PM PST 24 |
1984848248 ps |
T556 |
/workspace/coverage/default/4.sram_ctrl_partial_access.3165287164 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:38:24 PM PST 24 |
3895572030 ps |
T557 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1527197312 |
|
|
Feb 04 01:48:56 PM PST 24 |
Feb 04 01:51:08 PM PST 24 |
2082689687 ps |
T558 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.888870869 |
|
|
Feb 04 01:50:07 PM PST 24 |
Feb 04 01:56:41 PM PST 24 |
5474565042 ps |
T559 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2857432202 |
|
|
Feb 04 01:48:53 PM PST 24 |
Feb 04 01:50:01 PM PST 24 |
14392289740 ps |
T560 |
/workspace/coverage/default/14.sram_ctrl_partial_access.764130860 |
|
|
Feb 04 01:41:51 PM PST 24 |
Feb 04 01:42:16 PM PST 24 |
3956547147 ps |
T561 |
/workspace/coverage/default/8.sram_ctrl_executable.2641558203 |
|
|
Feb 04 01:39:52 PM PST 24 |
Feb 04 01:57:13 PM PST 24 |
14444614879 ps |
T562 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2501398507 |
|
|
Feb 04 01:37:58 PM PST 24 |
Feb 04 02:14:22 PM PST 24 |
34645072272 ps |
T563 |
/workspace/coverage/default/8.sram_ctrl_regwen.2411767446 |
|
|
Feb 04 01:39:51 PM PST 24 |
Feb 04 01:46:55 PM PST 24 |
1724670284 ps |
T564 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3348036470 |
|
|
Feb 04 01:52:58 PM PST 24 |
Feb 04 02:24:02 PM PST 24 |
26674152268 ps |
T565 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.918511736 |
|
|
Feb 04 01:40:43 PM PST 24 |
Feb 04 01:45:00 PM PST 24 |
8972041311 ps |
T566 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.50039665 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 02:04:29 PM PST 24 |
32374142726 ps |
T567 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.2460636200 |
|
|
Feb 04 01:49:44 PM PST 24 |
Feb 04 01:52:14 PM PST 24 |
12473592717 ps |
T568 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.864519747 |
|
|
Feb 04 01:49:46 PM PST 24 |
Feb 04 01:52:02 PM PST 24 |
8230304355 ps |
T569 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.810456688 |
|
|
Feb 04 01:51:25 PM PST 24 |
Feb 04 01:58:17 PM PST 24 |
4440149848 ps |
T570 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.661713715 |
|
|
Feb 04 01:43:48 PM PST 24 |
Feb 04 02:00:08 PM PST 24 |
18623073522 ps |
T571 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3332431580 |
|
|
Feb 04 01:46:37 PM PST 24 |
Feb 04 01:49:36 PM PST 24 |
816015886 ps |
T572 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.4237564436 |
|
|
Feb 04 01:44:56 PM PST 24 |
Feb 04 01:46:10 PM PST 24 |
9793853574 ps |
T573 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3426963128 |
|
|
Feb 04 01:42:36 PM PST 24 |
Feb 04 02:41:59 PM PST 24 |
2647461361 ps |
T574 |
/workspace/coverage/default/15.sram_ctrl_executable.3094992380 |
|
|
Feb 04 01:42:06 PM PST 24 |
Feb 04 01:49:18 PM PST 24 |
2119010573 ps |
T575 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4287886132 |
|
|
Feb 04 01:48:47 PM PST 24 |
Feb 04 01:50:19 PM PST 24 |
755677185 ps |
T576 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2941129288 |
|
|
Feb 04 01:49:31 PM PST 24 |
Feb 04 02:07:50 PM PST 24 |
7936213672 ps |
T577 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2943560932 |
|
|
Feb 04 01:39:50 PM PST 24 |
Feb 04 01:40:35 PM PST 24 |
20497260130 ps |
T578 |
/workspace/coverage/default/33.sram_ctrl_partial_access.502118788 |
|
|
Feb 04 01:47:23 PM PST 24 |
Feb 04 01:49:28 PM PST 24 |
910849204 ps |
T579 |
/workspace/coverage/default/47.sram_ctrl_bijection.921599145 |
|
|
Feb 04 01:52:11 PM PST 24 |
Feb 04 02:40:37 PM PST 24 |
755162223000 ps |
T580 |
/workspace/coverage/default/22.sram_ctrl_partial_access.339345515 |
|
|
Feb 04 01:44:01 PM PST 24 |
Feb 04 01:44:20 PM PST 24 |
3122836458 ps |
T581 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2292402424 |
|
|
Feb 04 01:42:55 PM PST 24 |
Feb 04 01:57:40 PM PST 24 |
88587501837 ps |
T582 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3001453847 |
|
|
Feb 04 01:46:56 PM PST 24 |
Feb 04 01:48:09 PM PST 24 |
970192872 ps |
T583 |
/workspace/coverage/default/40.sram_ctrl_regwen.1333429428 |
|
|
Feb 04 01:49:58 PM PST 24 |
Feb 04 02:03:32 PM PST 24 |
22518108792 ps |
T584 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2092174960 |
|
|
Feb 04 01:40:47 PM PST 24 |
Feb 04 01:41:22 PM PST 24 |
1643539451 ps |
T585 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1834621095 |
|
|
Feb 04 01:42:13 PM PST 24 |
Feb 04 01:44:50 PM PST 24 |
13892570084 ps |
T586 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1015640672 |
|
|
Feb 04 01:51:18 PM PST 24 |
Feb 04 01:51:51 PM PST 24 |
6278070853 ps |
T587 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2818880205 |
|
|
Feb 04 01:39:27 PM PST 24 |
Feb 04 01:43:41 PM PST 24 |
52441349746 ps |
T588 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2993940606 |
|
|
Feb 04 01:43:46 PM PST 24 |
Feb 04 01:45:22 PM PST 24 |
776074227 ps |
T589 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3363278447 |
|
|
Feb 04 01:36:57 PM PST 24 |
Feb 04 01:37:37 PM PST 24 |
2892727289 ps |
T590 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3024569879 |
|
|
Feb 04 01:41:51 PM PST 24 |
Feb 04 01:45:47 PM PST 24 |
24611459509 ps |
T591 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3588044637 |
|
|
Feb 04 01:44:37 PM PST 24 |
Feb 04 01:45:58 PM PST 24 |
2360913526 ps |
T592 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3912966358 |
|
|
Feb 04 01:38:23 PM PST 24 |
Feb 04 01:38:37 PM PST 24 |
360120574 ps |
T593 |
/workspace/coverage/default/2.sram_ctrl_smoke.3852690397 |
|
|
Feb 04 01:37:20 PM PST 24 |
Feb 04 01:37:35 PM PST 24 |
2701275924 ps |
T594 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1163569468 |
|
|
Feb 04 01:51:52 PM PST 24 |
Feb 04 03:07:11 PM PST 24 |
138501061678 ps |
T595 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1845375116 |
|
|
Feb 04 01:39:12 PM PST 24 |
Feb 04 01:39:21 PM PST 24 |
1399289463 ps |
T596 |
/workspace/coverage/default/12.sram_ctrl_regwen.866455588 |
|
|
Feb 04 01:41:18 PM PST 24 |
Feb 04 01:50:36 PM PST 24 |
38707513450 ps |
T597 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2059308060 |
|
|
Feb 04 01:51:22 PM PST 24 |
Feb 04 01:54:29 PM PST 24 |
979228665 ps |
T598 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1981857979 |
|
|
Feb 04 01:48:31 PM PST 24 |
Feb 04 01:51:01 PM PST 24 |
12841485400 ps |
T599 |
/workspace/coverage/default/7.sram_ctrl_partial_access.4135134651 |
|
|
Feb 04 01:38:52 PM PST 24 |
Feb 04 01:41:01 PM PST 24 |
2896500060 ps |
T600 |
/workspace/coverage/default/43.sram_ctrl_bijection.1124251646 |
|
|
Feb 04 01:50:50 PM PST 24 |
Feb 04 02:25:41 PM PST 24 |
112224135632 ps |
T601 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.4116975171 |
|
|
Feb 04 01:47:00 PM PST 24 |
Feb 04 01:53:38 PM PST 24 |
5347285219 ps |
T602 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1076088238 |
|
|
Feb 04 01:42:33 PM PST 24 |
Feb 04 01:43:11 PM PST 24 |
2957880905 ps |
T603 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.946758215 |
|
|
Feb 04 01:47:26 PM PST 24 |
Feb 04 02:02:43 PM PST 24 |
19850041144 ps |
T604 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.71172866 |
|
|
Feb 04 01:43:21 PM PST 24 |
Feb 04 01:45:31 PM PST 24 |
755971861 ps |
T28 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3891799181 |
|
|
Feb 04 01:37:56 PM PST 24 |
Feb 04 01:38:00 PM PST 24 |
234458834 ps |
T41 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3526047526 |
|
|
Feb 04 01:47:56 PM PST 24 |
Feb 04 01:51:07 PM PST 24 |
3112204825 ps |
T42 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2858901603 |
|
|
Feb 04 01:51:04 PM PST 24 |
Feb 04 01:51:06 PM PST 24 |
12714689 ps |
T43 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1043280051 |
|
|
Feb 04 01:47:56 PM PST 24 |
Feb 04 01:53:27 PM PST 24 |
11367554363 ps |
T44 |
/workspace/coverage/default/2.sram_ctrl_regwen.1365683616 |
|
|
Feb 04 01:37:32 PM PST 24 |
Feb 04 01:49:51 PM PST 24 |
19842547927 ps |
T45 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.1473422953 |
|
|
Feb 04 01:46:00 PM PST 24 |
Feb 04 02:09:22 PM PST 24 |
19089928139 ps |
T46 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3869050201 |
|
|
Feb 04 01:41:18 PM PST 24 |
Feb 04 01:46:55 PM PST 24 |
43119470820 ps |
T605 |
/workspace/coverage/default/49.sram_ctrl_smoke.4151635834 |
|
|
Feb 04 01:52:50 PM PST 24 |
Feb 04 01:53:36 PM PST 24 |
888291866 ps |
T606 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.484482332 |
|
|
Feb 04 01:51:33 PM PST 24 |
Feb 04 01:54:12 PM PST 24 |
112035878420 ps |
T607 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3765963451 |
|
|
Feb 04 01:36:50 PM PST 24 |
Feb 04 01:39:09 PM PST 24 |
778387150 ps |
T608 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.2026454790 |
|
|
Feb 04 01:47:57 PM PST 24 |
Feb 04 02:10:59 PM PST 24 |
7528599371 ps |
T609 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1783559076 |
|
|
Feb 04 01:50:24 PM PST 24 |
Feb 04 01:53:30 PM PST 24 |
17811324783 ps |
T610 |
/workspace/coverage/default/32.sram_ctrl_alert_test.860611442 |
|
|
Feb 04 01:47:15 PM PST 24 |
Feb 04 01:47:18 PM PST 24 |
18251687 ps |
T611 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.705327583 |
|
|
Feb 04 01:44:47 PM PST 24 |
Feb 04 02:32:09 PM PST 24 |
466271856 ps |
T612 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.94208227 |
|
|
Feb 04 01:41:37 PM PST 24 |
Feb 04 01:44:53 PM PST 24 |
1568275234 ps |
T613 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2132228292 |
|
|
Feb 04 01:51:52 PM PST 24 |
Feb 04 02:17:23 PM PST 24 |
37866970798 ps |
T614 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2990993279 |
|
|
Feb 04 01:51:17 PM PST 24 |
Feb 04 03:55:10 PM PST 24 |
6601699642 ps |
T615 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.4151650555 |
|
|
Feb 04 01:49:20 PM PST 24 |
Feb 04 01:52:06 PM PST 24 |
4759472675 ps |
T616 |
/workspace/coverage/default/26.sram_ctrl_partial_access.424232316 |
|
|
Feb 04 01:45:22 PM PST 24 |
Feb 04 01:45:39 PM PST 24 |
1051795626 ps |
T617 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3566209595 |
|
|
Feb 04 01:51:51 PM PST 24 |
Feb 04 01:58:44 PM PST 24 |
34440509084 ps |
T618 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1378014608 |
|
|
Feb 04 01:50:42 PM PST 24 |
Feb 04 01:56:45 PM PST 24 |
27792010863 ps |
T619 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.280113984 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:38:38 PM PST 24 |
2856315788 ps |
T620 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.206391854 |
|
|
Feb 04 01:45:10 PM PST 24 |
Feb 04 01:49:38 PM PST 24 |
4109177541 ps |
T621 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3169399758 |
|
|
Feb 04 01:48:11 PM PST 24 |
Feb 04 01:55:17 PM PST 24 |
4838246790 ps |
T622 |
/workspace/coverage/default/2.sram_ctrl_alert_test.366357327 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:37:42 PM PST 24 |
62531459 ps |
T623 |
/workspace/coverage/default/41.sram_ctrl_regwen.47231977 |
|
|
Feb 04 01:50:06 PM PST 24 |
Feb 04 01:54:47 PM PST 24 |
35166656256 ps |
T624 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.4231947810 |
|
|
Feb 04 01:42:56 PM PST 24 |
Feb 04 01:43:11 PM PST 24 |
1411919656 ps |
T625 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1996580926 |
|
|
Feb 04 01:49:39 PM PST 24 |
Feb 04 02:01:52 PM PST 24 |
6448454501 ps |
T626 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3564227737 |
|
|
Feb 04 01:42:44 PM PST 24 |
Feb 04 03:00:09 PM PST 24 |
2051690795 ps |
T627 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.923102682 |
|
|
Feb 04 01:49:18 PM PST 24 |
Feb 04 01:51:12 PM PST 24 |
38677255184 ps |
T628 |
/workspace/coverage/default/23.sram_ctrl_regwen.2192951723 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:57:21 PM PST 24 |
16663282839 ps |
T629 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.907140212 |
|
|
Feb 04 01:40:31 PM PST 24 |
Feb 04 01:41:03 PM PST 24 |
1061145912 ps |
T630 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1757271705 |
|
|
Feb 04 01:41:36 PM PST 24 |
Feb 04 01:58:53 PM PST 24 |
8319117633 ps |
T631 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2695040401 |
|
|
Feb 04 01:37:32 PM PST 24 |
Feb 04 02:02:34 PM PST 24 |
124907999023 ps |
T632 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1064227965 |
|
|
Feb 04 01:41:33 PM PST 24 |
Feb 04 01:42:12 PM PST 24 |
8374301648 ps |
T633 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1957831312 |
|
|
Feb 04 01:47:58 PM PST 24 |
Feb 04 01:49:16 PM PST 24 |
11085322231 ps |
T634 |
/workspace/coverage/default/6.sram_ctrl_alert_test.4098932519 |
|
|
Feb 04 01:38:51 PM PST 24 |
Feb 04 01:38:54 PM PST 24 |
37154488 ps |
T635 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3041857391 |
|
|
Feb 04 01:45:11 PM PST 24 |
Feb 04 03:13:10 PM PST 24 |
1149762210 ps |
T636 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.687802387 |
|
|
Feb 04 01:46:03 PM PST 24 |
Feb 04 01:50:58 PM PST 24 |
14073951537 ps |
T637 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1400980441 |
|
|
Feb 04 01:52:12 PM PST 24 |
Feb 04 01:52:20 PM PST 24 |
691378145 ps |
T638 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1112472794 |
|
|
Feb 04 01:42:19 PM PST 24 |
Feb 04 01:44:06 PM PST 24 |
4715532089 ps |
T639 |
/workspace/coverage/default/32.sram_ctrl_smoke.2394107907 |
|
|
Feb 04 01:46:56 PM PST 24 |
Feb 04 01:49:09 PM PST 24 |
1538756757 ps |
T640 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2401521134 |
|
|
Feb 04 01:46:00 PM PST 24 |
Feb 04 01:51:14 PM PST 24 |
3925665052 ps |
T641 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2428652796 |
|
|
Feb 04 01:40:50 PM PST 24 |
Feb 04 01:41:19 PM PST 24 |
3048638680 ps |
T642 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1748175860 |
|
|
Feb 04 01:36:57 PM PST 24 |
Feb 04 01:37:13 PM PST 24 |
351585765 ps |
T643 |
/workspace/coverage/default/15.sram_ctrl_regwen.546203270 |
|
|
Feb 04 01:42:07 PM PST 24 |
Feb 04 02:02:22 PM PST 24 |
15080832679 ps |
T644 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.612762209 |
|
|
Feb 04 01:37:42 PM PST 24 |
Feb 04 01:38:21 PM PST 24 |
713293714 ps |
T645 |
/workspace/coverage/default/13.sram_ctrl_bijection.4176945263 |
|
|
Feb 04 01:41:31 PM PST 24 |
Feb 04 01:49:30 PM PST 24 |
7232716094 ps |
T646 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.4198836458 |
|
|
Feb 04 01:44:06 PM PST 24 |
Feb 04 01:44:14 PM PST 24 |
699016118 ps |
T647 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.4021289818 |
|
|
Feb 04 01:41:51 PM PST 24 |
Feb 04 01:47:09 PM PST 24 |
26548805528 ps |
T648 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2217853460 |
|
|
Feb 04 01:46:42 PM PST 24 |
Feb 04 02:57:19 PM PST 24 |
865115650 ps |
T649 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.99055028 |
|
|
Feb 04 01:42:21 PM PST 24 |
Feb 04 01:46:28 PM PST 24 |
16422449775 ps |
T650 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3560496854 |
|
|
Feb 04 01:46:35 PM PST 24 |
Feb 04 01:46:37 PM PST 24 |
34948580 ps |
T651 |
/workspace/coverage/default/13.sram_ctrl_smoke.1119801543 |
|
|
Feb 04 01:41:32 PM PST 24 |
Feb 04 01:42:39 PM PST 24 |
1625851070 ps |
T652 |
/workspace/coverage/default/30.sram_ctrl_bijection.1739045269 |
|
|
Feb 04 01:46:36 PM PST 24 |
Feb 04 01:59:09 PM PST 24 |
50701342410 ps |
T653 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2700648115 |
|
|
Feb 04 01:41:17 PM PST 24 |
Feb 04 02:06:10 PM PST 24 |
53726432539 ps |
T654 |
/workspace/coverage/default/28.sram_ctrl_regwen.3463238954 |
|
|
Feb 04 01:46:00 PM PST 24 |
Feb 04 02:03:39 PM PST 24 |
62921267882 ps |
T655 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3973178012 |
|
|
Feb 04 01:52:27 PM PST 24 |
Feb 04 01:59:24 PM PST 24 |
16827814982 ps |
T656 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.2968912620 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:51:36 PM PST 24 |
6707303700 ps |
T657 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1689395776 |
|
|
Feb 04 01:52:12 PM PST 24 |
Feb 04 01:54:05 PM PST 24 |
7618832862 ps |
T658 |
/workspace/coverage/default/10.sram_ctrl_regwen.3997675475 |
|
|
Feb 04 01:40:50 PM PST 24 |
Feb 04 01:56:55 PM PST 24 |
3339751084 ps |
T659 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3471810335 |
|
|
Feb 04 01:47:45 PM PST 24 |
Feb 04 01:54:10 PM PST 24 |
1684436346 ps |
T660 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2755734412 |
|
|
Feb 04 01:43:02 PM PST 24 |
Feb 04 01:51:19 PM PST 24 |
121353615052 ps |
T661 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1217747081 |
|
|
Feb 04 01:37:00 PM PST 24 |
Feb 04 01:37:32 PM PST 24 |
2820548729 ps |
T662 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1380763282 |
|
|
Feb 04 01:44:58 PM PST 24 |
Feb 04 01:46:41 PM PST 24 |
1164258973 ps |
T663 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1988065103 |
|
|
Feb 04 01:50:26 PM PST 24 |
Feb 04 02:43:01 PM PST 24 |
526835797 ps |
T664 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2333266535 |
|
|
Feb 04 01:43:49 PM PST 24 |
Feb 04 01:45:17 PM PST 24 |
4801252220 ps |
T665 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.4177225461 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:43:40 PM PST 24 |
21086658676 ps |
T666 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.1148211986 |
|
|
Feb 04 01:45:23 PM PST 24 |
Feb 04 01:47:14 PM PST 24 |
56813596715 ps |
T667 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1476090982 |
|
|
Feb 04 01:45:22 PM PST 24 |
Feb 04 01:45:50 PM PST 24 |
734642738 ps |
T668 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3908551273 |
|
|
Feb 04 01:45:44 PM PST 24 |
Feb 04 01:47:43 PM PST 24 |
19636115703 ps |
T669 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3420512384 |
|
|
Feb 04 01:42:44 PM PST 24 |
Feb 04 01:43:43 PM PST 24 |
23074474253 ps |
T670 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2721217988 |
|
|
Feb 04 01:44:57 PM PST 24 |
Feb 04 01:52:13 PM PST 24 |
13172691147 ps |
T671 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.170068213 |
|
|
Feb 04 01:46:53 PM PST 24 |
Feb 04 02:14:00 PM PST 24 |
187060826024 ps |
T672 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3615276456 |
|
|
Feb 04 01:43:06 PM PST 24 |
Feb 04 01:43:49 PM PST 24 |
738295950 ps |
T673 |
/workspace/coverage/default/36.sram_ctrl_alert_test.536263929 |
|
|
Feb 04 01:48:52 PM PST 24 |
Feb 04 01:48:53 PM PST 24 |
37171348 ps |
T674 |
/workspace/coverage/default/14.sram_ctrl_executable.3635057618 |
|
|
Feb 04 01:41:51 PM PST 24 |
Feb 04 01:49:49 PM PST 24 |
16786245787 ps |
T675 |
/workspace/coverage/default/17.sram_ctrl_partial_access.62897932 |
|
|
Feb 04 01:42:46 PM PST 24 |
Feb 04 01:43:40 PM PST 24 |
4177695212 ps |
T676 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.2045685063 |
|
|
Feb 04 01:49:08 PM PST 24 |
Feb 04 01:51:20 PM PST 24 |
1567630768 ps |
T677 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.508462513 |
|
|
Feb 04 01:49:17 PM PST 24 |
Feb 04 02:08:28 PM PST 24 |
32439216740 ps |
T678 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.628380330 |
|
|
Feb 04 01:36:50 PM PST 24 |
Feb 04 01:47:13 PM PST 24 |
3572925029 ps |
T679 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.4236177771 |
|
|
Feb 04 01:50:23 PM PST 24 |
Feb 04 01:52:48 PM PST 24 |
8880970891 ps |
T680 |
/workspace/coverage/default/27.sram_ctrl_smoke.3117832616 |
|
|
Feb 04 01:45:46 PM PST 24 |
Feb 04 01:46:03 PM PST 24 |
385863296 ps |
T681 |
/workspace/coverage/default/1.sram_ctrl_partial_access.391905593 |
|
|
Feb 04 01:36:56 PM PST 24 |
Feb 04 01:39:49 PM PST 24 |
4048631220 ps |
T682 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.4070858665 |
|
|
Feb 04 01:44:35 PM PST 24 |
Feb 04 01:46:56 PM PST 24 |
15653049701 ps |
T683 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2603791450 |
|
|
Feb 04 01:43:47 PM PST 24 |
Feb 04 01:51:36 PM PST 24 |
13248192715 ps |
T684 |
/workspace/coverage/default/19.sram_ctrl_smoke.2437272241 |
|
|
Feb 04 01:42:59 PM PST 24 |
Feb 04 01:43:24 PM PST 24 |
1084859829 ps |
T685 |
/workspace/coverage/default/48.sram_ctrl_regwen.3173559945 |
|
|
Feb 04 01:52:42 PM PST 24 |
Feb 04 01:55:58 PM PST 24 |
26033669355 ps |
T686 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3292934281 |
|
|
Feb 04 01:41:17 PM PST 24 |
Feb 04 01:47:48 PM PST 24 |
18799036330 ps |
T687 |
/workspace/coverage/default/27.sram_ctrl_partial_access.701843298 |
|
|
Feb 04 01:45:44 PM PST 24 |
Feb 04 01:49:02 PM PST 24 |
3538739911 ps |
T688 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.785475600 |
|
|
Feb 04 01:43:12 PM PST 24 |
Feb 04 01:44:31 PM PST 24 |
2373615524 ps |
T689 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3783085056 |
|
|
Feb 04 01:39:33 PM PST 24 |
Feb 04 01:41:24 PM PST 24 |
4751397400 ps |
T690 |
/workspace/coverage/default/39.sram_ctrl_smoke.2758829407 |
|
|
Feb 04 01:49:23 PM PST 24 |
Feb 04 01:49:44 PM PST 24 |
840416910 ps |
T691 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.89618588 |
|
|
Feb 04 01:43:13 PM PST 24 |
Feb 04 01:53:40 PM PST 24 |
149472259238 ps |
T692 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3383459458 |
|
|
Feb 04 01:48:44 PM PST 24 |
Feb 04 01:52:55 PM PST 24 |
7407201413 ps |
T693 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3325807013 |
|
|
Feb 04 01:47:41 PM PST 24 |
Feb 04 01:47:43 PM PST 24 |
43057921 ps |
T694 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2089684054 |
|
|
Feb 04 01:43:15 PM PST 24 |
Feb 04 01:43:17 PM PST 24 |
44833698 ps |
T695 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2440629621 |
|
|
Feb 04 01:42:30 PM PST 24 |
Feb 04 01:43:10 PM PST 24 |
707342823 ps |
T696 |
/workspace/coverage/default/30.sram_ctrl_regwen.3415884035 |
|
|
Feb 04 01:46:41 PM PST 24 |
Feb 04 01:59:49 PM PST 24 |
11627986194 ps |
T697 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2059254651 |
|
|
Feb 04 01:52:19 PM PST 24 |
Feb 04 01:53:41 PM PST 24 |
2646882988 ps |
T698 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.438331432 |
|
|
Feb 04 01:47:34 PM PST 24 |
Feb 04 01:51:42 PM PST 24 |
4196661337 ps |
T699 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1185633307 |
|
|
Feb 04 01:48:29 PM PST 24 |
Feb 04 02:37:56 PM PST 24 |
637221685101 ps |
T700 |
/workspace/coverage/default/31.sram_ctrl_smoke.1592911346 |
|
|
Feb 04 01:46:40 PM PST 24 |
Feb 04 01:46:56 PM PST 24 |
1511738090 ps |
T701 |
/workspace/coverage/default/42.sram_ctrl_smoke.3392447569 |
|
|
Feb 04 01:50:27 PM PST 24 |
Feb 04 01:51:04 PM PST 24 |
996802723 ps |
T702 |
/workspace/coverage/default/28.sram_ctrl_stress_all.3048611937 |
|
|
Feb 04 01:46:12 PM PST 24 |
Feb 04 02:48:56 PM PST 24 |
431486518198 ps |
T703 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.33424035 |
|
|
Feb 04 01:40:48 PM PST 24 |
Feb 04 01:52:17 PM PST 24 |
12215004915 ps |
T704 |
/workspace/coverage/default/31.sram_ctrl_executable.4238713816 |
|
|
Feb 04 01:46:43 PM PST 24 |
Feb 04 01:49:15 PM PST 24 |
2056232650 ps |
T705 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3517605916 |
|
|
Feb 04 01:51:33 PM PST 24 |
Feb 04 01:51:48 PM PST 24 |
346748912 ps |
T706 |
/workspace/coverage/default/32.sram_ctrl_partial_access.370929213 |
|
|
Feb 04 01:47:13 PM PST 24 |
Feb 04 01:47:54 PM PST 24 |
2952978815 ps |
T707 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2880186053 |
|
|
Feb 04 01:38:51 PM PST 24 |
Feb 04 01:46:15 PM PST 24 |
35140378351 ps |
T708 |
/workspace/coverage/default/4.sram_ctrl_regwen.307753251 |
|
|
Feb 04 01:37:56 PM PST 24 |
Feb 04 01:50:10 PM PST 24 |
3619495663 ps |
T709 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.2609537674 |
|
|
Feb 04 01:43:02 PM PST 24 |
Feb 04 01:44:54 PM PST 24 |
10814816478 ps |
T710 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1540260159 |
|
|
Feb 04 01:46:52 PM PST 24 |
Feb 04 01:49:23 PM PST 24 |
40732111513 ps |
T711 |
/workspace/coverage/default/29.sram_ctrl_bijection.3555694304 |
|
|
Feb 04 01:46:14 PM PST 24 |
Feb 04 02:20:39 PM PST 24 |
188935927861 ps |
T712 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3440884057 |
|
|
Feb 04 01:39:49 PM PST 24 |
Feb 04 01:40:04 PM PST 24 |
1413058592 ps |
T713 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.321557261 |
|
|
Feb 04 01:41:23 PM PST 24 |
Feb 04 01:41:32 PM PST 24 |
345193003 ps |
T714 |
/workspace/coverage/default/30.sram_ctrl_stress_all.964180672 |
|
|
Feb 04 01:46:39 PM PST 24 |
Feb 04 02:42:47 PM PST 24 |
94082161878 ps |
T715 |
/workspace/coverage/default/43.sram_ctrl_partial_access.705457042 |
|
|
Feb 04 01:50:44 PM PST 24 |
Feb 04 01:51:57 PM PST 24 |
3230919764 ps |
T716 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3598041672 |
|
|
Feb 04 01:42:21 PM PST 24 |
Feb 04 01:50:22 PM PST 24 |
5883971880 ps |
T717 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2488673269 |
|
|
Feb 04 01:38:11 PM PST 24 |
Feb 04 01:39:32 PM PST 24 |
1698261425 ps |
T718 |
/workspace/coverage/default/42.sram_ctrl_regwen.3158352425 |
|
|
Feb 04 01:50:28 PM PST 24 |
Feb 04 02:12:01 PM PST 24 |
43151727194 ps |
T719 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1005759411 |
|
|
Feb 04 01:39:12 PM PST 24 |
Feb 04 01:40:53 PM PST 24 |
3013470185 ps |
T720 |
/workspace/coverage/default/44.sram_ctrl_regwen.2525174442 |
|
|
Feb 04 01:51:17 PM PST 24 |
Feb 04 02:03:24 PM PST 24 |
12659212505 ps |
T721 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2532081273 |
|
|
Feb 04 01:47:15 PM PST 24 |
Feb 04 01:49:38 PM PST 24 |
5226546247 ps |
T722 |
/workspace/coverage/default/30.sram_ctrl_smoke.3692863320 |
|
|
Feb 04 01:46:43 PM PST 24 |
Feb 04 01:47:07 PM PST 24 |
1108647020 ps |
T723 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.967466863 |
|
|
Feb 04 01:50:15 PM PST 24 |
Feb 04 01:51:40 PM PST 24 |
2635033418 ps |
T724 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3315707404 |
|
|
Feb 04 01:37:56 PM PST 24 |
Feb 04 01:40:37 PM PST 24 |
4023665691 ps |
T725 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2553156620 |
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|
Feb 04 01:49:44 PM PST 24 |
Feb 04 01:51:38 PM PST 24 |
1750171657 ps |
T726 |
/workspace/coverage/default/6.sram_ctrl_bijection.3272772777 |
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|
Feb 04 01:38:49 PM PST 24 |
Feb 04 01:58:13 PM PST 24 |
124020353540 ps |
T727 |
/workspace/coverage/default/17.sram_ctrl_smoke.786111154 |
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|
Feb 04 01:42:44 PM PST 24 |
Feb 04 01:45:40 PM PST 24 |
5442546028 ps |
T728 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1115227269 |
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|
Feb 04 01:50:28 PM PST 24 |
Feb 04 01:51:14 PM PST 24 |
2268121813 ps |
T729 |
/workspace/coverage/default/32.sram_ctrl_bijection.2431043488 |
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|
Feb 04 01:46:53 PM PST 24 |
Feb 04 02:16:08 PM PST 24 |
40300517118 ps |
T730 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1126641717 |
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|
Feb 04 01:41:35 PM PST 24 |
Feb 04 02:25:49 PM PST 24 |
57866429172 ps |
T731 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2110917479 |
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|
Feb 04 01:37:42 PM PST 24 |
Feb 04 01:49:27 PM PST 24 |
28259049959 ps |
T732 |
/workspace/coverage/default/34.sram_ctrl_smoke.2511308763 |
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|
Feb 04 01:47:46 PM PST 24 |
Feb 04 01:48:57 PM PST 24 |
2202282118 ps |
T733 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.2754581653 |
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|
Feb 04 01:42:24 PM PST 24 |
Feb 04 01:43:50 PM PST 24 |
3019219896 ps |
T734 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.2128345636 |
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|
Feb 04 01:49:02 PM PST 24 |
Feb 04 01:56:02 PM PST 24 |
6473592900 ps |
T735 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2507063383 |
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|
Feb 04 01:41:08 PM PST 24 |
Feb 04 01:42:19 PM PST 24 |
949087099 ps |
T736 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3185007464 |
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|
Feb 04 01:45:59 PM PST 24 |
Feb 04 01:48:19 PM PST 24 |
1572447558 ps |
T737 |
/workspace/coverage/default/14.sram_ctrl_bijection.2106281817 |
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|
Feb 04 01:41:35 PM PST 24 |
Feb 04 02:15:37 PM PST 24 |
489023997183 ps |
T738 |
/workspace/coverage/default/12.sram_ctrl_bijection.2248745043 |
|
|
Feb 04 01:41:23 PM PST 24 |
Feb 04 01:55:11 PM PST 24 |
67468551053 ps |
T739 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2932452887 |
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|
Feb 04 01:42:57 PM PST 24 |
Feb 04 01:43:54 PM PST 24 |
10211663922 ps |
T740 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.417529713 |
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|
Feb 04 01:51:52 PM PST 24 |
Feb 04 01:59:06 PM PST 24 |
13698374118 ps |
T741 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3854621600 |
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|
Feb 04 01:36:57 PM PST 24 |
Feb 04 01:42:46 PM PST 24 |
112923999841 ps |
T742 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2618810788 |
|
|
Feb 04 01:37:39 PM PST 24 |
Feb 04 01:38:29 PM PST 24 |
1044494748 ps |
T743 |
/workspace/coverage/default/28.sram_ctrl_smoke.2204682204 |
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|
Feb 04 01:45:45 PM PST 24 |
Feb 04 01:46:14 PM PST 24 |
2731938279 ps |
T744 |
/workspace/coverage/default/29.sram_ctrl_regwen.3671783885 |
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|
Feb 04 01:46:14 PM PST 24 |
Feb 04 01:55:38 PM PST 24 |
11885339348 ps |
T745 |
/workspace/coverage/default/45.sram_ctrl_regwen.4085276805 |
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|
Feb 04 01:51:32 PM PST 24 |
Feb 04 02:06:34 PM PST 24 |
28355519822 ps |
T746 |
/workspace/coverage/default/27.sram_ctrl_regwen.4139494144 |
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|
Feb 04 01:45:46 PM PST 24 |
Feb 04 02:05:13 PM PST 24 |
25887271982 ps |
T747 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1039916951 |
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|
Feb 04 01:42:33 PM PST 24 |
Feb 04 01:48:16 PM PST 24 |
68085891464 ps |
T748 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3933097057 |
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|
Feb 04 01:39:51 PM PST 24 |
Feb 04 01:42:28 PM PST 24 |
3136224141 ps |
T749 |
/workspace/coverage/default/20.sram_ctrl_bijection.1457056764 |
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|
Feb 04 01:43:13 PM PST 24 |
Feb 04 02:17:33 PM PST 24 |
90256307705 ps |
T750 |
/workspace/coverage/default/33.sram_ctrl_bijection.3278020689 |
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|
Feb 04 01:47:23 PM PST 24 |
Feb 04 02:14:28 PM PST 24 |
215858121669 ps |
T751 |
/workspace/coverage/default/16.sram_ctrl_alert_test.409331764 |
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|
Feb 04 01:42:34 PM PST 24 |
Feb 04 01:42:36 PM PST 24 |
30367536 ps |
T752 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.2101334019 |
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Feb 04 01:43:05 PM PST 24 |
Feb 04 01:45:08 PM PST 24 |
2059272847 ps |