49a27e136c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.600m | 2.645ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.710s | 20.983us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.720s | 19.463us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.470s | 680.438us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.740s | 116.387us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 16.640s | 4.785ms | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.720s | 19.463us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.740s | 116.387us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 6.503m | 229.441ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 2.859m | 17.405ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 185 | 205 | 90.24 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 39.786m | 132.393ms | 49 | 50 | 98.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.694m | 6.289ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 49.845m | 689.316ms | 48 | 50 | 96.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 38.246m | 24.692ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 5.822m | 49.013ms | 41 | 50 | 82.00 |
| V2 | executable | sram_ctrl_executable | 39.236m | 31.069ms | 19 | 50 | 38.00 |
| V2 | partial_access | sram_ctrl_partial_access | 3.092m | 8.656ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 8.826m | 23.815ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 3.118m | 833.087us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 3.169m | 9.762ms | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 26.008m | 77.005ms | 49 | 50 | 98.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 15.600s | 4.783ms | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.506h | 814.665ms | 30 | 50 | 60.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.750s | 161.471us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.800s | 75.918us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.800s | 75.918us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.710s | 20.983us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.720s | 19.463us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.740s | 116.387us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.880s | 109.418us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.710s | 20.983us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.720s | 19.463us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.740s | 116.387us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.880s | 109.418us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 676 | 740 | 91.35 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 4.523m | 37.050ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.300s | 235.138us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.770s | 649.703us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.300s | 235.138us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.770s | 649.703us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 26.008m | 77.005ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.720s | 19.463us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 39.236m | 31.069ms | 19 | 50 | 38.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 39.236m | 31.069ms | 19 | 50 | 38.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 39.236m | 31.069ms | 19 | 50 | 38.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 5.822m | 49.013ms | 41 | 50 | 82.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 4.523m | 37.050ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.600m | 2.645ms | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.600m | 2.645ms | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 39.236m | 31.069ms | 19 | 50 | 38.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.300s | 235.138us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 5.822m | 49.013ms | 41 | 50 | 82.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.300s | 235.138us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.300s | 235.138us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.600m | 2.645ms | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.300s | 235.138us | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 1.273m | 2.179ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 906 | 1040 | 87.12 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 10 | 62.50 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.26 | 100.00 | 97.62 | 100.00 | 100.00 | 99.15 | 99.70 | 98.33 |
UVM_ERROR (cip_base_vseq.sv:774) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 70 failures:
0.sram_ctrl_stress_all_with_rand_reset.97778360384142599829152116300013338508107260665675198387945980044899780705629
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 248792612 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 248792612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_stress_all_with_rand_reset.74611125541600788941341190366089720625954813483474624633218893536173621504542
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 777648448 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 777648448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.sram_ctrl_csr_mem_rw_with_rand_reset.9481192037935141100469638844043722002417395714288304862394045890738327550643
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1828600476 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 1828600476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_csr_mem_rw_with_rand_reset.37319356510992366694843634261250797781465730052604944154309709139266711746999
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 437990284 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 437990284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:164) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) item_err: *, allow_ifetch : *, sram_ifetch: *, exec: *, debug_en: *, lc_esc * has 13 failures:
0.sram_ctrl_executable.46343557818606843086121121941023807564370238305484298553673952596952368745847
Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 47387321391 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 105, exec: 6, debug_en: 10, lc_esc 0
UVM_INFO @ 47387321391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sram_ctrl_executable.90365754426711821250592165330348751157399476785628110249720780003717441424572
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 3438214807 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 150, exec: 9, debug_en: 5, lc_esc 0
UVM_INFO @ 3438214807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
4.sram_ctrl_stress_all.79388056039472034877928431615193711869056568816597903993589455524673264994030
Line 313, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 8929930119 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 105, exec: 6, debug_en: 7, lc_esc 0
UVM_INFO @ 8929930119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sram_ctrl_stress_all.65125962510150966255512513325933056904585740306928568686341616746093303664687
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 6533091630 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 150, exec: 1, debug_en: 10, lc_esc 0
UVM_INFO @ 6533091630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 13 failures:
5.sram_ctrl_lc_escalation.59290725839550242237526546330831119894709965107119347465198702277690628543728
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 681968285 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 681968285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.sram_ctrl_lc_escalation.2483775347989622109400562629225677718415462966010085266449175962993478194664
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 39197502558 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 39197502558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
35.sram_ctrl_stress_all.70377773983499298262368104880517897920367131022524907258755944058159704464713
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 12114434823 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 12114434823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.sram_ctrl_stress_all.76160894647129112310771949349154781714813237147486096380956564399244617357406
Line 415, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 256182210020 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 256182210020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
18.sram_ctrl_bijection.96706355076071577101660077936141518251004216573635060247130938516952042904221
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.sram_ctrl_bijection.21072105674828619509075073966899881220128860256182050478225550156636229839217
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4957471) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.sram_ctrl_stress_all.16801560285536488737782831668145559483901722141900500667568149624505032114812
Line 331, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 39003470907 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4957471) { a_addr: 'hede1cedc a_data: 'h89cf48fe a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9d a_opcode: 'h4 a_user: 'h19ced d_param: 'h0 d_source: 'h9d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 39003470907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1935348) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.sram_ctrl_executable.89930825268180726043252361615505295733029262302087803412905376972616430813811
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 1473067430 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1935348) { a_addr: 'h3cad89c4 a_data: 'h14248749 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'heb a_opcode: 'h4 a_user: 'h18b5c d_param: 'h0 d_source: 'heb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1473067430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2926880) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.sram_ctrl_executable.53963641234701148818403351234427816157965480869962503957265107089713300811922
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 4021146328 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2926880) { a_addr: 'hbf040b40 a_data: 'h876423f0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hcb a_opcode: 'h4 a_user: 'h1999a d_param: 'h0 d_source: 'hcb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4021146328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@29186733) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.sram_ctrl_stress_all.43157958587061482275165746655272617337530204907259587413886876306393248009759
Line 316, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 29664598209 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@29186733) { a_addr: 'h30dc2d84 a_data: 'he0874116 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hac a_opcode: 'h4 a_user: 'h18fc5 d_param: 'h0 d_source: 'hac d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 29664598209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496299) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.sram_ctrl_executable.97430251761773584339672798044000399929960697539122159326566859368772583666589
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 347372004 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496299) { a_addr: 'hbccf411c a_data: 'h8b2e643a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'had a_opcode: 'h4 a_user: 'h1a6dc d_param: 'h0 d_source: 'had d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 347372004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@19461459) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.sram_ctrl_stress_all.24911808817353914960765296565624340464636062603604761161901278923810906467850
Line 297, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 137880472534 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@19461459) { a_addr: 'h5b7b51c4 a_data: 'hfbb969db a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h89 a_opcode: 'h4 a_user: 'h1ac04 d_param: 'h0 d_source: 'h89 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 137880472534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@765588) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.sram_ctrl_executable.71362870204175669187232562572654010121870560812611252378290381695426205720402
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 12848320187 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@765588) { a_addr: 'he1f3c7f0 a_data: 'hc7e85bd3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha9 a_opcode: 'h4 a_user: 'h1a360 d_param: 'h0 d_source: 'ha9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 12848320187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@44873349) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.sram_ctrl_stress_all.107296051721706918206337845494284962046635248374813631785307639213509507353867
Line 366, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 213695095868 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@44873349) { a_addr: 'h8d266edc a_data: 'h72d5b08d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5e a_opcode: 'h4 a_user: 'h1ae96 d_param: 'h0 d_source: 'h5e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 213695095868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1958060) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.sram_ctrl_executable.101346263421214480606566478465731876206259609260653314783343861161662350351080
Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 7564477413 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1958060) { a_addr: 'h6ba53b40 a_data: 'h5e3bbc2f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h18773 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 7564477413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2686596) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.sram_ctrl_executable.44889931070508411453436811018884168046270631215356615005945041356823693622163
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 1883747847 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2686596) { a_addr: 'hb5605948 a_data: 'h7abb16e6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h42 a_opcode: 'h4 a_user: 'h18403 d_param: 'h0 d_source: 'h42 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1883747847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3387474) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.sram_ctrl_executable.4684456767092574039609548655871549912843958758859816881266754636176778761355
Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 21585336272 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3387474) { a_addr: 'he009b610 a_data: 'h47fcb8dd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb8 a_opcode: 'h4 a_user: 'h186f3 d_param: 'h0 d_source: 'hb8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 21585336272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@19093337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.sram_ctrl_stress_all.31094733287113040482807935388341664283160852695738576396359218332193411724305
Line 499, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 581283268418 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@19093337) { a_addr: 'hcf334f48 a_data: 'h93c35e68 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc4 a_opcode: 'h4 a_user: 'h1ae96 d_param: 'h0 d_source: 'hc4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 581283268418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@7908970) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.sram_ctrl_executable.95073920384190882868778806634700014050402462726780984551951391536342524092302
Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 5666303163 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@7908970) { a_addr: 'h393320dc a_data: 'hc845ea2e a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'hcb a_opcode: 'h4 a_user: 'h19e3a d_param: 'h0 d_source: 'hcb d_data: 'h0 d_size: 'h1 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'h2aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 5666303163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@88043357) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.sram_ctrl_stress_all.102649053950356982639939974921570885380291500241021813149184942172872059329852
Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 95215750477 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@88043357) { a_addr: 'hdd71a618 a_data: 'h592f1931 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha6 a_opcode: 'h4 a_user: 'h1972d d_param: 'h0 d_source: 'ha6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 95215750477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
21.sram_ctrl_regwen.62044008311730159027587256132668668583661500714717011042611527222223563632112
Line 313, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 122806088471 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3702530e
UVM_INFO @ 122806088471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@8159469) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
21.sram_ctrl_stress_all.88302765170784935844147943630287362906785243812493338016357434203163442183434
Line 386, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 28209647751 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@8159469) { a_addr: 'h9a0a7a00 a_data: 'h5f42496e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h87 a_opcode: 'h4 a_user: 'h19ded d_param: 'h0 d_source: 'h87 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 28209647751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@498278) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
22.sram_ctrl_executable.84145708339552918019408577043763860727766095620505161744913258199977919192951
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 6502810699 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@498278) { a_addr: 'h8a9d96e4 a_data: 'hbf50d4b8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he0 a_opcode: 'h4 a_user: 'h18553 d_param: 'h0 d_source: 'he0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 6502810699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1590928) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
24.sram_ctrl_executable.104280788019999117597580627133612247557174397752388227166971628625066976398917
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 3989728662 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1590928) { a_addr: 'hfab39fbc a_data: 'h36977b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h73 a_opcode: 'h4 a_user: 'h1b572 d_param: 'h0 d_source: 'h73 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3989728662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4447734) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
26.sram_ctrl_executable.77024180804845997220432073834175130671261546716712378582101160170086093740771
Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 3135387340 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4447734) { a_addr: 'h795f79b0 a_data: 'h977bb6da a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc5 a_opcode: 'h4 a_user: 'h1adad d_param: 'h0 d_source: 'hc5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3135387340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1678416) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
28.sram_ctrl_stress_all.45417591157196994330630483674627078280263746968275759957862339242228631204051
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 4355319080 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1678416) { a_addr: 'ha46df878 a_data: 'hf096adae a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h43 a_opcode: 'h4 a_user: 'h191b8 d_param: 'h0 d_source: 'h43 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4355319080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@18648807) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
29.sram_ctrl_stress_all.60747719242797809351519607155029598662833167060585141401757819194820744624637
Line 432, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 66162747999 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@18648807) { a_addr: 'h1019824 a_data: 'h4006dd08 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he1 a_opcode: 'h4 a_user: 'h1b999 d_param: 'h0 d_source: 'he1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 66162747999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
31.sram_ctrl_multiple_keys.26815037076318695745730082578207629437690499109056488049958558457125823183889
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest/run.log
UVM_FATAL @ 32691074148 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x7e1e6c4b
UVM_INFO @ 32691074148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2345398) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
31.sram_ctrl_executable.59154462338464354044753642494306705243362981422698016239576259424866467908626
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 6621929600 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2345398) { a_addr: 'h96cb6f94 a_data: 'h27eb45bf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he1 a_opcode: 'h4 a_user: 'h1a15d d_param: 'h0 d_source: 'he1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 6621929600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3927160) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
32.sram_ctrl_executable.98084657464929900281803795744306997333155547781024076808404633355265312048495
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 3865280631 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3927160) { a_addr: 'h87289c4 a_data: 'h541e08f5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc3 a_opcode: 'h4 a_user: 'h19907 d_param: 'h0 d_source: 'hc3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3865280631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1068276) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
33.sram_ctrl_executable.80742079323993911715518357113004177877751471483643362211437030920456297800909
Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 3883690094 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1068276) { a_addr: 'he99ce9e0 a_data: 'h56e9e94d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2f a_opcode: 'h4 a_user: 'h1a1c0 d_param: 'h0 d_source: 'h2f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3883690094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6949588) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
35.sram_ctrl_executable.98349010022231637658740803834456343052588936388532496902443325345383990187907
Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 6216602836 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6949588) { a_addr: 'h47d42ed0 a_data: 'h2675c5bb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h53 a_opcode: 'h4 a_user: 'h1aeeb d_param: 'h0 d_source: 'h53 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 6216602836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6240104) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
37.sram_ctrl_executable.87812181259213072920893496857029163299745451998144504821209148566068812086101
Line 298, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 4344487629 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6240104) { a_addr: 'h421fe918 a_data: 'h1ae4e367 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha6 a_opcode: 'h4 a_user: 'h1bf48 d_param: 'h0 d_source: 'ha6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4344487629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@495019) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
39.sram_ctrl_executable.105839453443519714173083586762423439325143439667602065881123547186649526301854
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 342946029 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@495019) { a_addr: 'h832cc88 a_data: 'hf8743a0a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h1b2c7 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 342946029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496728) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
40.sram_ctrl_executable.53883016138316242211902929652229619844667738385992797765241766839666181128878
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 347459858 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496728) { a_addr: 'hcc36be3c a_data: 'h918e1b68 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1828e d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 347459858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@7417565) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
41.sram_ctrl_stress_all.16119315723433945965946486280066139996629634855858678549025798794468147760569
Line 374, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 19989994273 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@7417565) { a_addr: 'h2c72a578 a_data: 'ha1905c72 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h18b05 d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 19989994273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2179124) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
42.sram_ctrl_executable.47284817353641821122695200371241851526127331643955337696754114762413925877843
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 1516317359 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2179124) { a_addr: 'h26ae18c8 a_data: 'h745969a6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'had a_opcode: 'h4 a_user: 'h1838d d_param: 'h0 d_source: 'had d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1516317359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1932790) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
44.sram_ctrl_executable.56974665439768958335389383716871414556234196130419613399201322681369016471026
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 6295163298 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1932790) { a_addr: 'h14f651a0 a_data: 'h5eeb4aa2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf8 a_opcode: 'h4 a_user: 'h18809 d_param: 'h0 d_source: 'hf8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 6295163298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@11964596) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
47.sram_ctrl_executable.86238651811521290278011720883856479958194977537850215052267749871603599840255
Line 334, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 16970930468 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@11964596) { a_addr: 'h3b588944 a_data: 'ha8d2bec6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5a a_opcode: 'h4 a_user: 'h1bcf4 d_param: 'h0 d_source: 'h5a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 16970930468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3189761) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
47.sram_ctrl_stress_all.15763261622698267320261765530855339952546916980675302753685125694632415155591
Line 339, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 27669332852 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3189761) { a_addr: 'h3aa83b0c a_data: 'hca4fc0f1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hdf a_opcode: 'h4 a_user: 'h1b2e4 d_param: 'h0 d_source: 'hdf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 27669332852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@9959959) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
48.sram_ctrl_stress_all.67134206077967055907592046123152373732130571841171535629650545251401855190695
Line 340, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 7775803478 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@9959959) { a_addr: 'h105a6238 a_data: 'h2ccd510f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h41 a_opcode: 'h4 a_user: 'h198fb d_param: 'h0 d_source: 'h41 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 7775803478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496228) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
49.sram_ctrl_executable.104932699624399668023409251596980587434638926125860856183123148712311267511093
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 346193566 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496228) { a_addr: 'h48d5d84c a_data: 'hbc962652 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h9b a_opcode: 'h4 a_user: 'h18da4 d_param: 'h0 d_source: 'h9b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 346193566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---