0cdf265eaa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.672m | 5.474ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.660s | 20.938us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.690s | 14.129us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.450s | 941.026us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.750s | 38.957us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 5.720s | 2.965ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.690s | 14.129us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.750s | 38.957us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 5.629m | 111.655ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 2.661m | 10.406ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 205 | 205 | 100.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 33.140m | 180.457ms | 47 | 50 | 94.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.499m | 13.169ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 49.706m | 689.453ms | 49 | 50 | 98.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 4.126m | 9.683ms | 0 | 50 | 0.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 1.778m | 80.982ms | 42 | 50 | 84.00 |
| V2 | executable | sram_ctrl_executable | 33.561m | 41.914ms | 47 | 50 | 94.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.806m | 1.337ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 10.731m | 398.423ms | 49 | 50 | 98.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.356m | 3.026ms | 0 | 50 | 0.00 |
| sram_ctrl_throughput_w_partial_write | 2.765m | 2.985ms | 0 | 50 | 0.00 | ||
| V2 | regwen | sram_ctrl_regwen | 37.723m | 20.363ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 4.430s | 4.793ms | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.368h | 436.096ms | 37 | 50 | 74.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.740s | 20.427us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.760s | 936.579us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.760s | 936.579us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.660s | 20.938us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.690s | 14.129us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 38.957us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.790s | 48.377us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.660s | 20.938us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.690s | 14.129us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 38.957us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.790s | 48.377us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 561 | 740 | 75.81 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 55.610s | 29.377ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.360s | 2.955ms | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.770s | 1.434ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.360s | 2.955ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.770s | 1.434ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 37.723m | 20.363ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.690s | 14.129us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 33.561m | 41.914ms | 47 | 50 | 94.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 33.561m | 41.914ms | 47 | 50 | 94.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 33.561m | 41.914ms | 47 | 50 | 94.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 1.778m | 80.982ms | 42 | 50 | 84.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 55.610s | 29.377ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.672m | 5.474ms | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.672m | 5.474ms | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 33.561m | 41.914ms | 47 | 50 | 94.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.360s | 2.955ms | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 1.778m | 80.982ms | 42 | 50 | 84.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.360s | 2.955ms | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.360s | 2.955ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.672m | 5.474ms | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.360s | 2.955ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 7.603m | 4.211ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 861 | 1040 | 82.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 16 | 16 | 7 | 43.75 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.47 | 100.00 | 98.32 | 100.00 | 100.00 | 99.72 | 99.70 | 98.52 |
UVM_ERROR (sram_ctrl_throughput_vseq.sv:44) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) has 100 failures:
0.sram_ctrl_max_throughput.29966145862927153721762737723458588218389700200125308504268260025676357288793
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest/run.log
UVM_ERROR @ 694845443 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (1018 [0x3fa] vs 999 [0x3e7])
UVM_INFO @ 694845443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_max_throughput.16738125234507556398339996788607111790900368954641796698060486858793315686985
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest/run.log
UVM_ERROR @ 710953798 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (4722 [0x1272] vs 4464 [0x1170])
UVM_INFO @ 710953798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.sram_ctrl_throughput_w_partial_write.9445487871446776884164777921096987158516992114190762441040171124442346974178
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest/run.log
UVM_ERROR @ 12424695813 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (8893 [0x22bd] vs 8867 [0x22a3])
UVM_INFO @ 12424695813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_throughput_w_partial_write.82221334721176112464620028156104106539159629719408906287800744610936693430836
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest/run.log
UVM_ERROR @ 738943896 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (6914 [0x1b02] vs 6567 [0x19a7])
UVM_INFO @ 738943896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 50 failures:
0.sram_ctrl_access_during_key_req.48451425554498643639669215753006520556824623646750658187834851121784269222452
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 2589188993 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2b) != exp (0x51)
UVM_INFO @ 2589188993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_access_during_key_req.41223169811644642453939368736502666390602720799848420362348269053678181120120
Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 3268904934 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x5e) != exp (0x52)
UVM_INFO @ 3268904934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:415) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 13 failures:
Test sram_ctrl_executable has 3 failures.
6.sram_ctrl_executable.35990561198393984620435448893135865847830574077192227231455746482601788161338
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 8689879002 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 8689879002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.sram_ctrl_executable.60791186091664561748083655548329012100073023214138390992405896706421733891761
Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 10909679948 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 10909679948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sram_ctrl_lc_escalation has 4 failures.
8.sram_ctrl_lc_escalation.63590456902407676792546011338689818201828929499649027537879972326102275693970
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 1369956752 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 1369956752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sram_ctrl_lc_escalation.23506992453512409236808101447416546379403397306615894383301799654838935463513
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 5114464059 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 5114464059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test sram_ctrl_stress_all has 3 failures.
18.sram_ctrl_stress_all.38811544159458727612249087334231182395976515496807276350676430991642222370783
Line 363, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 59749856046 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 59749856046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sram_ctrl_stress_all.78104388075657194001872319764377026728087694531049448809865831961149801801664
Line 390, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 126787136305 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 126787136305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sram_ctrl_partial_access_b2b has 1 failures.
21.sram_ctrl_partial_access_b2b.78107483620298530151276596966327275612820058830330194222078172391964733596321
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest/run.log
UVM_ERROR @ 33828537447 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 33828537447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_multiple_keys has 2 failures.
24.sram_ctrl_multiple_keys.93504344275896546293930398264898205111620350754509131391209124476182259309849
Line 362, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 180457020168 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 180457020168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.sram_ctrl_multiple_keys.83371019346231403460607144896204609477184335473928284570112110901370657097257
Line 336, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 222463531844 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 222463531844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_scoreboard.sv:399) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 8 failures:
3.sram_ctrl_stress_all.30981125020334893385256519358674895181216056602382302727908532412366998236064
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 6270634085 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 6270634085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sram_ctrl_stress_all.88306811578395192783544202566744832541808969041271933736189422421791569034906
Line 328, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 34725636493 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 34725636493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
7.sram_ctrl_lc_escalation.103634169342243518514105309498971633350881106102154591954917654612523746743475
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 13708200924 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 13708200924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.sram_ctrl_lc_escalation.60611417415895685692114443817933398038721903765030670166636836425441664493581
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 2218829022 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 2218829022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (sram_ctrl_base_vseq.sv:102) [sram_ctrl_bijection_vseq] Timed out waiting for key request done has 5 failures:
12.sram_ctrl_stress_all.66898734470694806499239296633743944513593211713500574385143562201941946588383
Line 312, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 36728873947 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 36728873947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.sram_ctrl_stress_all.73112685601385244165790774353741399577579079647850849748529516363761986387871
Line 354, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 54601269738 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 54601269738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
47.sram_ctrl_bijection.96882109669357551385107607645016555928736537133056546490240825488115581218918
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 298173471504 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 298173471504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:
7.sram_ctrl_stress_all.39824283521171101040924698354423701958015550181157629764858751739250986369325
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 624897846 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 624897846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.sram_ctrl_stress_all.41219608225170944613426776123792915428310234916687068909849296407965303238723
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 1087289619 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 1087289619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
28.sram_ctrl_multiple_keys.37528243801989437598934274267435454309270374236427764218153738349257003970214
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest/run.log
UVM_FATAL @ 27626943719 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xdd5ab006
UVM_INFO @ 27626943719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---