Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14998247	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

143138609

1

T1

246211

T2

4587

T3

373200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	77566765	1			T1	135282		T2	2237		T3	205511
values[0x0]	38792260	1			T1	65338		T2	1140		T3	98875
values[0x1]	41777831	1			T1	70057		T2	1210		T3	106401

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7638950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150497906

1

T1

258448

T2

4587

T3

392106

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	531747	1			T1	1065		T3	1583		T4	3982
valid_sources[0x01]	535820	1			T1	1127		T3	1772		T4	3798
valid_sources[0x02]	515556	1			T1	1159		T3	1687		T4	3971
valid_sources[0x03]	539171	1			T1	1063		T3	1573		T4	4022
valid_sources[0x04]	525210	1			T1	1087		T3	1604		T4	4174
valid_sources[0x05]	1839784	1			T1	952		T3	1604		T4	3973
valid_sources[0x06]	523866	1			T1	1186		T3	1600		T4	3956
valid_sources[0x07]	487538	1			T1	1105		T3	1515		T4	3868
valid_sources[0x08]	482379	1			T1	1054		T3	1614		T4	3813
valid_sources[0x09]	525367	1			T1	1059		T3	1594		T4	3851
valid_sources[0x0a]	491969	1			T1	1065		T3	1589		T4	3912
valid_sources[0x0b]	551482	1			T1	1049		T3	1528		T4	4104
valid_sources[0x0c]	491971	1			T1	1082		T3	1590		T4	3899
valid_sources[0x0d]	502713	1			T1	1063		T3	1622		T4	3805
valid_sources[0x0e]	490127	1			T1	1137		T3	1646		T4	4001
valid_sources[0x0f]	492923	1			T1	1049		T3	1603		T4	3928
valid_sources[0x10]	520147	1			T1	1018		T3	1565		T4	3933
valid_sources[0x11]	513446	1			T1	1038		T3	1604		T4	4036
valid_sources[0x12]	505480	1			T1	1081		T3	1547		T4	3914
valid_sources[0x13]	536619	1			T1	1074		T3	1687		T4	3908
valid_sources[0x14]	487087	1			T1	1077		T3	1661		T4	3939
valid_sources[0x15]	507347	1			T1	1026		T3	1652		T4	4032
valid_sources[0x16]	505365	1			T1	1124		T3	1547		T4	3828
valid_sources[0x17]	501622	1			T1	1103		T3	1614		T4	4042
valid_sources[0x18]	543682	1			T1	1099		T3	1602		T4	3848
valid_sources[0x19]	519037	1			T1	1028		T3	1581		T4	3929
valid_sources[0x1a]	488474	1			T1	1076		T3	1548		T4	3970
valid_sources[0x1b]	517759	1			T1	1052		T3	1634		T4	4071
valid_sources[0x1c]	503424	1			T1	899		T3	1522		T4	4028
valid_sources[0x1d]	525420	1			T1	1081		T3	1605		T4	4064
valid_sources[0x1e]	1159964	1			T1	1054		T3	1531		T4	4003
valid_sources[0x1f]	487567	1			T1	1056		T3	1567		T4	3972
valid_sources[0x20]	678449	1			T1	1120		T3	1649		T4	3945
valid_sources[0x21]	1863236	1			T1	1048		T3	1572		T4	3935
valid_sources[0x22]	514424	1			T1	1101		T3	1645		T4	4109
valid_sources[0x23]	507216	1			T1	1186		T3	1621		T4	3867
valid_sources[0x24]	859053	1			T1	1124		T3	1694		T4	3974
valid_sources[0x25]	553030	1			T1	1047		T3	1534		T4	3997
valid_sources[0x26]	508975	1			T1	941		T3	1625		T4	3941
valid_sources[0x27]	528149	1			T1	959		T3	1562		T4	4035
valid_sources[0x28]	515473	1			T1	1122		T3	1612		T4	3982
valid_sources[0x29]	526448	1			T1	1030		T3	1586		T4	4106
valid_sources[0x2a]	786234	1			T1	1014		T3	1534		T4	3858
valid_sources[0x2b]	555637	1			T1	1055		T3	1562		T4	3832
valid_sources[0x2c]	596168	1			T1	974		T3	1641		T4	3929
valid_sources[0x2d]	565365	1			T1	1051		T3	1673		T4	3965
valid_sources[0x2e]	480441	1			T1	1060		T3	1541		T4	3978
valid_sources[0x2f]	500236	1			T1	1102		T3	1638		T4	3929
valid_sources[0x30]	543033	1			T1	1074		T3	1537		T4	3905
valid_sources[0x31]	503197	1			T1	1138		T3	1710		T4	3998
valid_sources[0x32]	507699	1			T1	1106		T3	1675		T4	4125
valid_sources[0x33]	486349	1			T1	996		T3	1640		T4	3930
valid_sources[0x34]	1226150	1			T1	977		T3	1621		T4	3868
valid_sources[0x35]	543691	1			T1	1192		T3	1617		T4	3919
valid_sources[0x36]	501682	1			T1	1113		T3	1604		T4	3844
valid_sources[0x37]	489590	1			T1	1009		T3	1584		T4	3859
valid_sources[0x38]	534479	1			T1	1107		T3	1692		T4	4084
valid_sources[0x39]	489389	1			T1	994		T3	1612		T4	3888
valid_sources[0x3a]	520440	1			T1	1043		T3	1604		T4	3863
valid_sources[0x3b]	560202	1			T1	1112		T3	1548		T4	4026
valid_sources[0x3c]	512591	1			T1	963		T3	1651		T4	3809
valid_sources[0x3d]	566168	1			T1	1044		T3	1551		T4	4050
valid_sources[0x3e]	564018	1			T1	987		T3	1644		T4	3755
valid_sources[0x3f]	533100	1			T1	982		T3	1610		T4	3968
valid_sources[0x40]	708713	1			T1	1068		T3	1636		T4	3839
valid_sources[0x41]	526301	1			T1	970		T3	1612		T4	4108
valid_sources[0x42]	515296	1			T1	1045		T3	1661		T4	3879
valid_sources[0x43]	482864	1			T1	1077		T3	1607		T4	3780
valid_sources[0x44]	528493	1			T1	1146		T3	1559		T4	3830
valid_sources[0x45]	555715	1			T1	1051		T3	1602		T4	3856
valid_sources[0x46]	492284	1			T1	1080		T3	1674		T4	3786
valid_sources[0x47]	483177	1			T1	1084		T3	1509		T4	4005
valid_sources[0x48]	512374	1			T1	1137		T3	1593		T4	3891
valid_sources[0x49]	513754	1			T1	1041		T3	1576		T4	3957
valid_sources[0x4a]	514014	1			T1	1068		T3	1606		T4	3843
valid_sources[0x4b]	488695	1			T1	1065		T3	1569		T4	3933
valid_sources[0x4c]	525733	1			T1	1034		T3	1568		T4	4017
valid_sources[0x4d]	541402	1			T1	973		T3	1553		T4	4011
valid_sources[0x4e]	552290	1			T1	921		T3	1642		T4	4004
valid_sources[0x4f]	482236	1			T1	1025		T3	1555		T4	4008
valid_sources[0x50]	550461	1			T1	1093		T3	1666		T4	3914
valid_sources[0x51]	505794	1			T1	1016		T3	1678		T4	3926
valid_sources[0x52]	576838	1			T1	1073		T3	1608		T4	3947
valid_sources[0x53]	558007	1			T1	1079		T3	1600		T4	3904
valid_sources[0x54]	504397	1			T1	1039		T3	1536		T4	4004
valid_sources[0x55]	515457	1			T1	1056		T3	1571		T4	4154
valid_sources[0x56]	554102	1			T1	1022		T3	1676		T4	3976
valid_sources[0x57]	506924	1			T1	1025		T3	1667		T4	3885
valid_sources[0x58]	1792254	1			T1	1051		T3	1679		T4	3981
valid_sources[0x59]	506487	1			T1	1025		T3	1581		T4	3743
valid_sources[0x5a]	517056	1			T1	1061		T3	1630		T4	3855
valid_sources[0x5b]	504597	1			T1	1070		T3	1563		T4	3908
valid_sources[0x5c]	556099	1			T1	1074		T3	1539		T4	3911
valid_sources[0x5d]	504282	1			T1	1020		T3	1603		T4	3832
valid_sources[0x5e]	489428	1			T1	938		T3	1697		T4	4040
valid_sources[0x5f]	602873	1			T1	999		T3	1577		T4	4045
valid_sources[0x60]	518926	1			T1	950		T3	1550		T4	3852
valid_sources[0x61]	487979	1			T1	1020		T3	1703		T4	3903
valid_sources[0x62]	477714	1			T1	976		T3	1516		T4	3983
valid_sources[0x63]	549843	1			T1	990		T3	1596		T4	3884
valid_sources[0x64]	483165	1			T1	1111		T3	1537		T4	3938
valid_sources[0x65]	509526	1			T1	1010		T3	1566		T4	3907
valid_sources[0x66]	504411	1			T1	1154		T3	1662		T4	4001
valid_sources[0x67]	524906	1			T1	1056		T3	1572		T4	3831
valid_sources[0x68]	501615	1			T1	954		T3	1652		T4	3709
valid_sources[0x69]	494243	1			T1	1083		T3	1598		T4	4008
valid_sources[0x6a]	514447	1			T1	1017		T3	1572		T4	4035
valid_sources[0x6b]	475891	1			T1	979		T3	1527		T4	4006
valid_sources[0x6c]	1699923	1			T1	1184		T3	1625		T4	3886
valid_sources[0x6d]	488164	1			T1	1012		T3	1693		T4	3919
valid_sources[0x6e]	521524	1			T1	1093		T3	1587		T4	3903
valid_sources[0x6f]	496950	1			T1	1048		T3	1550		T4	4046
valid_sources[0x70]	507770	1			T1	1028		T3	1605		T4	4016
valid_sources[0x71]	517503	1			T1	1040		T3	1781		T4	4041
valid_sources[0x72]	492677	1			T1	1064		T3	1555		T4	3957
valid_sources[0x73]	913488	1			T1	943		T3	1651		T4	3916
valid_sources[0x74]	523779	1			T1	1097		T3	1664		T4	3955
valid_sources[0x75]	499095	1			T1	1044		T3	1670		T4	3980
valid_sources[0x76]	553464	1			T1	1109		T3	1585		T4	3959
valid_sources[0x77]	539312	1			T1	1077		T3	1613		T4	3873
valid_sources[0x78]	529698	1			T1	1093		T3	1516		T4	3956
valid_sources[0x79]	535601	1			T1	1103		T2	2293		T3	1645
valid_sources[0x7a]	493400	1			T1	995		T3	1598		T4	3830
valid_sources[0x7b]	1852901	1			T1	1082		T3	1633		T4	4003
valid_sources[0x7c]	481111	1			T1	1002		T3	1661		T4	3885
valid_sources[0x7d]	576974	1			T1	989		T3	1690		T4	3812
valid_sources[0x7e]	562750	1			T1	963		T3	1521		T4	3976
valid_sources[0x7f]	494343	1			T1	1043		T3	1617		T4	3879
valid_sources[0x80]	1880569	1			T1	1039		T3	1756		T4	3928

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70025446

1

T1

122936

T2

2237

T3

186770

values[0x0]

all_enables

biggest_size

36556100

1

T1

61706

T2

1140

T3

93258

values[0x1]

all_enables

biggest_size

36557063

1

T1

61569

T2

1210

T3

93172

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

175797

1

T1

31

T3

32

T4

79

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	59283	1			T1	24		T3	12		T4	65
values[0x0]	71808	1			T1	39		T2	2		T3	44
values[0x1]	77160	1			T1	47		T3	32		T4	79

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

184432

1

T1

38

T3

35

T4

91

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1187	1			T4	1		T5	11		T20	39
valid_sources[0x01]	821	1			T4	1		T5	6		T20	20
valid_sources[0x02]	770	1			T5	10		T20	16		T7	1
valid_sources[0x03]	844	1			T5	11		T20	18		T45	5
valid_sources[0x04]	570	1			T5	10		T20	9		T45	3
valid_sources[0x05]	758	1			T4	1		T5	9		T6	53
valid_sources[0x06]	755	1			T5	18		T20	30		T16	1
valid_sources[0x07]	800	1			T5	11		T20	17		T45	1
valid_sources[0x08]	751	1			T3	2		T4	2		T5	22
valid_sources[0x09]	893	1			T4	1		T5	17		T20	14
valid_sources[0x0a]	1009	1			T5	12		T20	21		T7	1
valid_sources[0x0b]	674	1			T5	14		T20	4		T46	8
valid_sources[0x0c]	750	1			T5	14		T6	2		T20	14
valid_sources[0x0d]	931	1			T4	1		T5	19		T6	2
valid_sources[0x0e]	730	1			T9	1		T4	2		T5	17
valid_sources[0x0f]	703	1			T5	18		T6	1		T20	12
valid_sources[0x10]	707	1			T3	8		T4	3		T5	17
valid_sources[0x11]	857	1			T1	2		T5	14		T20	14
valid_sources[0x12]	735	1			T1	1		T4	1		T5	8
valid_sources[0x13]	663	1			T4	1		T5	11		T6	1
valid_sources[0x14]	638	1			T3	2		T4	2		T5	13
valid_sources[0x15]	721	1			T4	1		T5	11		T20	16
valid_sources[0x16]	714	1			T4	1		T5	8		T20	27
valid_sources[0x17]	1014	1			T4	1		T5	8		T6	1
valid_sources[0x18]	651	1			T4	1		T5	19		T20	11
valid_sources[0x19]	726	1			T1	3		T4	4		T5	20
valid_sources[0x1a]	836	1			T4	1		T5	24		T20	6
valid_sources[0x1b]	728	1			T4	2		T5	19		T6	2
valid_sources[0x1c]	684	1			T4	1		T5	22		T12	1
valid_sources[0x1d]	826	1			T4	2		T5	20		T20	11
valid_sources[0x1e]	626	1			T5	13		T20	8		T45	6
valid_sources[0x1f]	1009	1			T5	16		T20	19		T46	5
valid_sources[0x20]	681	1			T5	20		T20	20		T45	9
valid_sources[0x21]	886	1			T5	18		T20	24		T45	4
valid_sources[0x22]	1024	1			T4	2		T5	15		T6	41
valid_sources[0x23]	885	1			T5	12		T20	13		T45	4
valid_sources[0x24]	1075	1			T4	1		T5	10		T20	18
valid_sources[0x25]	920	1			T3	7		T5	11		T20	8
valid_sources[0x26]	839	1			T4	2		T5	26		T20	15
valid_sources[0x27]	653	1			T5	16		T20	12		T45	3
valid_sources[0x28]	756	1			T1	3		T5	14		T12	2
valid_sources[0x29]	900	1			T5	18		T6	35		T20	33
valid_sources[0x2a]	1241	1			T4	2		T5	11		T20	33
valid_sources[0x2b]	712	1			T5	15		T20	27		T45	5
valid_sources[0x2c]	847	1			T1	2		T4	2		T5	11
valid_sources[0x2d]	724	1			T4	2		T10	1		T5	19
valid_sources[0x2e]	805	1			T5	10		T6	1		T20	19
valid_sources[0x2f]	615	1			T1	1		T5	9		T20	18
valid_sources[0x30]	844	1			T4	1		T5	10		T20	18
valid_sources[0x31]	681	1			T4	1		T5	26		T6	1
valid_sources[0x32]	673	1			T11	1		T5	13		T20	23
valid_sources[0x33]	855	1			T4	1		T5	12		T20	8
valid_sources[0x34]	865	1			T4	1		T5	14		T6	3
valid_sources[0x35]	764	1			T5	14		T20	14		T45	10
valid_sources[0x36]	825	1			T3	1		T4	1		T5	11
valid_sources[0x37]	1178	1			T4	1		T5	11		T20	9
valid_sources[0x38]	1004	1			T5	14		T20	5		T45	5
valid_sources[0x39]	930	1			T4	2		T5	12		T20	18
valid_sources[0x3a]	912	1			T4	2		T5	15		T6	1
valid_sources[0x3b]	1080	1			T5	19		T6	21		T20	30
valid_sources[0x3c]	699	1			T4	3		T5	12		T6	1
valid_sources[0x3d]	667	1			T4	1		T5	11		T20	18
valid_sources[0x3e]	698	1			T5	11		T20	38		T45	2
valid_sources[0x3f]	658	1			T4	2		T5	15		T20	21
valid_sources[0x40]	759	1			T4	2		T5	16		T20	23
valid_sources[0x41]	1169	1			T1	6		T3	4		T5	9
valid_sources[0x42]	715	1			T4	1		T5	23		T20	24
valid_sources[0x43]	743	1			T4	2		T5	12		T20	34
valid_sources[0x44]	638	1			T5	26		T6	1		T20	19
valid_sources[0x45]	724	1			T5	9		T20	10		T46	6
valid_sources[0x46]	776	1			T1	3		T4	1		T5	12
valid_sources[0x47]	813	1			T4	2		T5	12		T6	87
valid_sources[0x48]	660	1			T5	20		T20	24		T45	3
valid_sources[0x49]	781	1			T4	3		T5	15		T20	12
valid_sources[0x4a]	783	1			T4	2		T5	12		T6	1
valid_sources[0x4b]	690	1			T5	19		T20	10		T51	1
valid_sources[0x4c]	778	1			T5	20		T20	19		T45	9
valid_sources[0x4d]	664	1			T4	1		T5	13		T20	17
valid_sources[0x4e]	660	1			T5	14		T20	7		T22	1
valid_sources[0x4f]	737	1			T5	15		T20	20		T45	5
valid_sources[0x50]	631	1			T4	1		T5	16		T20	12
valid_sources[0x51]	1005	1			T5	15		T20	10		T45	9
valid_sources[0x52]	1038	1			T5	18		T20	58		T45	4
valid_sources[0x53]	627	1			T4	2		T5	14		T20	10
valid_sources[0x54]	949	1			T1	11		T4	1		T5	13
valid_sources[0x55]	797	1			T5	18		T20	13		T7	2
valid_sources[0x56]	1460	1			T4	3		T5	21		T20	18
valid_sources[0x57]	1173	1			T5	24		T20	10		T44	1
valid_sources[0x58]	1023	1			T4	2		T5	12		T20	36
valid_sources[0x59]	739	1			T5	19		T6	1		T20	12
valid_sources[0x5a]	582	1			T4	4		T5	18		T20	22
valid_sources[0x5b]	761	1			T5	27		T6	7		T20	18
valid_sources[0x5c]	787	1			T4	1		T5	22		T20	11
valid_sources[0x5d]	741	1			T1	2		T4	1		T5	13
valid_sources[0x5e]	688	1			T4	2		T5	13		T20	21
valid_sources[0x5f]	808	1			T4	1		T5	9		T6	8
valid_sources[0x60]	776	1			T4	2		T5	14		T6	7
valid_sources[0x61]	1059	1			T4	2		T5	11		T20	20
valid_sources[0x62]	657	1			T4	2		T5	16		T20	10
valid_sources[0x63]	914	1			T5	10		T6	1		T20	20
valid_sources[0x64]	681	1			T4	1		T5	28		T20	28
valid_sources[0x65]	798	1			T4	4		T5	17		T20	23
valid_sources[0x66]	586	1			T5	12		T20	14		T46	9
valid_sources[0x67]	789	1			T4	1		T5	10		T6	1
valid_sources[0x68]	686	1			T3	3		T4	2		T5	27
valid_sources[0x69]	1098	1			T4	1		T5	5		T20	7
valid_sources[0x6a]	644	1			T5	14		T20	27		T45	2
valid_sources[0x6b]	684	1			T5	8		T20	25		T21	1
valid_sources[0x6c]	1201	1			T5	12		T20	44		T14	1
valid_sources[0x6d]	829	1			T1	5		T5	22		T20	37
valid_sources[0x6e]	717	1			T4	2		T5	16		T20	31
valid_sources[0x6f]	566	1			T5	14		T20	25		T14	1
valid_sources[0x70]	767	1			T5	11		T6	1		T20	25
valid_sources[0x71]	825	1			T4	1		T5	7		T6	4
valid_sources[0x72]	888	1			T4	1		T5	14		T6	26
valid_sources[0x73]	1207	1			T4	2		T5	4		T6	3
valid_sources[0x74]	1005	1			T4	1		T5	13		T6	19
valid_sources[0x75]	780	1			T4	1		T5	9		T20	3
valid_sources[0x76]	715	1			T5	14		T20	21		T45	6
valid_sources[0x77]	918	1			T4	1		T5	12		T6	1
valid_sources[0x78]	756	1			T4	1		T5	20		T6	44
valid_sources[0x79]	727	1			T4	1		T5	17		T20	33
valid_sources[0x7a]	714	1			T5	9		T6	31		T20	8
valid_sources[0x7b]	1107	1			T5	22		T6	55		T20	30
valid_sources[0x7c]	635	1			T5	15		T20	21		T45	10
valid_sources[0x7d]	707	1			T5	10		T20	18		T45	1
valid_sources[0x7e]	672	1			T4	1		T5	9		T20	2
valid_sources[0x7f]	806	1			T4	1		T5	14		T20	12
valid_sources[0x80]	962	1			T4	1		T5	10		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47233

1

T1

15

T3

4

T4

31

values[0x0]

all_enables

biggest_size

65016

1

T1

13

T3

22

T4

31

values[0x1]

all_enables

biggest_size

63548

1

T1

3

T3

6

T4

17