Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14994709

1

T1

20509

T3

36286

T4

44136

full_word

140387787

1

T1

207602

T2

4587

T3

359881

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	155382206	1			T1	228111		T2	4587		T3	396167
auto[TlIntgErrCmd]	104	1			T95	3		T96	6		T97	4
auto[TlIntgErrData]	86	1			T95	3		T97	3		T110	6
auto[TlIntgErrBoth]	100	1			T95	4		T96	4		T97	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74646381

1

T1

92716

T2

2237

T3

190891

auto[1]

80736115

1

T1

135395

T2

2350

T3

205276

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7326050	1			T1	8389		T3	17440		T4	19178
auto[TlIntgErrNone]	partial	auto[1]	7668391	1			T1	12120		T3	18846		T4	24958
auto[TlIntgErrNone]	full_word	auto[0]	67320201	1			T1	84327		T2	2237		T3	173451
auto[TlIntgErrNone]	full_word	auto[1]	73067564	1			T1	123275		T2	2350		T3	186430
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T95	1		T96	1		T97	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T95	1		T96	4		T97	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T97	1		T119	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T95	1		T96	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T95	2		T97	1		T110	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T95	1		T97	2		T110	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T117	1		T120	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T117	2		T118	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T95	1		T96	3		T97	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T95	3		T96	1		T97	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T110	1		T117	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T121	1		T112	1		-	-